riscv64: Cleanup trap handling (#7047)

* riscv64: Deduplicate Trap Instruction * riscv64: Use `defer_trap` in TrapIf instruction This places the actual trap opcode at the end. * riscv64: Emit islands before `br_table` sequence This fixes a slightly subtle issue with our island emission in BrTable. We used to emit islands right before the jump table targets. This causes issues because if the island is actually emitted, we have the potential to jump right into the middle of it. This happens because we have calculated a fixed offset from the `auipc` instruction assuming no island is emitted. This commit changes the island to be emitted right at the start of the br_table sequence so that this cannot happen. * riscv64: Add trapz and trapnz helpers * riscv64: Emit inline traps on `TrapIf`
1 year ago · 27345059c7
16 changed files with 130 additions and 153 deletions
--- a/cranelift/codegen/src/isa/riscv64/abi.rs
+++ b/cranelift/codegen/src/isa/riscv64/abi.rs
@ -290,7 +290,7 @@ impl ABIMachineSpec for Riscv64MachineDeps {

    fn gen_stack_lower_bound_trap(limit_reg: Reg) -> SmallInstVec<Inst> {
        let mut insts = SmallVec::new();
-        insts.push(Inst::TrapIfC {
+        insts.push(Inst::TrapIf {
            cc: IntCC::UnsignedLessThan,
            rs1: stack_reg(),
            rs2: limit_reg,
--- a/cranelift/codegen/src/isa/riscv64/inst.isle
+++ b/cranelift/codegen/src/isa/riscv64/inst.isle
@ -122,12 +122,8 @@
      (callee Reg)
      (info BoxReturnCallInfo))

+    ;; Emits a trap with the given trap code if the comparison succeeds
    (TrapIf
-      (test Reg)
-      (trap_code TrapCode))
-
-    ;; use a simple compare to decide to cause trap or not.
-    (TrapIfC
      (rs1 Reg)
      (rs2 Reg)
      (cc IntCC)
@ -2877,36 +2873,39 @@
  (gen_select_reg (IntCC.SignedGreaterThan) x y x y))


-(decl gen_trapif (XReg TrapCode) InstOutput)
-(rule
-  (gen_trapif test trap_code)
-  (side_effect (SideEffectNoResult.Inst (MInst.TrapIf test trap_code))))
+;; Builds an instruction sequence that traps if the comparision succeeds.
+(decl gen_trapif (IntCC XReg XReg TrapCode) InstOutput)
+(rule (gen_trapif cc a b trap_code)
+  (side_effect (SideEffectNoResult.Inst (MInst.TrapIf a b cc trap_code))))
+
+;; Builds an instruction sequence that traps if the input is non-zero.
+(decl gen_trapnz (XReg TrapCode) InstOutput)
+(rule (gen_trapnz test trap_code)
+  (gen_trapif (IntCC.NotEqual) test (zero_reg) trap_code))
+
+;; Builds an instruction sequence that traps if the input is zero.
+(decl gen_trapz (XReg TrapCode) InstOutput)
+(rule (gen_trapz test trap_code)
+  (gen_trapif (IntCC.Equal) test (zero_reg) trap_code))

-(decl gen_trapifc (IntCC XReg XReg TrapCode) InstOutput)
-(rule
-  (gen_trapifc cc a b trap_code)
-  (side_effect (SideEffectNoResult.Inst (MInst.TrapIfC a b cc trap_code))))

 (decl shift_int_to_most_significant (XReg Type) XReg)
 (extern constructor shift_int_to_most_significant shift_int_to_most_significant)

 ;;; generate div overflow.
 (decl gen_div_overflow (XReg XReg Type) InstOutput)
-(rule
-  (gen_div_overflow rs1 rs2 ty)
-  (let
-    ((r_const_neg_1 XReg (imm $I64 (i64_as_u64 -1)))
-      (r_const_min XReg (rv_slli (imm $I64 1) (imm12_const 63)))
-      (tmp_rs1 XReg (shift_int_to_most_significant rs1 ty))
-      (t1 XReg (gen_icmp (IntCC.Equal) r_const_neg_1 rs2 ty))
-      (t2 XReg (gen_icmp (IntCC.Equal) r_const_min tmp_rs1 ty))
-      (test XReg (rv_and t1 t2)))
-    (gen_trapif test (TrapCode.IntegerOverflow))))
+(rule (gen_div_overflow rs1 rs2 ty)
+  (let ((r_const_neg_1 XReg (imm $I64 (i64_as_u64 -1)))
+        (r_const_min XReg (rv_slli (imm $I64 1) (imm12_const 63)))
+        (tmp_rs1 XReg (shift_int_to_most_significant rs1 ty))
+        (t1 XReg (gen_icmp (IntCC.Equal) r_const_neg_1 rs2 ty))
+        (t2 XReg (gen_icmp (IntCC.Equal) r_const_min tmp_rs1 ty))
+        (test XReg (rv_and t1 t2)))
+    (gen_trapnz test (TrapCode.IntegerOverflow))))

 (decl gen_div_by_zero (XReg) InstOutput)
-(rule
-  (gen_div_by_zero r)
-  (gen_trapifc (IntCC.Equal) (zero_reg) r (TrapCode.IntegerDivisionByZero)))
+(rule (gen_div_by_zero r)
+  (gen_trapz r (TrapCode.IntegerDivisionByZero)))

 ;;;; Helpers for Emitting Calls ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

--- a/cranelift/codegen/src/isa/riscv64/inst/emit.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/emit.rs
@ -339,7 +339,6 @@ impl Inst {
            | Inst::CallInd { .. }
            | Inst::ReturnCall { .. }
            | Inst::ReturnCallInd { .. }
-            | Inst::TrapIf { .. }
            | Inst::Jal { .. }
            | Inst::CondBr { .. }
            | Inst::LoadExtName { .. }
@ -365,7 +364,7 @@ impl Inst {
            | Inst::AtomicStore { .. }
            | Inst::AtomicLoad { .. }
            | Inst::AtomicRmwLoop { .. }
-            | Inst::TrapIfC { .. }
+            | Inst::TrapIf { .. }
            | Inst::Unwind { .. }
            | Inst::DummyUse { .. }
            | Inst::FloatRound { .. }
@ -1097,6 +1096,20 @@ impl Inst {
                let default_target = targets[0];
                let targets = &targets[1..];

+                // We are going to potentially emit a large amount of instructions, so ensure that we emit an island
+                // now if we need one.
+                //
+                // The worse case PC calculations are 12 instructions. And each entry in the jump table is 2 instructions.
+                // Check if we need to emit a jump table here to support that jump.
+                let inst_count = 12 + (targets.len() * 2);
+                let distance = (inst_count * Inst::UNCOMPRESSED_INSTRUCTION_SIZE as usize) as u32;
+                if sink.island_needed(distance) {
+                    let jump_around_label = sink.get_label();
+                    Inst::gen_jump(jump_around_label).emit(&[], sink, emit_info, state);
+                    sink.emit_island(distance + 4, &mut state.ctrl_plane);
+                    sink.bind_label(jump_around_label, &mut state.ctrl_plane);
+                }
+
                // We emit a bounds check on the index, if the index is larger than the number of
                // jump table entries, we jump to the default block.  Otherwise we compute a jump
                // offset by multiplying the index by 8 (the size of each entry) and then jump to
@ -1204,17 +1217,9 @@ impl Inst {

                // Emit the jump table.
                //
-                // Each entry is a aupc + jalr to the target block. We also start with a island
+                // Each entry is a auipc + jalr to the target block. We also start with a island
                // if necessary.

-                // Each entry in the jump table is 2 instructions, so 8 bytes. Check if
-                // we need to emit a jump table here to support that jump.
-                let distance =
-                    (targets.len() * 2 * Inst::UNCOMPRESSED_INSTRUCTION_SIZE as usize) as u32;
-                if sink.island_needed(distance) {
-                    sink.emit_island(distance, &mut state.ctrl_plane);
-                }
-
                // Emit the jumps back to back
                for target in targets.iter() {
                    sink.use_label_at_offset(sink.cur_offset(), *target, LabelUse::PCRel32);
@ -1824,7 +1829,9 @@ impl Inst {
                    }
                    .emit(&[], sink, emit_info, state);
                    Inst::TrapIf {
-                        test: rd.to_reg(),
+                        cc: IntCC::NotEqual,
+                        rs1: rd.to_reg(),
+                        rs2: zero_reg(),
                        trap_code: TrapCode::IntegerOverflow,
                    }
                    .emit(&[], sink, emit_info, state);
@ -1852,7 +1859,9 @@ impl Inst {
                    .emit(&[], sink, emit_info, state);

                    Inst::TrapIf {
-                        test: rd.to_reg(),
+                        cc: IntCC::NotEqual,
+                        rs1: rd.to_reg(),
+                        rs2: zero_reg(),
                        trap_code: TrapCode::IntegerOverflow,
                    }
                    .emit(&[], sink, emit_info, state);
@ -2013,45 +2022,25 @@ impl Inst {
                .emit_uncompressed(sink, emit_info, state, start_off);
            }

-            &Inst::TrapIfC {
+            &Inst::TrapIf {
                rs1,
                rs2,
                cc,
                trap_code,
            } => {
-                let label_trap = sink.get_label();
-                let label_jump_over = sink.get_label();
+                let label_end = sink.get_label();
+                let cond = IntegerCompare { kind: cc, rs1, rs2 };
+
+                // Jump over the trap if we the condition is false.
                Inst::CondBr {
-                    taken: CondBrTarget::Label(label_trap),
-                    not_taken: CondBrTarget::Label(label_jump_over),
-                    kind: IntegerCompare { kind: cc, rs1, rs2 },
+                    taken: CondBrTarget::Label(label_end),
+                    not_taken: CondBrTarget::Fallthrough,
+                    kind: cond.inverse(),
                }
                .emit(&[], sink, emit_info, state);
-                // trap
-                sink.bind_label(label_trap, &mut state.ctrl_plane);
                Inst::Udf { trap_code }.emit(&[], sink, emit_info, state);
-                sink.bind_label(label_jump_over, &mut state.ctrl_plane);
-            }
-            &Inst::TrapIf { test, trap_code } => {
-                let label_trap = sink.get_label();
-                let label_jump_over = sink.get_label();
-                Inst::CondBr {
-                    taken: CondBrTarget::Label(label_trap),
-                    not_taken: CondBrTarget::Label(label_jump_over),
-                    kind: IntegerCompare {
-                        kind: IntCC::NotEqual,
-                        rs1: test,
-                        rs2: zero_reg(),
-                    },
-                }
-                .emit(&[], sink, emit_info, state);
-                // trap
-                sink.bind_label(label_trap, &mut state.ctrl_plane);
-                Inst::Udf {
-                    trap_code: trap_code,
-                }
-                .emit(&[], sink, emit_info, state);
-                sink.bind_label(label_jump_over, &mut state.ctrl_plane);
+
+                sink.bind_label(label_end, &mut state.ctrl_plane);
            }
            &Inst::Udf { trap_code } => {
                sink.add_trap(trap_code);
@ -3334,23 +3323,18 @@ impl Inst {
                Inst::ElfTlsGetAddr { rd, name }
            }

-            Inst::TrapIfC {
+            Inst::TrapIf {
                rs1,
                rs2,
                cc,
                trap_code,
-            } => Inst::TrapIfC {
+            } => Inst::TrapIf {
                rs1: allocs.next(rs1),
                rs2: allocs.next(rs2),
                cc,
                trap_code,
            },

-            Inst::TrapIf { test, trap_code } => Inst::TrapIf {
-                test: allocs.next(test),
-                trap_code,
-            },
-
            Inst::Udf { .. } => self,

            Inst::AtomicLoad { rd, ty, p } => Inst::AtomicLoad {
--- a/cranelift/codegen/src/isa/riscv64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/mod.rs
@ -459,9 +459,6 @@ fn riscv64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
                collector.reg_fixed_use(u.vreg, u.preg);
            }
        }
-        &Inst::TrapIf { test, .. } => {
-            collector.reg_use(test);
-        }
        &Inst::Jal { .. } => {
            // JAL technically has a rd register, but we currently always
            // hardcode it to x0.
@ -603,7 +600,7 @@ fn riscv64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
            collector.reg_early_def(t0);
            collector.reg_early_def(dst);
        }
-        &Inst::TrapIfC { rs1, rs2, .. } => {
+        &Inst::TrapIf { rs1, rs2, .. } => {
            collector.reg_use(rs1);
            collector.reg_use(rs2);
        }
@ -1635,10 +1632,7 @@ impl Inst {
                }
                s
            }
-            &MInst::TrapIf { test, trap_code } => {
-                format!("trap_if {},{}", format_reg(test, allocs), trap_code,)
-            }
-            &MInst::TrapIfC {
+            &MInst::TrapIf {
                rs1,
                rs2,
                cc,
@ -1646,7 +1640,7 @@ impl Inst {
            } => {
                let rs1 = format_reg(rs1, allocs);
                let rs2 = format_reg(rs2, allocs);
-                format!("trap_ifc {}##({} {} {})", trap_code, rs1, cc, rs2)
+                format!("trap_if {trap_code}##({rs1} {cc} {rs2})")
            }
            &MInst::Jal { label } => {
                format!("j {}", label.to_string())
--- a/cranelift/codegen/src/isa/riscv64/lower.isle
+++ b/cranelift/codegen/src/isa/riscv64/lower.isle
@ -297,7 +297,7 @@
 (rule
  (lower (has_type (fits_in_64 ty) (uadd_overflow_trap x y tc)))
  (let ((res ValueRegs (lower_uadd_overflow x y ty))
-        (_ InstOutput (gen_trapif (value_regs_get res 1) tc)))
+        (_ InstOutput (gen_trapnz (value_regs_get res 1) tc)))
    (value_regs_get res 0)))


--- a/cranelift/filetests/filetests/isa/riscv64/arithmetic.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/arithmetic.clif
@ -96,8 +96,8 @@ block0(v0: i64, v1: i64):
 ;   eq a3,a3,a1##ty=i64
 ;   eq a5,a2,a0##ty=i64
 ;   and a2,a3,a5
-;   trap_if a2,int_ovf
-;   trap_ifc int_divz##(zero eq a1)
+;   trap_if int_ovf##(a2 ne zero)
+;   trap_if int_divz##(a1 eq zero)
 ;   div a0,a0,a1
 ;   ret
 ;
@ -117,7 +117,7 @@ block0(v0: i64, v1: i64):
 ;   and a2, a3, a5
 ;   beqz a2, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
-;   bne zero, a1, 8
+;   bnez a1, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
 ;   div a0, a0, a1
 ;   ret
@ -138,8 +138,8 @@ block0(v0: i64):
 ;   eq a4,a4,a3##ty=i64
 ;   eq a5,a1,a0##ty=i64
 ;   and a1,a4,a5
-;   trap_if a1,int_ovf
-;   trap_ifc int_divz##(zero eq a3)
+;   trap_if int_ovf##(a1 ne zero)
+;   trap_if int_divz##(a3 eq zero)
 ;   div a0,a0,a3
 ;   ret
 ;
@ -160,7 +160,7 @@ block0(v0: i64):
 ;   and a1, a4, a5
 ;   beqz a1, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
-;   bne zero, a3, 8
+;   bnez a3, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
 ;   div a0, a0, a3
 ;   ret
@ -173,13 +173,13 @@ block0(v0: i64, v1: i64):

 ; VCode:
 ; block0:
-;   trap_ifc int_divz##(zero eq a1)
+;   trap_if int_divz##(a1 eq zero)
 ;   divu a0,a0,a1
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bne zero, a1, 8
+;   bnez a1, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
 ;   divu a0, a0, a1
 ;   ret
@ -194,14 +194,14 @@ block0(v0: i64):
 ; VCode:
 ; block0:
 ;   li a3,2
-;   trap_ifc int_divz##(zero eq a3)
+;   trap_if int_divz##(a3 eq zero)
 ;   divu a0,a0,a3
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   addi a3, zero, 2
-;   bne zero, a3, 8
+;   bnez a3, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
 ;   divu a0, a0, a3
 ;   ret
@ -214,13 +214,13 @@ block0(v0: i64, v1: i64):

 ; VCode:
 ; block0:
-;   trap_ifc int_divz##(zero eq a1)
+;   trap_if int_divz##(a1 eq zero)
 ;   rem a0,a0,a1
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bne zero, a1, 8
+;   bnez a1, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
 ;   rem a0, a0, a1
 ;   ret
@ -233,13 +233,13 @@ block0(v0: i64, v1: i64):

 ; VCode:
 ; block0:
-;   trap_ifc int_divz##(zero eq a1)
+;   trap_if int_divz##(a1 eq zero)
 ;   remu a0,a0,a1
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bne zero, a1, 8
+;   bnez a1, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
 ;   remu a0, a0, a1
 ;   ret
@ -261,8 +261,8 @@ block0(v0: i32, v1: i32):
 ;   eq a4,a1,a5##ty=i32
 ;   eq a0,a0,a2##ty=i32
 ;   and a1,a4,a0
-;   trap_if a1,int_ovf
-;   trap_ifc int_divz##(zero eq a5)
+;   trap_if int_ovf##(a1 ne zero)
+;   trap_if int_divz##(a5 eq zero)
 ;   divw a0,a3,a5
 ;   ret
 ;
@ -285,7 +285,7 @@ block0(v0: i32, v1: i32):
 ;   and a1, a4, a0
 ;   beqz a1, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
-;   bne zero, a5, 8
+;   bnez a5, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
 ;   divw a0, a3, a5
 ;   ret
@ -310,8 +310,8 @@ block0(v0: i32):
 ;   eq a4,a1,a5##ty=i32
 ;   eq a0,a0,a2##ty=i32
 ;   and a1,a4,a0
-;   trap_if a1,int_ovf
-;   trap_ifc int_divz##(zero eq a5)
+;   trap_if int_ovf##(a1 ne zero)
+;   trap_if int_divz##(a5 eq zero)
 ;   divw a0,a3,a5
 ;   ret
 ;
@ -336,7 +336,7 @@ block0(v0: i32):
 ;   and a1, a4, a0
 ;   beqz a1, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
-;   bne zero, a5, 8
+;   bnez a5, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
 ;   divw a0, a3, a5
 ;   ret
@ -351,7 +351,7 @@ block0(v0: i32, v1: i32):
 ; block0:
 ;   slli a3,a1,32
 ;   srli a5,a3,32
-;   trap_ifc int_divz##(zero eq a5)
+;   trap_if int_divz##(a5 eq zero)
 ;   slli a2,a0,32
 ;   srli a4,a2,32
 ;   divuw a0,a4,a5
@ -361,7 +361,7 @@ block0(v0: i32, v1: i32):
 ; block0: ; offset 0x0
 ;   slli a3, a1, 0x20
 ;   srli a5, a3, 0x20
-;   bne zero, a5, 8
+;   bnez a5, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
 ;   slli a2, a0, 0x20
 ;   srli a4, a2, 0x20
@ -380,7 +380,7 @@ block0(v0: i32):
 ;   li a1,2
 ;   slli a3,a1,32
 ;   srli a5,a3,32
-;   trap_ifc int_divz##(zero eq a5)
+;   trap_if int_divz##(a5 eq zero)
 ;   slli a2,a0,32
 ;   srli a4,a2,32
 ;   divuw a0,a4,a5
@ -391,7 +391,7 @@ block0(v0: i32):
 ;   addi a1, zero, 2
 ;   slli a3, a1, 0x20
 ;   srli a5, a3, 0x20
-;   bne zero, a5, 8
+;   bnez a5, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
 ;   slli a2, a0, 0x20
 ;   srli a4, a2, 0x20
@ -407,14 +407,14 @@ block0(v0: i32, v1: i32):
 ; VCode:
 ; block0:
 ;   sext.w a3,a1
-;   trap_ifc int_divz##(zero eq a3)
+;   trap_if int_divz##(a3 eq zero)
 ;   remw a0,a0,a3
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   sext.w a3, a1
-;   bne zero, a3, 8
+;   bnez a3, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
 ;   remw a0, a0, a3
 ;   ret
@ -429,7 +429,7 @@ block0(v0: i32, v1: i32):
 ; block0:
 ;   slli a3,a1,32
 ;   srli a5,a3,32
-;   trap_ifc int_divz##(zero eq a5)
+;   trap_if int_divz##(a5 eq zero)
 ;   remuw a0,a0,a5
 ;   ret
 ;
@ -437,7 +437,7 @@ block0(v0: i32, v1: i32):
 ; block0: ; offset 0x0
 ;   slli a3, a1, 0x20
 ;   srli a5, a3, 0x20
-;   bne zero, a5, 8
+;   bnez a5, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
 ;   remuw a0, a0, a5
 ;   ret
@ -807,14 +807,14 @@ block0(v0: i64):
 ; VCode:
 ; block0:
 ;   li a3,2
-;   trap_ifc int_divz##(zero eq a3)
+;   trap_if int_divz##(a3 eq zero)
 ;   rem a0,a0,a3
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   addi a3, zero, 2
-;   bne zero, a3, 8
+;   bnez a3, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
 ;   rem a0, a0, a3
 ;   ret
@ -829,14 +829,14 @@ block0(v0: i64):
 ; VCode:
 ; block0:
 ;   li a3,2
-;   trap_ifc int_divz##(zero eq a3)
+;   trap_if int_divz##(a3 eq zero)
 ;   remu a0,a0,a3
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   addi a3, zero, 2
-;   bne zero, a3, 8
+;   bnez a3, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
 ;   remu a0, a0, a3
 ;   ret
@ -857,8 +857,8 @@ block0(v0: i64):
 ;   eq a4,a4,a3##ty=i64
 ;   eq a5,a1,a0##ty=i64
 ;   and a1,a4,a5
-;   trap_if a1,int_ovf
-;   trap_ifc int_divz##(zero eq a3)
+;   trap_if int_ovf##(a1 ne zero)
+;   trap_if int_divz##(a3 eq zero)
 ;   div a0,a0,a3
 ;   ret
 ;
@ -879,7 +879,7 @@ block0(v0: i64):
 ;   and a1, a4, a5
 ;   beqz a1, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
-;   bne zero, a3, 8
+;   bnez a3, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
 ;   div a0, a0, a3
 ;   ret
--- a/cranelift/filetests/filetests/isa/riscv64/stack-limit.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/stack-limit.clif
@ -58,7 +58,7 @@ block0(v0: i64):
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   trap_ifc stk_ovf##(sp ult a0)
+;   trap_if stk_ovf##(sp ult a0)
 ; block0:
 ;   load_sym a2,%foo+0
 ;   callind a2
@ -105,7 +105,7 @@ block0(v0: i64):
 ;   mv fp,sp
 ;   ld t6,0(a0)
 ;   ld t6,4(t6)
-;   trap_ifc stk_ovf##(sp ult t6)
+;   trap_if stk_ovf##(sp ult t6)
 ; block0:
 ;   load_sym a2,%foo+0
 ;   callind a2
@ -148,7 +148,7 @@ block0(v0: i64):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ;   addi t6,a0,176
-;   trap_ifc stk_ovf##(sp ult t6)
+;   trap_if stk_ovf##(sp ult t6)
 ;   add sp,-176
 ; block0:
 ;   add sp,+176
@ -185,11 +185,11 @@ block0(v0: i64):
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   trap_ifc stk_ovf##(sp ult a0)
+;   trap_if stk_ovf##(sp ult a0)
 ;   lui t5,98
 ;   addi t5,t5,-1408
 ;   add t6,t5,a0
-;   trap_ifc stk_ovf##(sp ult t6)
+;   trap_if stk_ovf##(sp ult t6)
 ;   lui a0,98
 ;   addi a0,a0,-1408
 ;   call %Probestack
@ -252,7 +252,7 @@ block0(v0: i64):
 ;   ld t6,0(a0)
 ;   ld t6,4(t6)
 ;   addi t6,t6,32
-;   trap_ifc stk_ovf##(sp ult t6)
+;   trap_if stk_ovf##(sp ult t6)
 ;   add sp,-32
 ; block0:
 ;   add sp,+32
@ -297,11 +297,11 @@ block0(v0: i64):
 ;   mv fp,sp
 ;   ld t6,0(a0)
 ;   ld t6,4(t6)
-;   trap_ifc stk_ovf##(sp ult t6)
+;   trap_if stk_ovf##(sp ult t6)
 ;   lui t5,98
 ;   addi t5,t5,-1408
 ;   add t6,t5,t6
-;   trap_ifc stk_ovf##(sp ult t6)
+;   trap_if stk_ovf##(sp ult t6)
 ;   lui a0,98
 ;   addi a0,a0,-1408
 ;   call %Probestack
@ -364,7 +364,7 @@ block0(v0: i64):
 ;   mv fp,sp
 ;   ld t6,400000(a0)
 ;   addi t6,t6,32
-;   trap_ifc stk_ovf##(sp ult t6)
+;   trap_if stk_ovf##(sp ult t6)
 ;   add sp,-32
 ; block0:
 ;   add sp,+32
--- a/cranelift/filetests/filetests/isa/riscv64/uadd_overflow_trap.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/uadd_overflow_trap.clif
@ -17,7 +17,7 @@ block0(v0: i32):
 ;   srli a3,a1,32
 ;   add a0,a5,a3
 ;   srli a1,a0,32
-;   trap_if a1,user0
+;   trap_if user0##(a1 ne zero)
 ;   ret
 ;
 ; Disassembled:
@ -49,7 +49,7 @@ block0(v0: i32):
 ;   srli a3,a1,32
 ;   add a0,a5,a3
 ;   srli a1,a0,32
-;   trap_if a1,user0
+;   trap_if user0##(a1 ne zero)
 ;   ret
 ;
 ; Disassembled:
@ -79,7 +79,7 @@ block0(v0: i32, v1: i32):
 ;   srli a3,a1,32
 ;   add a0,a5,a3
 ;   srli a1,a0,32
-;   trap_if a1,user0
+;   trap_if user0##(a1 ne zero)
 ;   ret
 ;
 ; Disassembled:
@ -107,7 +107,7 @@ block0(v0: i64):
 ;   li a4,127
 ;   add a0,a1,a4
 ;   ult a5,a0,a1##ty=i64
-;   trap_if a5,user0
+;   trap_if user0##(a5 ne zero)
 ;   ret
 ;
 ; Disassembled:
@ -135,7 +135,7 @@ block0(v0: i64):
 ;   li a4,127
 ;   add a0,a4,a0
 ;   ult a5,a0,a4##ty=i64
-;   trap_if a5,user0
+;   trap_if user0##(a5 ne zero)
 ;   ret
 ;
 ; Disassembled:
@ -162,7 +162,7 @@ block0(v0: i64, v1: i64):
 ;   mv a1,a3
 ;   ult a5,a1,a0##ty=i64
 ;   mv a0,a1
-;   trap_if a5,user0
+;   trap_if user0##(a5 ne zero)
 ;   ret
 ;
 ; Disassembled:
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
@ -46,7 +46,7 @@
 ;;   ld a4,[const(1)]
 ;;   add a4,a3,a4
 ;;   ult a5,a4,a3##ty=i64
-;;   trap_if a5,heap_oob
+;;   trap_if heap_oob##(a5 ne zero)
 ;;   ld a5,8(a2)
 ;;   ugt a4,a4,a5##ty=i64
 ;;   bne a4,zero,taken(label3),not_taken(label1)
@ -69,7 +69,7 @@
 ;;   ld a2,[const(1)]
 ;;   add a2,a3,a2
 ;;   ult a4,a2,a3##ty=i64
-;;   trap_if a4,heap_oob
+;;   trap_if heap_oob##(a4 ne zero)
 ;;   ld a4,8(a1)
 ;;   ugt a4,a2,a4##ty=i64
 ;;   bne a4,zero,taken(label3),not_taken(label1)
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@ -46,7 +46,7 @@
 ;;   ld a4,[const(1)]
 ;;   add a4,a3,a4
 ;;   ult a5,a4,a3##ty=i64
-;;   trap_if a5,heap_oob
+;;   trap_if heap_oob##(a5 ne zero)
 ;;   ld a5,8(a2)
 ;;   ugt a4,a4,a5##ty=i64
 ;;   bne a4,zero,taken(label3),not_taken(label1)
@ -69,7 +69,7 @@
 ;;   ld a2,[const(1)]
 ;;   add a2,a3,a2
 ;;   ult a4,a2,a3##ty=i64
-;;   trap_if a4,heap_oob
+;;   trap_if heap_oob##(a4 ne zero)
 ;;   ld a4,8(a1)
 ;;   ugt a4,a2,a4##ty=i64
 ;;   bne a4,zero,taken(label3),not_taken(label1)
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@ -46,7 +46,7 @@
 ;;   ld a4,[const(1)]
 ;;   add a3,a5,a4
 ;;   ult a0,a3,a5##ty=i64
-;;   trap_if a0,heap_oob
+;;   trap_if heap_oob##(a0 ne zero)
 ;;   ld a0,8(a2)
 ;;   ugt a0,a3,a0##ty=i64
 ;;   ld a2,0(a2)
@ -73,7 +73,7 @@
 ;;   ld a4,[const(1)]
 ;;   add a3,a5,a4
 ;;   ult a0,a3,a5##ty=i64
-;;   trap_if a0,heap_oob
+;;   trap_if heap_oob##(a0 ne zero)
 ;;   ld a0,8(a1)
 ;;   ugt a0,a3,a0##ty=i64
 ;;   ld a1,0(a1)
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@ -46,7 +46,7 @@
 ;;   ld a4,[const(1)]
 ;;   add a3,a5,a4
 ;;   ult a0,a3,a5##ty=i64
-;;   trap_if a0,heap_oob
+;;   trap_if heap_oob##(a0 ne zero)
 ;;   ld a0,8(a2)
 ;;   ugt a0,a3,a0##ty=i64
 ;;   ld a2,0(a2)
@ -73,7 +73,7 @@
 ;;   ld a4,[const(1)]
 ;;   add a3,a5,a4
 ;;   ult a0,a3,a5##ty=i64
-;;   trap_if a0,heap_oob
+;;   trap_if heap_oob##(a0 ne zero)
 ;;   ld a0,8(a1)
 ;;   ugt a0,a3,a0##ty=i64
 ;;   ld a1,0(a1)
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
@ -44,7 +44,7 @@
 ;;   ld a3,[const(1)]
 ;;   add a5,a0,a3
 ;;   ult a3,a5,a0##ty=i64
-;;   trap_if a3,heap_oob
+;;   trap_if heap_oob##(a3 ne zero)
 ;;   ld a3,8(a2)
 ;;   ugt a3,a5,a3##ty=i64
 ;;   bne a3,zero,taken(label3),not_taken(label1)
@ -65,7 +65,7 @@
 ;;   ld a2,[const(1)]
 ;;   add a5,a0,a2
 ;;   ult a2,a5,a0##ty=i64
-;;   trap_if a2,heap_oob
+;;   trap_if heap_oob##(a2 ne zero)
 ;;   ld a2,8(a1)
 ;;   ugt a2,a5,a2##ty=i64
 ;;   bne a2,zero,taken(label3),not_taken(label1)
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@ -44,7 +44,7 @@
 ;;   ld a3,[const(1)]
 ;;   add a5,a0,a3
 ;;   ult a3,a5,a0##ty=i64
-;;   trap_if a3,heap_oob
+;;   trap_if heap_oob##(a3 ne zero)
 ;;   ld a3,8(a2)
 ;;   ugt a3,a5,a3##ty=i64
 ;;   bne a3,zero,taken(label3),not_taken(label1)
@ -65,7 +65,7 @@
 ;;   ld a2,[const(1)]
 ;;   add a5,a0,a2
 ;;   ult a2,a5,a0##ty=i64
-;;   trap_if a2,heap_oob
+;;   trap_if heap_oob##(a2 ne zero)
 ;;   ld a2,8(a1)
 ;;   ugt a2,a5,a2##ty=i64
 ;;   bne a2,zero,taken(label3),not_taken(label1)
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@ -44,7 +44,7 @@
 ;;   ld a3,[const(1)]
 ;;   add a3,a0,a3
 ;;   ult a4,a3,a0##ty=i64
-;;   trap_if a4,heap_oob
+;;   trap_if heap_oob##(a4 ne zero)
 ;;   ld a4,8(a2)
 ;;   ugt a4,a3,a4##ty=i64
 ;;   ld a3,0(a2)
@ -69,7 +69,7 @@
 ;;   ld a2,[const(1)]
 ;;   add a2,a0,a2
 ;;   ult a3,a2,a0##ty=i64
-;;   trap_if a3,heap_oob
+;;   trap_if heap_oob##(a3 ne zero)
 ;;   ld a3,8(a1)
 ;;   ugt a4,a2,a3##ty=i64
 ;;   ld a3,0(a1)
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@ -44,7 +44,7 @@
 ;;   ld a3,[const(1)]
 ;;   add a3,a0,a3
 ;;   ult a4,a3,a0##ty=i64
-;;   trap_if a4,heap_oob
+;;   trap_if heap_oob##(a4 ne zero)
 ;;   ld a4,8(a2)
 ;;   ugt a4,a3,a4##ty=i64
 ;;   ld a3,0(a2)
@ -69,7 +69,7 @@
 ;;   ld a2,[const(1)]
 ;;   add a2,a0,a2
 ;;   ult a3,a2,a0##ty=i64
-;;   trap_if a3,heap_oob
+;;   trap_if heap_oob##(a3 ne zero)
 ;;   ld a3,8(a1)
 ;;   ugt a4,a2,a3##ty=i64
 ;;   ld a3,0(a1)