diff --git a/cranelift/codegen/src/isa/x64/inst/mod.rs b/cranelift/codegen/src/isa/x64/inst/mod.rs
index 7fb1597f4d..c069015da2 100644
--- a/cranelift/codegen/src/isa/x64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/x64/inst/mod.rs
@@ -56,7 +56,7 @@ pub enum Inst {
         dst: Writable<Reg>,
     },
 
-    /// Bitwise negation
+    /// Bitwise not
     Not {
         size: u8, // 1, 2, 4 or 8
         src: Writable<Reg>,
diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs
index f9cb49ded9..16f2e1f45b 100644
--- a/cranelift/codegen/src/isa/x64/lower.rs
+++ b/cranelift/codegen/src/isa/x64/lower.rs
@@ -651,7 +651,7 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
                     _ => unreachable!(),
                 },
                 types::I32 | types::I64 => (dst_ty.bytes() as u8, input_to_reg(ctx, inputs[0])),
-                _ => unreachable!("{}", dst_ty),
+                _ => unreachable!("unhandled output type for shift/rotates: {}", dst_ty),
             };
 
             let (count, rhs) = if let Some(cst) = ctx.get_input(insn, 1).constant {