From 5ade0c779c126b19e22436a2afb668bc755f9519 Mon Sep 17 00:00:00 2001
From: Nick Fitzgerald <fitzgen@gmail.com>
Date: Wed, 26 Jul 2023 19:49:31 -0700
Subject: [PATCH] Cranelift: Fix `ABIMachineSpec::gen_add_imm` for riscv64
 (#6780)

It was generating bit-wise and instructions instead of addition instructions.

While we are at it, use field literal short hand for a struct literal in riscv64
instruction emission.
---
 cranelift/codegen/src/isa/riscv64/abi.rs             |  2 +-
 cranelift/codegen/src/isa/riscv64/inst/emit.rs       |  5 +----
 .../filetests/filetests/isa/riscv64/stack-limit.clif | 12 ++++++------
 3 files changed, 8 insertions(+), 11 deletions(-)

diff --git a/cranelift/codegen/src/isa/riscv64/abi.rs b/cranelift/codegen/src/isa/riscv64/abi.rs
index e8aa958240..50fa73b6cf 100644
--- a/cranelift/codegen/src/isa/riscv64/abi.rs
+++ b/cranelift/codegen/src/isa/riscv64/abi.rs
@@ -275,7 +275,7 @@ impl ABIMachineSpec for Riscv64MachineDeps {
         let mut insts = SmallInstVec::new();
         if let Some(imm12) = Imm12::maybe_from_u64(imm as u64) {
             insts.push(Inst::AluRRImm12 {
-                alu_op: AluOPRRI::Andi,
+                alu_op: AluOPRRI::Addi,
                 rd: into_reg,
                 rs: from_reg,
                 imm12,
diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit.rs b/cranelift/codegen/src/isa/riscv64/inst/emit.rs
index 742cc9220e..15f44ebfaf 100644
--- a/cranelift/codegen/src/isa/riscv64/inst/emit.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/emit.rs
@@ -1996,10 +1996,7 @@ impl MachInstEmit for Inst {
                 .emit(&[], sink, emit_info, state);
                 // trap
                 sink.bind_label(label_trap, &mut state.ctrl_plane);
-                Inst::Udf {
-                    trap_code: trap_code,
-                }
-                .emit(&[], sink, emit_info, state);
+                Inst::Udf { trap_code }.emit(&[], sink, emit_info, state);
                 sink.bind_label(label_jump_over, &mut state.ctrl_plane);
             }
             &Inst::TrapIf { test, trap_code } => {
diff --git a/cranelift/filetests/filetests/isa/riscv64/stack-limit.clif b/cranelift/filetests/filetests/isa/riscv64/stack-limit.clif
index 6487c9e7e3..0364fcb82b 100644
--- a/cranelift/filetests/filetests/isa/riscv64/stack-limit.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/stack-limit.clif
@@ -147,7 +147,7 @@ block0(v0: i64):
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   andi t6,a0,176
+;   addi t6,a0,176
 ;   trap_ifc stk_ovf##(sp ult t6)
 ;   add sp,-176
 ; block0:
@@ -163,7 +163,7 @@ block0(v0: i64):
 ;   sd ra, 8(sp)
 ;   sd s0, 0(sp)
 ;   ori s0, sp, 0
-;   andi t6, a0, 0xb0
+;   addi t6, a0, 0xb0
 ;   bgeu sp, t6, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: stk_ovf
 ;   addi sp, sp, -0xb0
@@ -251,7 +251,7 @@ block0(v0: i64):
 ;   mv fp,sp
 ;   ld t6,0(a0)
 ;   ld t6,4(t6)
-;   andi t6,t6,32
+;   addi t6,t6,32
 ;   trap_ifc stk_ovf##(sp ult t6)
 ;   add sp,-32
 ; block0:
@@ -269,7 +269,7 @@ block0(v0: i64):
 ;   ori s0, sp, 0
 ;   ld t6, 0(a0)
 ;   ld t6, 4(t6)
-;   andi t6, t6, 0x20
+;   addi t6, t6, 0x20
 ;   bgeu sp, t6, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: stk_ovf
 ;   addi sp, sp, -0x20
@@ -363,7 +363,7 @@ block0(v0: i64):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ;   ld t6,400000(a0)
-;   andi t6,t6,32
+;   addi t6,t6,32
 ;   trap_ifc stk_ovf##(sp ult t6)
 ;   add sp,-32
 ; block0:
@@ -386,7 +386,7 @@ block0(v0: i64):
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   add t6, t6, a0
 ;   ld t6, 0(t6)
-;   andi t6, t6, 0x20
+;   addi t6, t6, 0x20
 ;   bgeu sp, t6, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: stk_ovf
 ;   addi sp, sp, -0x20