From 6aea8e0d7e5c2894dea187d516e4e72b0ef392e6 Mon Sep 17 00:00:00 2001
From: Trevor Elliott <telliott@fastly.com>
Date: Mon, 5 Dec 2022 08:18:49 -0800
Subject: [PATCH] Don't reuse destination registers when lowering splat on
 aarch64 (#5370)

---
 cranelift/codegen/src/isa/aarch64/inst/mod.rs       | 5 +++--
 cranelift/filetests/filetests/isa/aarch64/simd.clif | 4 ++--
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs
index dca2a479d0..68ac126cf5 100644
--- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs
@@ -421,8 +421,9 @@ impl Inst {
                 size
             }]
         } else if let Some(imm) = widen_32_bit_pattern(pattern, lane_size) {
+            let tmp = alloc_tmp(types::I64X2);
             let mut insts = smallvec![Inst::VecDupImm {
-                rd,
+                rd: tmp,
                 imm,
                 invert: false,
                 size: VectorSize::Size64x2,
@@ -433,7 +434,7 @@ impl Inst {
             if !size.is_128bits() {
                 insts.push(Inst::FpuExtend {
                     rd,
-                    rn: rd.to_reg(),
+                    rn: tmp.to_reg(),
                     size: ScalarSize::Size64,
                 });
             }
diff --git a/cranelift/filetests/filetests/isa/aarch64/simd.clif b/cranelift/filetests/filetests/isa/aarch64/simd.clif
index b21ec65304..91da31460b 100644
--- a/cranelift/filetests/filetests/isa/aarch64/simd.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/simd.clif
@@ -101,8 +101,8 @@ block0:
 }
 
 ; block0:
-;   movi v0.2d, #18374687579166474495
-;   fmov d0, d0
+;   movi v1.2d, #18374687579166474495
+;   fmov d0, d1
 ;   ret
 
 function %f10() -> i32x4 {