PCC: Fix several aarch64 check_constant failures (#7593)

* PCC: Fix several aarch64 check_constant failures

This patch fixes several aarch64 check_constant failures:

1. `check_subsume` for `AluRRImmLogic` failed due to the mismatch of fact width

  isle rule for `orr_imm` always generates fact with bit_width 64 regardless of
  immediate type. So when Type is I32, `check_subsume` will be failed.

2. `MovN` generates incorrect fact range value when `first_is_inverted` is true

  `running_value` should be calculated as !(((!imm16) & 0xffff) << shift) or
  !(u64::from(imm.bits) << shift)

Added two test cases in cranelift/filetests/filetests/pcc/succeed/const.clif.

Additional fix for `get_fact_or_default`:

  `trace!` treats `reg` as VirtualReg and it will panic when "reg" is RealReg and
  `trace-log` feature is enabled.

* simplify get_fact_or_default

Co-authored-by: Nick Fitzgerald <fitzgen@gmail.com>

* fix missing comma

---------

Co-authored-by: Nick Fitzgerald <fitzgen@gmail.com>

cranelift/codegen/src/isa/aarch64/inst.isle

@@ -1709,6 +1709,9 @@
 (decl pure partial imm_logic_from_u64 (Type u64) ImmLogic)
 (extern constructor imm_logic_from_u64 imm_logic_from_u64)
 
+(decl pure partial imm_size_from_type (Type) u16)
+(extern constructor imm_size_from_type imm_size_from_type)
+
 (decl pure partial imm_logic_from_imm64 (Type Imm64) ImmLogic)
 (extern constructor imm_logic_from_imm64 imm_logic_from_imm64)
 
@@ -2938,9 +2941,10 @@
 ;; we only match when we are zero-extending the value.
 (rule 1 (imm (integral_ty ty) (ImmExtend.Zero) k)
       (if-let n (imm_logic_from_u64 ty k))
+      (if-let m (imm_size_from_type ty))
       (add_range_fact
        (orr_imm ty (zero_reg) n)
-       64 k k))
+       m k k))
 
 (decl load_constant64_full (Type ImmExtend u64) Reg)
 (extern constructor load_constant64_full load_constant64_full)

cranelift/codegen/src/isa/aarch64/lower/isle.rs

@@ -174,6 +174,14 @@ impl Context for IsleContext<'_, '_, MInst, AArch64Backend> {
         ImmLogic::maybe_from_u64(n, ty)
     }
 
+    fn imm_size_from_type(&mut self, ty: Type) -> Option<u16> {
+        match ty {
+            I32 => Some(32),
+            I64 => Some(64),
+            _ => None,
+        }
+    }
+
     fn imm_logic_from_imm64(&mut self, ty: Type, n: Imm64) -> Option<ImmLogic> {
         let ty = if ty.bits() < 32 { I32 } else { ty };
         self.imm_logic_from_u64(ty, n.bits() as u64)
@@ -395,7 +403,7 @@ impl Context for IsleContext<'_, '_, MInst, AArch64Backend> {
                         size,
                     });
                     if pcc {
-                        running_value = !(imm16 << shift);
+                        running_value = !(u64::from(imm.bits) << shift);
                         self.lower_ctx.add_range_fact(
                             rd.to_reg(),
                             64,

cranelift/codegen/src/machinst/pcc.rs

@@ -6,8 +6,7 @@ use crate::trace;
 
 pub(crate) fn get_fact_or_default<I: VCodeInst>(vcode: &VCode<I>, reg: Reg, width: u16) -> Fact {
     trace!(
-        "get_fact_or_default: reg v{} -> {:?}",
-        reg.to_virtual_reg().unwrap().index(),
+        "get_fact_or_default: reg {reg:?} -> {:?}",
         vcode.vreg_fact(reg.into())
     );
     vcode

cranelift/filetests/filetests/pcc/succeed/const.clif

@@ -16,3 +16,15 @@ block0:
     v8 ! range(64, 0xffff_0000_0000_ffff, 0xffff_0000_0000_ffff) = iconst.i64 0xffff_0000_0000_ffff
     return
 }
+
+function %f1() -> i32 {
+block0:
+    v0 = iconst.i32 0x10_0010
+    return v0
+}
+
+function %f2() -> i64 {
+block0:
+    v0 = iconst.i64 0x9_ffff_ffff
+    return v0
+}