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This PR updates the AArch64 ABI implementation so that it (i) properly respects that v8-v15 inclusive have callee-save lower halves, and caller-save upper halves, by conservatively approximating (to full registers) in the appropriate directions when generating prologue caller-saves and when informing the regalloc of clobbered regs across callsites. In order to prevent saving all of these vector registers in the prologue of every non-leaf function due to the above approximation, this also makes use of a new regalloc.rs feature to exclude call instructions' writes from the clobber set returned by register allocation. This is safe whenever the caller and callee have the same ABI (because anything the callee could clobber, the caller is allowed to clobber as well without saving it in the prologue). Fixes #2254.pull/2267/head
Chris Fallin
4 years ago
29 changed files with 325 additions and 206 deletions
@ -1,66 +0,0 @@ |
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//! Pretty-printing for machine code (virtual-registerized or final).
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use regalloc::{RealRegUniverse, Reg, Writable}; |
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use std::fmt::Debug; |
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use std::hash::Hash; |
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use std::string::{String, ToString}; |
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// FIXME: Should this go into regalloc.rs instead?
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/// A trait for printing instruction bits and pieces, with the the ability to
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/// take a contextualising RealRegUniverse that is used to give proper names to
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/// registers.
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pub trait ShowWithRRU { |
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/// Return a string that shows the implementing object in context of the
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/// given `RealRegUniverse`, if provided.
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fn show_rru(&self, mb_rru: Option<&RealRegUniverse>) -> String; |
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/// The same as |show_rru|, but with an optional hint giving a size in
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/// bytes. Its interpretation is object-dependent, and it is intended to
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/// pass around enough information to facilitate printing sub-parts of
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/// real registers correctly. Objects may ignore size hints that are
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/// irrelevant to them.
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fn show_rru_sized(&self, mb_rru: Option<&RealRegUniverse>, _size: u8) -> String { |
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// Default implementation is to ignore the hint.
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self.show_rru(mb_rru) |
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} |
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} |
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impl ShowWithRRU for Reg { |
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fn show_rru(&self, mb_rru: Option<&RealRegUniverse>) -> String { |
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if self.is_real() { |
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if let Some(rru) = mb_rru { |
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let reg_ix = self.get_index(); |
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if reg_ix < rru.regs.len() { |
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return rru.regs[reg_ix].1.to_string(); |
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} else { |
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// We have a real reg which isn't listed in the universe.
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// Per the regalloc.rs interface requirements, this is
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// Totally Not Allowed. Print it generically anyway, so
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// we have something to debug.
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return format!("!!{:?}!!", self); |
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} |
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} |
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} |
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// The reg is virtual, or we have no universe. Be generic.
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format!("%{:?}", self) |
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} |
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fn show_rru_sized(&self, _mb_rru: Option<&RealRegUniverse>, _size: u8) -> String { |
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// For the specific case of Reg, we demand not to have a size hint,
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// since interpretation of the size is target specific, but this code
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// is used by all targets.
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panic!("Reg::show_rru_sized: impossible to implement"); |
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} |
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} |
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impl<R: ShowWithRRU + Copy + Ord + Hash + Eq + Debug> ShowWithRRU for Writable<R> { |
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fn show_rru(&self, mb_rru: Option<&RealRegUniverse>) -> String { |
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self.to_reg().show_rru(mb_rru) |
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} |
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fn show_rru_sized(&self, mb_rru: Option<&RealRegUniverse>, size: u8) -> String { |
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self.to_reg().show_rru_sized(mb_rru, size) |
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} |
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} |
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@ -0,0 +1,99 @@ |
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test compile |
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target aarch64 |
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function %f(f64) -> f64 { |
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block0(v0: f64): |
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v1 = fadd.f64 v0, v0 |
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v2 = fadd.f64 v0, v0 |
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v3 = fadd.f64 v0, v0 |
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v4 = fadd.f64 v0, v0 |
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v5 = fadd.f64 v0, v0 |
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v6 = fadd.f64 v0, v0 |
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v7 = fadd.f64 v0, v0 |
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v8 = fadd.f64 v0, v0 |
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v9 = fadd.f64 v0, v0 |
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v10 = fadd.f64 v0, v0 |
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v11 = fadd.f64 v0, v0 |
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v12 = fadd.f64 v0, v0 |
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v13 = fadd.f64 v0, v0 |
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v14 = fadd.f64 v0, v0 |
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v15 = fadd.f64 v0, v0 |
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v16 = fadd.f64 v0, v0 |
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v17 = fadd.f64 v0, v0 |
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v18 = fadd.f64 v0, v0 |
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v19 = fadd.f64 v0, v0 |
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v20 = fadd.f64 v0, v0 |
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v21 = fadd.f64 v0, v0 |
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v22 = fadd.f64 v0, v0 |
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v23 = fadd.f64 v0, v0 |
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v24 = fadd.f64 v0, v0 |
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v25 = fadd.f64 v0, v0 |
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v26 = fadd.f64 v0, v0 |
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v27 = fadd.f64 v0, v0 |
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v28 = fadd.f64 v0, v0 |
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v29 = fadd.f64 v0, v0 |
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v30 = fadd.f64 v0, v0 |
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v31 = fadd.f64 v0, v0 |
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v32 = fadd.f64 v0, v1 |
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v33 = fadd.f64 v2, v3 |
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v34 = fadd.f64 v4, v5 |
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v35 = fadd.f64 v6, v7 |
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v36 = fadd.f64 v8, v9 |
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v37 = fadd.f64 v10, v11 |
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v38 = fadd.f64 v12, v13 |
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v39 = fadd.f64 v14, v15 |
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v40 = fadd.f64 v16, v17 |
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v41 = fadd.f64 v18, v19 |
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v42 = fadd.f64 v20, v21 |
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v43 = fadd.f64 v22, v23 |
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v44 = fadd.f64 v24, v25 |
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v45 = fadd.f64 v26, v27 |
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v46 = fadd.f64 v28, v29 |
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v47 = fadd.f64 v30, v31 |
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v48 = fadd.f64 v32, v33 |
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v49 = fadd.f64 v34, v35 |
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v50 = fadd.f64 v36, v37 |
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v51 = fadd.f64 v38, v39 |
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v52 = fadd.f64 v40, v41 |
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v53 = fadd.f64 v42, v43 |
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v54 = fadd.f64 v44, v45 |
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v55 = fadd.f64 v46, v47 |
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v56 = fadd.f64 v48, v49 |
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v57 = fadd.f64 v50, v51 |
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v58 = fadd.f64 v52, v53 |
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v59 = fadd.f64 v54, v55 |
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v60 = fadd.f64 v56, v57 |
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v61 = fadd.f64 v58, v59 |
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v62 = fadd.f64 v60, v61 |
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return v62 |
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} |
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; check: stp fp, lr, [sp, #-16]! |
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; nextln: mov fp, sp |
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; nextln: sub sp, sp, #128 |
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; nextln: str q8, [sp] |
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; nextln: str q9, [sp, #16] |
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; nextln: str q10, [sp, #32] |
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; nextln: str q11, [sp, #48] |
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; nextln: str q12, [sp, #64] |
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; nextln: str q13, [sp, #80] |
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; nextln: str q14, [sp, #96] |
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; nextln: str q15, [sp, #112] |
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; check: ldr q8, [sp] |
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; nextln: ldr q9, [sp, #16] |
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; nextln: ldr q10, [sp, #32] |
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; nextln: ldr q11, [sp, #48] |
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; nextln: ldr q12, [sp, #64] |
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; nextln: ldr q13, [sp, #80] |
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; nextln: ldr q14, [sp, #96] |
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; nextln: ldr q15, [sp, #112] |
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; nextln: mov sp, fp |
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; nextln: ldp fp, lr, [sp], #16 |
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; nextln: ret |
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