Take reg_universe as argument to machinst::compile

cranelift/codegen/src/isa/aarch64/mod.rs

@@ -58,7 +58,7 @@ impl AArch64Backend {
     ) -> CodegenResult<VCode<inst::Inst>> {
         let emit_info = EmitInfo::new(flags.clone());
         let abi = Box::new(abi::AArch64ABICallee::new(func, flags)?);
-        compile::compile::<AArch64Backend>(func, self, abi, emit_info)
+        compile::compile::<AArch64Backend>(func, self, abi, self.reg_universe(), emit_info)
     }
 }
 

cranelift/codegen/src/isa/arm32/mod.rs

@@ -49,7 +49,7 @@ impl Arm32Backend {
         // block layout and finalizes branches. The result is ready for binary emission.
         let emit_info = EmitInfo::new(flags.clone());
         let abi = Box::new(abi::Arm32ABICallee::new(func, flags)?);
-        compile::compile::<Arm32Backend>(func, self, abi, emit_info)
+        compile::compile::<Arm32Backend>(func, self, abi, self.reg_universe(), emit_info)
     }
 }
 

cranelift/codegen/src/isa/s390x/mod.rs

@@ -61,7 +61,7 @@ impl S390xBackend {
     ) -> CodegenResult<VCode<inst::Inst>> {
         let emit_info = EmitInfo::new(flags.clone(), self.isa_flags.clone());
         let abi = Box::new(abi::S390xABICallee::new(func, flags)?);
-        compile::compile::<S390xBackend>(func, self, abi, emit_info)
+        compile::compile::<S390xBackend>(func, self, abi, self.reg_universe(), emit_info)
     }
 }
 

cranelift/codegen/src/isa/x64/mod.rs

@@ -50,7 +50,7 @@ impl X64Backend {
         // block layout and finalizes branches. The result is ready for binary emission.
         let emit_info = EmitInfo::new(flags.clone(), self.x64_flags.clone());
         let abi = Box::new(abi::X64ABICallee::new(&func, flags)?);
-        compile::compile::<Self>(&func, self, abi, emit_info)
+        compile::compile::<Self>(&func, self, abi, self.reg_universe(), emit_info)
     }
 }
 

cranelift/codegen/src/machinst/compile.rs

@@ -14,6 +14,7 @@ pub fn compile<B: LowerBackend + MachBackend>(
     f: &Function,
     b: &B,
     abi: Box<dyn ABICallee<I = B::MInst>>,
+    reg_universe: &RealRegUniverse,
     emit_info: <B::MInst as MachInstEmit>::Info,
 ) -> CodegenResult<VCode<B::MInst>>
 where
@@ -33,7 +34,7 @@ where
     // rendering.
     log::trace!(
         "vcode from lowering: \n{}",
-        DeferredDisplay::new(|| vcode.show_rru(Some(b.reg_universe())))
+        DeferredDisplay::new(|| vcode.show_rru(Some(reg_universe)))
     );
 
     // Perform register allocation.
@@ -55,7 +56,7 @@ where
         use std::fs;
         use std::path::Path;
         if let Some(path) = std::env::var("SERIALIZE_REGALLOC").ok() {
-            let snapshot = regalloc::IRSnapshot::from_function(&vcode, b.reg_universe());
+            let snapshot = regalloc::IRSnapshot::from_function(&vcode, reg_universe);
             let serialized = bincode::serialize(&snapshot).expect("couldn't serialize snapshot");
 
             let file_path = Path::new(&path).join(Path::new(&format!("ir{}.bin", f.name)));
@@ -78,7 +79,7 @@ where
         let _tt = timing::regalloc();
         allocate_registers_with_opts(
             &mut vcode,
-            b.reg_universe(),
+            reg_universe,
             sri,
             Options {
                 run_checker,
@@ -88,7 +89,7 @@ where
         .map_err(|err| {
             log::error!(
                 "Register allocation error for vcode\n{}\nError: {:?}",
-                vcode.show_rru(Some(b.reg_universe())),
+                vcode.show_rru(Some(reg_universe)),
                 err
             );
             err
@@ -105,7 +106,7 @@ where
 
     log::trace!(
         "vcode after regalloc: final version:\n{}",
-        DeferredDisplay::new(|| vcode.show_rru(Some(b.reg_universe())))
+        DeferredDisplay::new(|| vcode.show_rru(Some(reg_universe)))
     );
 
     Ok(vcode)