cranelift: Remove the `enable_simd` shared setting (#6631)

This commit removes a setting for Cranelift which I've found a bit
confusing historically and I think is no longer necessary. The setting
is currently documented as enabling SIMD instructions, but that only
sort of works for the x64 backend and none of the other backends look at
it. Historically this was used to flag to Cranelift that a higher x64
baseline feature set is required for codegen but as of #6625 that's no
longer necessary.

Otherwise it seems more Cranelift-like nowadays to say that vector
instructions generate SIMD instructions where non-vector instructions
probably don't, but may still depending on activated CPU features. In
that sense I'm not sure if a dedicated `enable_simd` setting is still
motivated, so this PR removes it.

This renames some features in the x86 backend such as `use_avx_simd` to
`use_avx` since the `_simd` part is no longer part of the computation
now that `enable_simd` is gone.

cranelift/codegen/meta/src/cdsl/settings.rs

@@ -142,17 +142,6 @@ impl SettingGroup {
         let num_predicates = self.num_bool_settings() + (self.predicates.len() as u8);
         self.bool_start_byte_offset + (num_predicates + 7) / 8
     }
-
-    pub fn get_bool(&self, name: &'static str) -> (BoolSettingIndex, &Self) {
-        for (i, s) in self.settings.iter().enumerate() {
-            if let SpecificSetting::Bool(_) = s.specific {
-                if s.name == name {
-                    return (BoolSettingIndex(i), self);
-                }
-            }
-        }
-        panic!("Should have found bool setting by name.");
-    }
 }
 
 /// This is the basic information needed to track the specific parts of a setting when building

cranelift/codegen/meta/src/isa/x86.rs

@@ -3,13 +3,13 @@ use crate::cdsl::settings::{PredicateNode, SettingGroup, SettingGroupBuilder};
 
 use crate::shared::Definitions as SharedDefinitions;
 
-pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
-    let settings = define_settings(&shared_defs.settings);
+pub(crate) fn define(_shared_defs: &mut SharedDefinitions) -> TargetIsa {
+    let settings = define_settings();
 
     TargetIsa::new("x86", settings)
 }
 
-fn define_settings(shared: &SettingGroup) -> SettingGroup {
+fn define_settings() -> SettingGroup {
     let mut settings = SettingGroupBuilder::new("x86");
 
     // CPUID.01H:ECX
@@ -114,51 +114,18 @@ fn define_settings(shared: &SettingGroup) -> SettingGroup {
         false,
     );
 
-    let shared_enable_simd = shared.get_bool("enable_simd");
-
     settings.add_predicate("use_ssse3", predicate!(has_ssse3));
     settings.add_predicate("use_sse41", predicate!(has_sse41));
     settings.add_predicate("use_sse42", predicate!(has_sse41 && has_sse42));
     settings.add_predicate("use_fma", predicate!(has_avx && has_fma));
 
-    settings.add_predicate(
-        "use_ssse3_simd",
-        predicate!(shared_enable_simd && has_ssse3),
-    );
-    settings.add_predicate(
-        "use_sse41_simd",
-        predicate!(shared_enable_simd && has_sse41),
-    );
-    settings.add_predicate(
-        "use_sse42_simd",
-        predicate!(shared_enable_simd && has_sse41 && has_sse42),
-    );
-
-    settings.add_predicate("use_avx_simd", predicate!(shared_enable_simd && has_avx));
-    settings.add_predicate(
-        "use_avx2_simd",
-        predicate!(shared_enable_simd && has_avx && has_avx2),
-    );
-    settings.add_predicate(
-        "use_avx512bitalg_simd",
-        predicate!(shared_enable_simd && has_avx512bitalg),
-    );
-    settings.add_predicate(
-        "use_avx512dq_simd",
-        predicate!(shared_enable_simd && has_avx512dq),
-    );
-    settings.add_predicate(
-        "use_avx512vl_simd",
-        predicate!(shared_enable_simd && has_avx512vl),
-    );
-    settings.add_predicate(
-        "use_avx512vbmi_simd",
-        predicate!(shared_enable_simd && has_avx512vbmi),
-    );
-    settings.add_predicate(
-        "use_avx512f_simd",
-        predicate!(shared_enable_simd && has_avx512f),
-    );
+    settings.add_predicate("use_avx", predicate!(has_avx));
+    settings.add_predicate("use_avx2", predicate!(has_avx && has_avx2));
+    settings.add_predicate("use_avx512bitalg", predicate!(has_avx512bitalg));
+    settings.add_predicate("use_avx512dq", predicate!(has_avx512dq));
+    settings.add_predicate("use_avx512vl", predicate!(has_avx512vl));
+    settings.add_predicate("use_avx512vbmi", predicate!(has_avx512vbmi));
+    settings.add_predicate("use_avx512f", predicate!(has_avx512f));
 
     settings.add_predicate("use_popcnt", predicate!(has_popcnt && has_sse42));
     settings.add_predicate("use_bmi1", predicate!(has_bmi1));

cranelift/codegen/meta/src/shared/settings.rs

@@ -115,13 +115,6 @@ pub(crate) fn define() -> SettingGroup {
         false,
     );
 
-    settings.add_bool(
-        "enable_simd",
-        "Enable the use of SIMD instructions.",
-        "",
-        false,
-    );
-
     settings.add_bool(
         "enable_atomics",
         "Enable the use of atomic instructions",

cranelift/codegen/src/isa/x64/lower.isle

@@ -784,13 +784,13 @@
 ;; feature sets. To remedy this, a small dance is done with an unsigned right
 ;; shift plus some extra ops.
 (rule 3 (lower (has_type ty @ $I64X2 (sshr src (iconst n))))
-        (if-let $true (use_avx512vl_simd))
-        (if-let $true (use_avx512f_simd))
+        (if-let $true (use_avx512vl))
+        (if-let $true (use_avx512f))
         (x64_vpsraq_imm src (shift_amount_masked ty n)))
 
 (rule 2 (lower (has_type ty @ $I64X2 (sshr src amt)))
-        (if-let $true (use_avx512vl_simd))
-        (if-let $true (use_avx512f_simd))
+        (if-let $true (use_avx512vl))
+        (if-let $true (use_avx512f))
         (let ((masked Gpr (x64_and $I64 amt (RegMemImm.Imm (shift_mask ty)))))
           (x64_vpsraq src (x64_movd_to_xmm masked))))
 
@@ -1018,8 +1018,8 @@
 ;; With AVX-512 we can implement `i64x2` multiplication with a single
 ;; instruction.
 (rule 3 (lower (has_type (multi_lane 64 2) (imul x y)))
-      (if-let $true (use_avx512vl_simd))
-      (if-let $true (use_avx512dq_simd))
+      (if-let $true (use_avx512vl))
+      (if-let $true (use_avx512dq))
       (x64_vpmullq x y))
 
 ;; Otherwise, for i64x2 multiplication we describe a lane A as being composed of
@@ -1200,8 +1200,8 @@
 
 ;; When AVX512 is available, we can use a single `vpabsq` instruction.
 (rule 2 (lower (has_type $I64X2 (iabs x)))
-      (if-let $true (use_avx512vl_simd))
-      (if-let $true (use_avx512f_simd))
+      (if-let $true (use_avx512vl))
+      (if-let $true (use_avx512f))
       (x64_vpabsq x))
 
 ;; Otherwise, we use a separate register, `neg`, to contain the results of `0 -
@@ -2193,8 +2193,8 @@
 
 
 (rule 2 (lower (has_type $I8X16 (popcnt src)))
-      (if-let $true (use_avx512vl_simd))
-      (if-let $true (use_avx512bitalg_simd))
+      (if-let $true (use_avx512vl))
+      (if-let $true (use_avx512bitalg))
       (x64_vpopcntb src))
 
 
@@ -3322,8 +3322,8 @@
 ;; When AVX512VL and AVX512F are available,
 ;; `fcvt_from_uint` can be lowered to a single instruction.
 (rule 2 (lower (has_type $F32X4 (fcvt_from_uint src)))
-      (if-let $true (use_avx512vl_simd))
-      (if-let $true (use_avx512f_simd))
+      (if-let $true (use_avx512vl))
+      (if-let $true (use_avx512f))
       (x64_vcvtudq2ps src))
 
 ;; Converting packed unsigned integers to packed floats
@@ -4230,15 +4230,15 @@
 ;; greater than 31) we must mask off those resulting values in the result of
 ;; `vpermi2b`.
 (rule 2 (lower (shuffle a b (vec_mask_from_immediate (perm_from_mask_with_zeros mask zeros))))
-      (if-let $true (use_avx512vl_simd))
-      (if-let $true (use_avx512vbmi_simd))
+      (if-let $true (use_avx512vl))
+      (if-let $true (use_avx512vbmi))
       (x64_andps (x64_vpermi2b (x64_xmm_load_const $I8X16 mask) a b) zeros))
 
 ;; However, if the shuffle mask contains no out-of-bounds values, we can use
 ;; `vpermi2b` without any masking.
 (rule 1 (lower (shuffle a b (vec_mask_from_immediate mask)))
-      (if-let $true (use_avx512vl_simd))
-      (if-let $true (use_avx512vbmi_simd))
+      (if-let $true (use_avx512vl))
+      (if-let $true (use_avx512vbmi))
       (x64_vpermi2b (x64_xmm_load_const $I8X16 (perm_from_mask mask)) a b))
 
 ;; If `lhs` and `rhs` are different, we must shuffle each separately and then OR
@@ -4379,13 +4379,13 @@
         (if-let $true (use_ssse3))
         (x64_pshufb (bitcast_gpr_to_xmm $I32 src) (xmm_zero $I8X16)))
 (rule 2 (lower (has_type $I8X16 (splat src)))
-        (if-let $true (use_avx2_simd))
+        (if-let $true (use_avx2))
         (x64_vpbroadcastb (bitcast_gpr_to_xmm $I32 src)))
 (rule 3 (lower (has_type $I8X16 (splat (sinkable_load_exact addr))))
         (if-let $true (use_sse41))
         (x64_pshufb (x64_pinsrb (xmm_uninit_value) addr 0) (xmm_zero $I8X16)))
 (rule 4 (lower (has_type $I8X16 (splat (sinkable_load_exact addr))))
-        (if-let $true (use_avx2_simd))
+        (if-let $true (use_avx2))
         (x64_vpbroadcastb addr))
 
 ;; i16x8 splats: use `vpbroadcastw` on AVX2 and otherwise a 16-bit value is
@@ -4396,12 +4396,12 @@
 (rule 0 (lower (has_type $I16X8 (splat src)))
         (x64_pshufd (x64_pshuflw (bitcast_gpr_to_xmm $I32 src) 0) 0))
 (rule 1 (lower (has_type $I16X8 (splat src)))
-        (if-let $true (use_avx2_simd))
+        (if-let $true (use_avx2))
         (x64_vpbroadcastw (bitcast_gpr_to_xmm $I32 src)))
 (rule 2 (lower (has_type $I16X8 (splat (sinkable_load_exact addr))))
         (x64_pshufd (x64_pshuflw (x64_pinsrw (xmm_uninit_value) addr 0) 0) 0))
 (rule 3 (lower (has_type $I16X8 (splat (sinkable_load_exact addr))))
-        (if-let $true (use_avx2_simd))
+        (if-let $true (use_avx2))
         (x64_vpbroadcastw addr))
 
 ;; i32x4.splat - use `vpbroadcastd` on AVX2 and otherwise `pshufd` can be
@@ -4411,7 +4411,7 @@
 (rule 0 (lower (has_type $I32X4 (splat src)))
         (x64_pshufd (bitcast_gpr_to_xmm $I32 src) 0))
 (rule 1 (lower (has_type $I32X4 (splat src)))
-        (if-let $true (use_avx2_simd))
+        (if-let $true (use_avx2))
         (x64_vpbroadcastd (bitcast_gpr_to_xmm $I32 src)))
 
 ;; f32x4.splat - the source is already in an xmm register so `shufps` is all
@@ -4421,7 +4421,7 @@
         (let ((tmp Xmm src))
           (x64_shufps src src 0)))
 (rule 1 (lower (has_type $F32X4 (splat src)))
-        (if-let $true (use_avx2_simd))
+        (if-let $true (use_avx2))
         (x64_vbroadcastss src))
 
 ;; t32x4.splat of a load - use a `movss` to load into an xmm register and then
@@ -4432,12 +4432,12 @@
 ;; that the memory-operand encoding of `vbroadcastss` is usable with AVX, but
 ;; the register-based encoding is only available with AVX2. With the
 ;; `sinkable_load` extractor this should be guaranteed to use the memory-based
-;; encoding hence the `use_avx_simd` test.
+;; encoding hence the `use_avx` test.
 (rule 5 (lower (has_type (multi_lane 32 4) (splat (sinkable_load addr))))
         (let ((tmp Xmm (x64_movss_load addr)))
           (x64_shufps tmp tmp 0)))
 (rule 6 (lower (has_type (multi_lane 32 4) (splat (sinkable_load addr))))
-        (if-let $true (use_avx_simd))
+        (if-let $true (use_avx))
         (x64_vbroadcastss addr))
 
 ;; t64x2.splat - use `pshufd` to broadcast the lower 64-bit lane to the upper

cranelift/codegen/src/isa/x64/lower/isle.rs

@@ -170,38 +170,38 @@ impl Context for IsleContext<'_, '_, MInst, X64Backend> {
     }
 
     #[inline]
-    fn use_avx_simd(&mut self) -> bool {
-        self.backend.x64_flags.use_avx_simd()
+    fn use_avx(&mut self) -> bool {
+        self.backend.x64_flags.use_avx()
     }
 
     #[inline]
-    fn use_avx2_simd(&mut self) -> bool {
-        self.backend.x64_flags.use_avx2_simd()
+    fn use_avx2(&mut self) -> bool {
+        self.backend.x64_flags.use_avx2()
     }
 
     #[inline]
-    fn use_avx512vl_simd(&mut self) -> bool {
-        self.backend.x64_flags.use_avx512vl_simd()
+    fn use_avx512vl(&mut self) -> bool {
+        self.backend.x64_flags.use_avx512vl()
     }
 
     #[inline]
-    fn use_avx512dq_simd(&mut self) -> bool {
-        self.backend.x64_flags.use_avx512dq_simd()
+    fn use_avx512dq(&mut self) -> bool {
+        self.backend.x64_flags.use_avx512dq()
     }
 
     #[inline]
-    fn use_avx512f_simd(&mut self) -> bool {
-        self.backend.x64_flags.use_avx512f_simd()
+    fn use_avx512f(&mut self) -> bool {
+        self.backend.x64_flags.use_avx512f()
     }
 
     #[inline]
-    fn use_avx512bitalg_simd(&mut self) -> bool {
-        self.backend.x64_flags.use_avx512bitalg_simd()
+    fn use_avx512bitalg(&mut self) -> bool {
+        self.backend.x64_flags.use_avx512bitalg()
     }
 
     #[inline]
-    fn use_avx512vbmi_simd(&mut self) -> bool {
-        self.backend.x64_flags.use_avx512vbmi_simd()
+    fn use_avx512vbmi(&mut self) -> bool {
+        self.backend.x64_flags.use_avx512vbmi()
     }
 
     #[inline]

cranelift/codegen/src/settings.rs

@@ -535,7 +535,6 @@ use_colocated_libcalls = false
 enable_float = true
 enable_nan_canonicalization = false
 enable_pinned_reg = false
-enable_simd = false
 enable_atomics = true
 enable_safepoints = false
 enable_llvm_abi_extensions = false
@@ -558,18 +557,17 @@ enable_incremental_compilation_cache_checks = false
             );
         }
         assert_eq!(f.opt_level(), super::OptLevel::None);
-        assert_eq!(f.enable_simd(), false);
     }
 
     #[test]
     fn modify_bool() {
         let mut b = builder();
         assert_eq!(b.enable("not_there"), Err(BadName("not_there".to_string())));
-        assert_eq!(b.enable("enable_simd"), Ok(()));
-        assert_eq!(b.set("enable_simd", "false"), Ok(()));
+        assert_eq!(b.enable("enable_atomics"), Ok(()));
+        assert_eq!(b.set("enable_atomics", "false"), Ok(()));
 
         let f = Flags::new(b);
-        assert_eq!(f.enable_simd(), false);
+        assert_eq!(f.enable_atomics(), false);
     }
 
     #[test]
@@ -579,9 +577,12 @@ enable_incremental_compilation_cache_checks = false
             b.set("not_there", "true"),
             Err(BadName("not_there".to_string()))
         );
-        assert_eq!(b.set("enable_simd", ""), Err(BadValue("bool".to_string())));
         assert_eq!(
-            b.set("enable_simd", "best"),
+            b.set("enable_atomics", ""),
+            Err(BadValue("bool".to_string()))
+        );
+        assert_eq!(
+            b.set("enable_atomics", "best"),
             Err(BadValue("bool".to_string()))
         );
         assert_eq!(
@@ -591,10 +592,10 @@ enable_incremental_compilation_cache_checks = false
             ))
         );
         assert_eq!(b.set("opt_level", "speed"), Ok(()));
-        assert_eq!(b.set("enable_simd", "0"), Ok(()));
+        assert_eq!(b.set("enable_atomics", "0"), Ok(()));
 
         let f = Flags::new(b);
-        assert_eq!(f.enable_simd(), false);
+        assert_eq!(f.enable_atomics(), false);
         assert_eq!(f.opt_level(), super::OptLevel::Speed);
     }
 }

cranelift/filetests/filetests/isa/aarch64/simd-bitwise-compile.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target aarch64
 
 function %band_f32x4(f32x4, f32x4) -> f32x4 {

cranelift/filetests/filetests/isa/aarch64/simd-comparison-legalize.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target aarch64
 
 function %icmp_ne_32x4(i32x4, i32x4) -> i32x4 {

cranelift/filetests/filetests/isa/aarch64/simd-lane-access-compile.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target aarch64
 
 ;; shuffle

cranelift/filetests/filetests/isa/aarch64/simd-logical-compile.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target aarch64
 
 function %bnot_i32x4(i32x4) -> i32x4 {

cranelift/filetests/filetests/isa/x64/ceil-avx.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 sse42 has_avx
 
 function %f1(f32) -> f32 {

cranelift/filetests/filetests/isa/x64/extractlane-avx.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 sse42 has_avx
 
 function %f1(i8x16) -> i8 {

cranelift/filetests/filetests/isa/x64/fcvt-avx.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 has_avx
 
 function %f3(i32) -> f32 {

cranelift/filetests/filetests/isa/x64/fcvt-simd.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 has_avx512vl has_avx512f
 
 function %f1(i32x4) -> f32x4 {

cranelift/filetests/filetests/isa/x64/float-avx.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 sse42 has_avx
 
 function %f32_add(f32, f32) -> f32 {

cranelift/filetests/filetests/isa/x64/float-bitcast-avx.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 has_avx
 
 function %i32_to_f32(i32) -> f32 {

cranelift/filetests/filetests/isa/x64/float-bitcast.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64
 
 function %i32_to_f32(i32) -> f32 {

cranelift/filetests/filetests/isa/x64/fpromote-demote-avx.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 has_avx
 
 function %fpromote(f32) -> f64 {

cranelift/filetests/filetests/isa/x64/fpromote-demote.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64
 
 function %fpromote(f32) -> f64 {

cranelift/filetests/filetests/isa/x64/fsqrt-avx.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 has_avx
 
 function %sqrt_f32(f32) -> f32 {

cranelift/filetests/filetests/isa/x64/fsqrt.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64
 
 function %sqrt_f32(f32) -> f32 {

cranelift/filetests/filetests/isa/x64/iadd-pairwise-avx.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 sse42 has_avx
 
 function %iadd_pairwise_i16x8(i16x8, i16x8) -> i16x8 {

cranelift/filetests/filetests/isa/x64/iadd-pairwise.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 ssse3
 
 function %iadd_pairwise_i16x8(i16x8, i16x8) -> i16x8 {

cranelift/filetests/filetests/isa/x64/insertlane-avx.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 sse42 has_avx
 
 function %insertlane_f64x2_zero(f64x2, f64) -> f64x2 {

cranelift/filetests/filetests/isa/x64/insertlane.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 sse41
 
 function %insertlane_f64x2_zero(f64x2, f64) -> f64x2 {

cranelift/filetests/filetests/isa/x64/move-elision.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 skylake
 
 function %move_registers(i32x4) -> i8x16 {

cranelift/filetests/filetests/isa/x64/shuffle-avx.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 sse42 has_avx
 
 function %punpckldq(i32x4, i32x4) -> i32x4 {

cranelift/filetests/filetests/isa/x64/shuffle-avx512.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 has_avx512vl has_avx512vbmi
 
 function %shuffle_in_bounds(i8x16, i8x16) -> i8x16 {

cranelift/filetests/filetests/isa/x64/shuffle.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 sse41
 
 function %punpcklbw(i8x16, i8x16) -> i8x16 {

cranelift/filetests/filetests/isa/x64/simd-abs-avx512.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 icelake-client
 
 function %f1(i64) -> i64x2 {

cranelift/filetests/filetests/isa/x64/simd-arith-avx.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 sse42 has_avx
 
 function %i8x16_add(i8x16, i8x16) -> i8x16 {

cranelift/filetests/filetests/isa/x64/simd-bitselect.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 sse41
 
 function %mask_from_icmp(i8x16, i8x16) -> i8x16 {

cranelift/filetests/filetests/isa/x64/simd-bitwise-avx.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 sse42 has_avx
 
 function %or_from_memory(f32x4, i64) -> f32x4 {

cranelift/filetests/filetests/isa/x64/simd-bitwise-compile.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64
 
 function %band_f32x4(f32x4, f32x4) -> f32x4 {

cranelift/filetests/filetests/isa/x64/simd-cmp-avx.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 sse42 has_avx
 
 function %i8x16_eq(i8x16, i8x16) -> i8x16 {

cranelift/filetests/filetests/isa/x64/simd-comparison-legalize.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 sse41
 
 function %icmp_ne_32x4(i32x4, i32x4) -> i32x4 {

cranelift/filetests/filetests/isa/x64/simd-i64x2-shift-avx512.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 sse42 has_avx has_avx2 has_avx512f has_avx512vl
 
 function %sshr(i64x2, i64) -> i64x2 {

cranelift/filetests/filetests/isa/x64/simd-issue-3951.clif

@@ -1,5 +1,4 @@
 test compile
-set enable_simd
 target x86_64 skylake
 
 ;; Compile a CLIF version of the register allocation issue identified in

cranelift/filetests/filetests/isa/x64/simd-lane-access-compile.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 has_sse3 has_ssse3 has_sse41
 
 ;; shuffle

cranelift/filetests/filetests/isa/x64/simd-load-avx.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 sse42 has_avx
 
 function %sload8x8(i64) -> i16x8 {

cranelift/filetests/filetests/isa/x64/simd-load-extend.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 sse41
 
 function %uload8x8(i64) -> i16x8 {

cranelift/filetests/filetests/isa/x64/simd-logical-compile.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 sse41
 
 function %bnot_i32x4(i32x4) -> i32x4 {

cranelift/filetests/filetests/isa/x64/simd-splat-avx.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 sse42 has_avx
 
 function %splat_i8(i8) -> i8x16 {

cranelift/filetests/filetests/isa/x64/simd-splat-avx2.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 sse42 has_avx has_avx2
 
 function %splat_i8(i8) -> i8x16 {

cranelift/filetests/filetests/isa/x64/simd-splat.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 sse41
 
 function %splat_i8(i8) -> i8x16 {

cranelift/filetests/filetests/isa/x64/simd-widen-mul.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 sse41
 
 function %imul_swiden_hi_i8x16(i8x16, i8x16) -> i16x8 {

cranelift/filetests/filetests/isa/x64/vhigh_bits-avx.clif

@@ -1,5 +1,4 @@
 test compile precise-output
-set enable_simd
 target x86_64 has_avx
 
 function %f1(i8x16) -> i8 {

cranelift/filetests/filetests/runtests/bitcast.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target aarch64
 target x86_64
 target x86_64 has_avx

cranelift/filetests/filetests/runtests/ceil.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 sse41
 target x86_64 sse42

cranelift/filetests/filetests/runtests/conversion.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target aarch64
 target s390x
 target x86_64

cranelift/filetests/filetests/runtests/fabs.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target aarch64
 target x86_64
 target x86_64 has_avx

cranelift/filetests/filetests/runtests/fadd.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 has_avx
 target aarch64

cranelift/filetests/filetests/runtests/fcmp-eq.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 has_avx
 target aarch64

cranelift/filetests/filetests/runtests/fcmp-ge.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 has_avx
 target aarch64

cranelift/filetests/filetests/runtests/fcmp-gt.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 has_avx
 target aarch64

cranelift/filetests/filetests/runtests/fcmp-le.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 has_avx
 target aarch64

cranelift/filetests/filetests/runtests/fcmp-lt.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 has_avx
 target aarch64

cranelift/filetests/filetests/runtests/fcmp-ne.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 has_avx
 target aarch64

cranelift/filetests/filetests/runtests/fcmp-one.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 has_avx
 target s390x

cranelift/filetests/filetests/runtests/fcmp-ord.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 has_avx
 target s390x

cranelift/filetests/filetests/runtests/fcmp-ueq.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 has_avx
 target s390x

cranelift/filetests/filetests/runtests/fcmp-uge.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 has_avx
 target s390x

cranelift/filetests/filetests/runtests/fcmp-ugt.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 has_avx
 target s390x

cranelift/filetests/filetests/runtests/fcmp-ule.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 has_avx
 target s390x

cranelift/filetests/filetests/runtests/fcmp-ult.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 has_avx
 target s390x

cranelift/filetests/filetests/runtests/fcmp-uno.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 has_avx
 target s390x

cranelift/filetests/filetests/runtests/fcopysign.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target aarch64
 target x86_64
 target x86_64 has_avx

cranelift/filetests/filetests/runtests/fdemote.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 has_avx
 target s390x

cranelift/filetests/filetests/runtests/fdiv.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 has_avx
 target aarch64

cranelift/filetests/filetests/runtests/float-bitops.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 has_avx
 

cranelift/filetests/filetests/runtests/floor.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 sse41
 target x86_64 sse42

cranelift/filetests/filetests/runtests/fmax-pseudo.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 has_avx
 target aarch64

cranelift/filetests/filetests/runtests/fmax.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 has_avx
 target aarch64

cranelift/filetests/filetests/runtests/fmin-max-pseudo-vector.clif

@@ -1,5 +1,4 @@
 test run
-set enable_simd
 target aarch64
 ; target s390x FIXME: This currently fails under qemu due to a qemu bug
 target x86_64

cranelift/filetests/filetests/runtests/fmin-pseudo.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 has_avx
 target aarch64

cranelift/filetests/filetests/runtests/fmin.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 has_avx
 target aarch64

cranelift/filetests/filetests/runtests/fmul.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 has_avx
 target aarch64

cranelift/filetests/filetests/runtests/fneg.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target aarch64
 target x86_64
 target x86_64 has_avx

cranelift/filetests/filetests/runtests/fpromote.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 has_avx
 target s390x

cranelift/filetests/filetests/runtests/fsub.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 has_avx
 target aarch64

cranelift/filetests/filetests/runtests/issue-5690.clif

@@ -1,7 +1,6 @@
 test interpret
 test run
 set opt_level=speed
-set enable_simd=true
 set enable_safepoints=true
 set unwind_info=false
 set preserve_frame_pointers=true

cranelift/filetests/filetests/runtests/nearest.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target x86_64
 target x86_64 sse41
 target x86_64 sse42

cranelift/filetests/filetests/runtests/simd-arithmetic.clif

@@ -2,7 +2,6 @@ test interpret
 test run
 target aarch64
 target s390x
-set enable_simd
 target x86_64
 target x86_64 sse41
 target x86_64 sse42

cranelift/filetests/filetests/runtests/simd-avg-round.clif

@@ -1,7 +1,6 @@
 test run
 target aarch64
 target s390x
-set enable_simd
 target x86_64
 target x86_64 skylake
 target riscv64 has_v

cranelift/filetests/filetests/runtests/simd-band-splat.clif

@@ -2,7 +2,6 @@ test interpret
 test run
 target aarch64
 target s390x
-set enable_simd
 target x86_64
 target x86_64 ssse3
 target x86_64 sse42

cranelift/filetests/filetests/runtests/simd-band.clif

@@ -2,7 +2,6 @@ test interpret
 test run
 target aarch64
 target s390x
-set enable_simd
 target x86_64
 target x86_64 sse42
 target x86_64 sse42 has_avx

cranelift/filetests/filetests/runtests/simd-bitcast.clif

@@ -1,6 +1,5 @@
 test interpret
 test run
-set enable_simd
 target aarch64
 target x86_64
 target x86_64 has_avx

cranelift/filetests/filetests/runtests/simd-bitselect-to-vselect.clif

@@ -2,7 +2,6 @@ test run
 target aarch64
 target s390x
 set opt_level=speed_and_size
-set enable_simd
 target x86_64
 target x86_64 skylake
 

cranelift/filetests/filetests/runtests/simd-bitselect.clif

@@ -1,5 +1,4 @@
 test run
-set enable_simd
 target aarch64
 target s390x
 target x86_64 has_sse3 has_ssse3 has_sse41

cranelift/filetests/filetests/runtests/simd-bnot.clif

@@ -2,7 +2,6 @@ test interpret
 test run
 target aarch64
 target s390x
-set enable_simd
 target x86_64
 target x86_64 ssse3
 target x86_64 sse42

cranelift/filetests/filetests/runtests/simd-bor-splat.clif

@@ -2,7 +2,6 @@ test interpret
 test run
 target aarch64
 target s390x
-set enable_simd
 target x86_64
 target x86_64 sse42
 target x86_64 sse42 has_avx

cranelift/filetests/filetests/runtests/simd-bor.clif

@@ -2,7 +2,6 @@ test interpret
 test run
 target aarch64
 target s390x
-set enable_simd
 target x86_64
 target x86_64 sse42
 target x86_64 sse42 has_avx

cranelift/filetests/filetests/runtests/simd-bxor-splat.clif

@@ -2,7 +2,6 @@ test interpret
 test run
 target aarch64
 target s390x
-set enable_simd
 target x86_64
 target x86_64 sse41
 target x86_64 sse42

cranelift/filetests/filetests/runtests/simd-bxor.clif

@@ -2,7 +2,6 @@ test interpret
 test run
 target aarch64
 target s390x
-set enable_simd
 target x86_64
 target x86_64 sse42
 target x86_64 sse42 has_avx

cranelift/filetests/filetests/runtests/simd-conversion.clif

@@ -2,7 +2,6 @@ test interpret
 test run
 target aarch64
 target s390x
-set enable_simd
 target x86_64
 target x86_64 sse41
 target x86_64 sse42

cranelift/filetests/filetests/runtests/simd-extractlane.clif

@@ -2,7 +2,6 @@ test interpret
 test run
 target aarch64
 target s390x
-set enable_simd
 target x86_64
 target x86_64 sse41
 target x86_64 sse42

cranelift/filetests/filetests/runtests/simd-fadd-splat.clif

@@ -1,7 +1,6 @@
 test run
 target aarch64
 target s390x
-set enable_simd
 target x86_64
 target x86_64 sse41
 target x86_64 sse42

cranelift/filetests/filetests/runtests/simd-fadd.clif

@@ -1,7 +1,6 @@
 test run
 target aarch64
 target s390x
-set enable_simd
 target x86_64
 target x86_64 ssse3
 target x86_64 sse41

cranelift/filetests/filetests/runtests/simd-fcmp.clif

@@ -1,7 +1,6 @@
 test run
 target aarch64
 target s390x
-set enable_simd
 target x86_64 has_sse3 has_ssse3 has_sse41
 target x86_64 has_sse3 has_ssse3 has_sse41 has_avx