From c69ab340ca3623eef648f4f10b6a1aab8f955143 Mon Sep 17 00:00:00 2001 From: Edoardo Vacchi Date: Wed, 17 Jul 2024 00:17:31 +0200 Subject: [PATCH] winch(arm64): and, or, xor, shifts (#8921) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * winch(arm64): and, or, xor, shifts Signed-off-by: Edoardo Vacchi * fmt Signed-off-by: Edoardo Vacchi * docs Signed-off-by: Edoardo Vacchi * shift Signed-off-by: Edoardo Vacchi * shifts: test cases Signed-off-by: Edoardo Vacchi * cleanup Signed-off-by: Edoardo Vacchi * apply first batch of suggestions Signed-off-by: Edoardo Vacchi * refactor shift operations Signed-off-by: Edoardo Vacchi * fix doc strings Signed-off-by: Edoardo Vacchi * Minor cleanups This commit includes very minor clean-ups, these are mechanical changes only. * Rename `shift_rr` to `shift`, as we're still passing the context in, the callee can decide what to do with the instruction arguments. * Delete the un-used `Into for ShiftKind` --------- Signed-off-by: Edoardo Vacchi Co-authored-by: Saúl Cabrera --- tests/disas/winch/aarch64/i32_and/const.wat | 26 ++++ tests/disas/winch/aarch64/i32_and/locals.wat | 44 ++++++ tests/disas/winch/aarch64/i32_and/params.wat | 29 ++++ tests/disas/winch/aarch64/i32_or/const.wat | 26 ++++ tests/disas/winch/aarch64/i32_or/locals.wat | 44 ++++++ tests/disas/winch/aarch64/i32_or/params.wat | 29 ++++ .../disas/winch/aarch64/i32_rotl/16_const.wat | 28 ++++ .../disas/winch/aarch64/i32_rotl/8_const.wat | 27 ++++ tests/disas/winch/aarch64/i32_rotl/locals.wat | 45 ++++++ tests/disas/winch/aarch64/i32_rotl/params.wat | 30 ++++ .../disas/winch/aarch64/i32_rotr/16_const.wat | 27 ++++ .../disas/winch/aarch64/i32_rotr/8_const.wat | 26 ++++ tests/disas/winch/aarch64/i32_rotr/locals.wat | 44 ++++++ tests/disas/winch/aarch64/i32_rotr/params.wat | 29 ++++ .../disas/winch/aarch64/i32_shl/16_const.wat | 28 ++++ tests/disas/winch/aarch64/i32_shl/8_const.wat | 27 ++++ tests/disas/winch/aarch64/i32_shl/locals.wat | 44 ++++++ tests/disas/winch/aarch64/i32_shl/params.wat | 29 ++++ .../winch/aarch64/i32_shr_s/16_const.wat | 27 ++++ .../disas/winch/aarch64/i32_shr_s/8_const.wat | 26 ++++ .../disas/winch/aarch64/i32_shr_s/locals.wat | 44 ++++++ .../disas/winch/aarch64/i32_shr_s/params.wat | 29 ++++ .../winch/aarch64/i32_shr_u/16_const.wat | 27 ++++ .../disas/winch/aarch64/i32_shr_u/8_const.wat | 26 ++++ .../disas/winch/aarch64/i32_shr_u/locals.wat | 44 ++++++ .../disas/winch/aarch64/i32_shr_u/params.wat | 29 ++++ tests/disas/winch/aarch64/i32_xor/const.wat | 26 ++++ tests/disas/winch/aarch64/i32_xor/locals.wat | 44 ++++++ tests/disas/winch/aarch64/i32_xor/params.wat | 29 ++++ .../disas/winch/aarch64/i64_and/32_const.wat | 26 ++++ .../disas/winch/aarch64/i64_and/64_const.wat | 26 ++++ tests/disas/winch/aarch64/i64_and/locals.wat | 44 ++++++ tests/disas/winch/aarch64/i64_and/params.wat | 29 ++++ tests/disas/winch/aarch64/i64_or/32_const.wat | 26 ++++ tests/disas/winch/aarch64/i64_or/64_const.wat | 26 ++++ tests/disas/winch/aarch64/i64_or/locals.wat | 44 ++++++ tests/disas/winch/aarch64/i64_or/params.wat | 29 ++++ .../disas/winch/aarch64/i64_rotl/16_const.wat | 28 ++++ .../disas/winch/aarch64/i64_rotl/8_const.wat | 27 ++++ tests/disas/winch/aarch64/i64_rotl/locals.wat | 46 ++++++ tests/disas/winch/aarch64/i64_rotl/params.wat | 30 ++++ .../disas/winch/aarch64/i64_rotr/16_const.wat | 27 ++++ .../disas/winch/aarch64/i64_rotr/8_const.wat | 26 ++++ tests/disas/winch/aarch64/i64_rotr/locals.wat | 45 ++++++ tests/disas/winch/aarch64/i64_rotr/params.wat | 29 ++++ .../disas/winch/aarch64/i64_shl/16_const.wat | 27 ++++ tests/disas/winch/aarch64/i64_shl/8_const.wat | 26 ++++ tests/disas/winch/aarch64/i64_shl/locals.wat | 45 ++++++ tests/disas/winch/aarch64/i64_shl/params.wat | 29 ++++ .../winch/aarch64/i64_shr_s/16_const.wat | 27 ++++ .../disas/winch/aarch64/i64_shr_s/8_const.wat | 26 ++++ .../disas/winch/aarch64/i64_shr_s/locals.wat | 45 ++++++ .../disas/winch/aarch64/i64_shr_s/params.wat | 29 ++++ .../winch/aarch64/i64_shr_u/16_const.wat | 27 ++++ .../disas/winch/aarch64/i64_shr_u/8_const.wat | 26 ++++ .../disas/winch/aarch64/i64_shr_u/locals.wat | 45 ++++++ .../disas/winch/aarch64/i64_shr_u/params.wat | 29 ++++ .../disas/winch/aarch64/i64_xor/32_const.wat | 26 ++++ .../disas/winch/aarch64/i64_xor/64_const.wat | 26 ++++ tests/disas/winch/aarch64/i64_xor/locals.wat | 44 ++++++ tests/disas/winch/aarch64/i64_xor/params.wat | 29 ++++ winch/codegen/src/codegen/context.rs | 53 ++++++- winch/codegen/src/codegen/mod.rs | 29 ++-- winch/codegen/src/isa/aarch64/asm.rs | 140 +++++++++++++++++- winch/codegen/src/isa/aarch64/masm.rs | 69 ++++++++- winch/codegen/src/isa/x64/masm.rs | 41 ++--- winch/codegen/src/masm.rs | 8 +- winch/codegen/src/visitor.rs | 30 ++-- 68 files changed, 2235 insertions(+), 82 deletions(-) create mode 100644 tests/disas/winch/aarch64/i32_and/const.wat create mode 100644 tests/disas/winch/aarch64/i32_and/locals.wat create mode 100644 tests/disas/winch/aarch64/i32_and/params.wat create mode 100644 tests/disas/winch/aarch64/i32_or/const.wat create mode 100644 tests/disas/winch/aarch64/i32_or/locals.wat create mode 100644 tests/disas/winch/aarch64/i32_or/params.wat create mode 100644 tests/disas/winch/aarch64/i32_rotl/16_const.wat create mode 100644 tests/disas/winch/aarch64/i32_rotl/8_const.wat create mode 100644 tests/disas/winch/aarch64/i32_rotl/locals.wat create mode 100644 tests/disas/winch/aarch64/i32_rotl/params.wat create mode 100644 tests/disas/winch/aarch64/i32_rotr/16_const.wat create mode 100644 tests/disas/winch/aarch64/i32_rotr/8_const.wat create mode 100644 tests/disas/winch/aarch64/i32_rotr/locals.wat create mode 100644 tests/disas/winch/aarch64/i32_rotr/params.wat create mode 100644 tests/disas/winch/aarch64/i32_shl/16_const.wat create mode 100644 tests/disas/winch/aarch64/i32_shl/8_const.wat create mode 100644 tests/disas/winch/aarch64/i32_shl/locals.wat create mode 100644 tests/disas/winch/aarch64/i32_shl/params.wat create mode 100644 tests/disas/winch/aarch64/i32_shr_s/16_const.wat create mode 100644 tests/disas/winch/aarch64/i32_shr_s/8_const.wat create mode 100644 tests/disas/winch/aarch64/i32_shr_s/locals.wat create mode 100644 tests/disas/winch/aarch64/i32_shr_s/params.wat create mode 100644 tests/disas/winch/aarch64/i32_shr_u/16_const.wat create mode 100644 tests/disas/winch/aarch64/i32_shr_u/8_const.wat create mode 100644 tests/disas/winch/aarch64/i32_shr_u/locals.wat create mode 100644 tests/disas/winch/aarch64/i32_shr_u/params.wat create mode 100644 tests/disas/winch/aarch64/i32_xor/const.wat create mode 100644 tests/disas/winch/aarch64/i32_xor/locals.wat create mode 100644 tests/disas/winch/aarch64/i32_xor/params.wat create mode 100644 tests/disas/winch/aarch64/i64_and/32_const.wat create mode 100644 tests/disas/winch/aarch64/i64_and/64_const.wat create mode 100644 tests/disas/winch/aarch64/i64_and/locals.wat create mode 100644 tests/disas/winch/aarch64/i64_and/params.wat create mode 100644 tests/disas/winch/aarch64/i64_or/32_const.wat create mode 100644 tests/disas/winch/aarch64/i64_or/64_const.wat create mode 100644 tests/disas/winch/aarch64/i64_or/locals.wat create mode 100644 tests/disas/winch/aarch64/i64_or/params.wat create mode 100644 tests/disas/winch/aarch64/i64_rotl/16_const.wat create mode 100644 tests/disas/winch/aarch64/i64_rotl/8_const.wat create mode 100644 tests/disas/winch/aarch64/i64_rotl/locals.wat create mode 100644 tests/disas/winch/aarch64/i64_rotl/params.wat create mode 100644 tests/disas/winch/aarch64/i64_rotr/16_const.wat create mode 100644 tests/disas/winch/aarch64/i64_rotr/8_const.wat create mode 100644 tests/disas/winch/aarch64/i64_rotr/locals.wat create mode 100644 tests/disas/winch/aarch64/i64_rotr/params.wat create mode 100644 tests/disas/winch/aarch64/i64_shl/16_const.wat create mode 100644 tests/disas/winch/aarch64/i64_shl/8_const.wat create mode 100644 tests/disas/winch/aarch64/i64_shl/locals.wat create mode 100644 tests/disas/winch/aarch64/i64_shl/params.wat create mode 100644 tests/disas/winch/aarch64/i64_shr_s/16_const.wat create mode 100644 tests/disas/winch/aarch64/i64_shr_s/8_const.wat create mode 100644 tests/disas/winch/aarch64/i64_shr_s/locals.wat create mode 100644 tests/disas/winch/aarch64/i64_shr_s/params.wat create mode 100644 tests/disas/winch/aarch64/i64_shr_u/16_const.wat create mode 100644 tests/disas/winch/aarch64/i64_shr_u/8_const.wat create mode 100644 tests/disas/winch/aarch64/i64_shr_u/locals.wat create mode 100644 tests/disas/winch/aarch64/i64_shr_u/params.wat create mode 100644 tests/disas/winch/aarch64/i64_xor/32_const.wat create mode 100644 tests/disas/winch/aarch64/i64_xor/64_const.wat create mode 100644 tests/disas/winch/aarch64/i64_xor/locals.wat create mode 100644 tests/disas/winch/aarch64/i64_xor/params.wat diff --git a/tests/disas/winch/aarch64/i32_and/const.wat b/tests/disas/winch/aarch64/i32_and/const.wat new file mode 100644 index 0000000000..51697a2706 --- /dev/null +++ b/tests/disas/winch/aarch64/i32_and/const.wat @@ -0,0 +1,26 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i32) + (i32.const 1) + (i32.const 2) + (i32.and) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; mov x16, #1 +;; mov w0, w16 +;; and w0, w0, #2 +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_and/locals.wat b/tests/disas/winch/aarch64/i32_and/locals.wat new file mode 100644 index 0000000000..907ad21d1b --- /dev/null +++ b/tests/disas/winch/aarch64/i32_and/locals.wat @@ -0,0 +1,44 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i32) + (local $foo i32) + (local $bar i32) + + (i32.const 1) + (local.set $foo) + + (i32.const 2) + (local.set $bar) + + (local.get $foo) + (local.get $bar) + (i32.and) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x18 +;; mov x28, sp +;; stur x0, [x28, #0x10] +;; stur x1, [x28, #8] +;; mov x16, #0 +;; stur x16, [x28] +;; mov x16, #1 +;; mov w0, w16 +;; stur w0, [x28, #4] +;; mov x16, #2 +;; mov w0, w16 +;; stur w0, [x28] +;; ldur w0, [x28] +;; ldur w1, [x28, #4] +;; and w1, w1, w0 +;; mov w0, w1 +;; add sp, sp, #0x18 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_and/params.wat b/tests/disas/winch/aarch64/i32_and/params.wat new file mode 100644 index 0000000000..f794d45bf7 --- /dev/null +++ b/tests/disas/winch/aarch64/i32_and/params.wat @@ -0,0 +1,29 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (param i32) (param i32) (result i32) + (local.get 0) + (local.get 1) + (i32.and) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x18 +;; mov x28, sp +;; stur x0, [x28, #0x10] +;; stur x1, [x28, #8] +;; stur w2, [x28, #4] +;; stur w3, [x28] +;; ldur w0, [x28] +;; ldur w1, [x28, #4] +;; and w1, w1, w0 +;; mov w0, w1 +;; add sp, sp, #0x18 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_or/const.wat b/tests/disas/winch/aarch64/i32_or/const.wat new file mode 100644 index 0000000000..710a188d15 --- /dev/null +++ b/tests/disas/winch/aarch64/i32_or/const.wat @@ -0,0 +1,26 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i32) + (i32.const 1) + (i32.const 2) + (i32.or) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; mov x16, #1 +;; mov w0, w16 +;; orr w0, w0, #2 +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_or/locals.wat b/tests/disas/winch/aarch64/i32_or/locals.wat new file mode 100644 index 0000000000..a4493e038f --- /dev/null +++ b/tests/disas/winch/aarch64/i32_or/locals.wat @@ -0,0 +1,44 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i32) + (local $foo i32) + (local $bar i32) + + (i32.const 1) + (local.set $foo) + + (i32.const 2) + (local.set $bar) + + (local.get $foo) + (local.get $bar) + (i32.or) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x18 +;; mov x28, sp +;; stur x0, [x28, #0x10] +;; stur x1, [x28, #8] +;; mov x16, #0 +;; stur x16, [x28] +;; mov x16, #1 +;; mov w0, w16 +;; stur w0, [x28, #4] +;; mov x16, #2 +;; mov w0, w16 +;; stur w0, [x28] +;; ldur w0, [x28] +;; ldur w1, [x28, #4] +;; orr w1, w1, w0 +;; mov w0, w1 +;; add sp, sp, #0x18 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_or/params.wat b/tests/disas/winch/aarch64/i32_or/params.wat new file mode 100644 index 0000000000..c61280c8e4 --- /dev/null +++ b/tests/disas/winch/aarch64/i32_or/params.wat @@ -0,0 +1,29 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (param i32) (param i32) (result i32) + (local.get 0) + (local.get 1) + (i32.or) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x18 +;; mov x28, sp +;; stur x0, [x28, #0x10] +;; stur x1, [x28, #8] +;; stur w2, [x28, #4] +;; stur w3, [x28] +;; ldur w0, [x28] +;; ldur w1, [x28, #4] +;; orr w1, w1, w0 +;; mov w0, w1 +;; add sp, sp, #0x18 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_rotl/16_const.wat b/tests/disas/winch/aarch64/i32_rotl/16_const.wat new file mode 100644 index 0000000000..b1cc4727cf --- /dev/null +++ b/tests/disas/winch/aarch64/i32_rotl/16_const.wat @@ -0,0 +1,28 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i32) + (i32.const 1) + (i32.const 512) + (i32.rotl) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; mov x16, #1 +;; mov w0, w16 +;; sub w0, w0, wzr +;; mov x16, #0x200 +;; ror w0, w0, w16 +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_rotl/8_const.wat b/tests/disas/winch/aarch64/i32_rotl/8_const.wat new file mode 100644 index 0000000000..fb6048c262 --- /dev/null +++ b/tests/disas/winch/aarch64/i32_rotl/8_const.wat @@ -0,0 +1,27 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i32) + (i32.const 1) + (i32.const 2) + (i32.rotl) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; mov x16, #1 +;; mov w0, w16 +;; sub w0, w0, wzr +;; ror w0, w0, #2 +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_rotl/locals.wat b/tests/disas/winch/aarch64/i32_rotl/locals.wat new file mode 100644 index 0000000000..a425fee868 --- /dev/null +++ b/tests/disas/winch/aarch64/i32_rotl/locals.wat @@ -0,0 +1,45 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i32) + (local $foo i32) + (local $bar i32) + + (i32.const 1) + (local.set $foo) + + (i32.const 2) + (local.set $bar) + + (local.get $foo) + (local.get $bar) + (i32.rotl) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x18 +;; mov x28, sp +;; stur x0, [x28, #0x10] +;; stur x1, [x28, #8] +;; mov x16, #0 +;; stur x16, [x28] +;; mov x16, #1 +;; mov w0, w16 +;; stur w0, [x28, #4] +;; mov x16, #2 +;; mov w0, w16 +;; stur w0, [x28] +;; ldur w0, [x28] +;; ldur w1, [x28, #4] +;; sub w0, w0, wzr +;; ror w1, w1, w0 +;; mov w0, w1 +;; add sp, sp, #0x18 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_rotl/params.wat b/tests/disas/winch/aarch64/i32_rotl/params.wat new file mode 100644 index 0000000000..2f3d857ab6 --- /dev/null +++ b/tests/disas/winch/aarch64/i32_rotl/params.wat @@ -0,0 +1,30 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (param i32) (param i32) (result i32) + (local.get 0) + (local.get 1) + (i32.rotl) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x18 +;; mov x28, sp +;; stur x0, [x28, #0x10] +;; stur x1, [x28, #8] +;; stur w2, [x28, #4] +;; stur w3, [x28] +;; ldur w0, [x28] +;; ldur w1, [x28, #4] +;; sub w0, w0, wzr +;; ror w1, w1, w0 +;; mov w0, w1 +;; add sp, sp, #0x18 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_rotr/16_const.wat b/tests/disas/winch/aarch64/i32_rotr/16_const.wat new file mode 100644 index 0000000000..82a0df5ab2 --- /dev/null +++ b/tests/disas/winch/aarch64/i32_rotr/16_const.wat @@ -0,0 +1,27 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i32) + (i32.const 1) + (i32.const 512) + (i32.rotr) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; mov x16, #1 +;; mov w0, w16 +;; mov x16, #0x200 +;; ror w0, w0, w16 +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_rotr/8_const.wat b/tests/disas/winch/aarch64/i32_rotr/8_const.wat new file mode 100644 index 0000000000..68b98462b2 --- /dev/null +++ b/tests/disas/winch/aarch64/i32_rotr/8_const.wat @@ -0,0 +1,26 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i32) + (i32.const 1) + (i32.const 2) + (i32.rotr) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; mov x16, #1 +;; mov w0, w16 +;; ror w0, w0, #2 +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_rotr/locals.wat b/tests/disas/winch/aarch64/i32_rotr/locals.wat new file mode 100644 index 0000000000..998edff0b1 --- /dev/null +++ b/tests/disas/winch/aarch64/i32_rotr/locals.wat @@ -0,0 +1,44 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i32) + (local $foo i32) + (local $bar i32) + + (i32.const 1) + (local.set $foo) + + (i32.const 2) + (local.set $bar) + + (local.get $foo) + (local.get $bar) + (i32.rotr) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x18 +;; mov x28, sp +;; stur x0, [x28, #0x10] +;; stur x1, [x28, #8] +;; mov x16, #0 +;; stur x16, [x28] +;; mov x16, #1 +;; mov w0, w16 +;; stur w0, [x28, #4] +;; mov x16, #2 +;; mov w0, w16 +;; stur w0, [x28] +;; ldur w0, [x28] +;; ldur w1, [x28, #4] +;; ror w1, w1, w0 +;; mov w0, w1 +;; add sp, sp, #0x18 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_rotr/params.wat b/tests/disas/winch/aarch64/i32_rotr/params.wat new file mode 100644 index 0000000000..73a2ba6910 --- /dev/null +++ b/tests/disas/winch/aarch64/i32_rotr/params.wat @@ -0,0 +1,29 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (param i32) (param i32) (result i32) + (local.get 0) + (local.get 1) + (i32.rotr) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x18 +;; mov x28, sp +;; stur x0, [x28, #0x10] +;; stur x1, [x28, #8] +;; stur w2, [x28, #4] +;; stur w3, [x28] +;; ldur w0, [x28] +;; ldur w1, [x28, #4] +;; ror w1, w1, w0 +;; mov w0, w1 +;; add sp, sp, #0x18 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_shl/16_const.wat b/tests/disas/winch/aarch64/i32_shl/16_const.wat new file mode 100644 index 0000000000..f792f53932 --- /dev/null +++ b/tests/disas/winch/aarch64/i32_shl/16_const.wat @@ -0,0 +1,28 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i32) + (i32.const 1) + (i32.const 512) + (i32.shl) + ) +) + +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; mov x16, #1 +;; mov w0, w16 +;; mov x16, #0x200 +;; lsl w0, w0, w16 +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_shl/8_const.wat b/tests/disas/winch/aarch64/i32_shl/8_const.wat new file mode 100644 index 0000000000..9f2c79e05c --- /dev/null +++ b/tests/disas/winch/aarch64/i32_shl/8_const.wat @@ -0,0 +1,27 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i32) + (i32.const 1) + (i32.const 2) + (i32.shl) + ) +) + +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; mov x16, #1 +;; mov w0, w16 +;; lsl w0, w0, #2 +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_shl/locals.wat b/tests/disas/winch/aarch64/i32_shl/locals.wat new file mode 100644 index 0000000000..9d25ff10c1 --- /dev/null +++ b/tests/disas/winch/aarch64/i32_shl/locals.wat @@ -0,0 +1,44 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i32) + (local $foo i32) + (local $bar i32) + + (i32.const 1) + (local.set $foo) + + (i32.const 2) + (local.set $bar) + + (local.get $foo) + (local.get $bar) + (i32.shl) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x18 +;; mov x28, sp +;; stur x0, [x28, #0x10] +;; stur x1, [x28, #8] +;; mov x16, #0 +;; stur x16, [x28] +;; mov x16, #1 +;; mov w0, w16 +;; stur w0, [x28, #4] +;; mov x16, #2 +;; mov w0, w16 +;; stur w0, [x28] +;; ldur w0, [x28] +;; ldur w1, [x28, #4] +;; lsl w1, w1, w0 +;; mov w0, w1 +;; add sp, sp, #0x18 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_shl/params.wat b/tests/disas/winch/aarch64/i32_shl/params.wat new file mode 100644 index 0000000000..750bae0c8b --- /dev/null +++ b/tests/disas/winch/aarch64/i32_shl/params.wat @@ -0,0 +1,29 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (param i32) (param i32) (result i32) + (local.get 0) + (local.get 1) + (i32.shl) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x18 +;; mov x28, sp +;; stur x0, [x28, #0x10] +;; stur x1, [x28, #8] +;; stur w2, [x28, #4] +;; stur w3, [x28] +;; ldur w0, [x28] +;; ldur w1, [x28, #4] +;; lsl w1, w1, w0 +;; mov w0, w1 +;; add sp, sp, #0x18 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_shr_s/16_const.wat b/tests/disas/winch/aarch64/i32_shr_s/16_const.wat new file mode 100644 index 0000000000..2adbff3e19 --- /dev/null +++ b/tests/disas/winch/aarch64/i32_shr_s/16_const.wat @@ -0,0 +1,27 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i32) + (i32.const 1) + (i32.const 512) + (i32.shr_s) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; mov x16, #1 +;; mov w0, w16 +;; mov x16, #0x200 +;; asr w0, w0, w16 +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_shr_s/8_const.wat b/tests/disas/winch/aarch64/i32_shr_s/8_const.wat new file mode 100644 index 0000000000..ceff09d356 --- /dev/null +++ b/tests/disas/winch/aarch64/i32_shr_s/8_const.wat @@ -0,0 +1,26 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i32) + (i32.const 1) + (i32.const 2) + (i32.shr_s) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; mov x16, #1 +;; mov w0, w16 +;; asr w0, w0, #2 +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_shr_s/locals.wat b/tests/disas/winch/aarch64/i32_shr_s/locals.wat new file mode 100644 index 0000000000..5bc01fd76c --- /dev/null +++ b/tests/disas/winch/aarch64/i32_shr_s/locals.wat @@ -0,0 +1,44 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i32) + (local $foo i32) + (local $bar i32) + + (i32.const 1) + (local.set $foo) + + (i32.const 2) + (local.set $bar) + + (local.get $foo) + (local.get $bar) + (i32.shr_s) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x18 +;; mov x28, sp +;; stur x0, [x28, #0x10] +;; stur x1, [x28, #8] +;; mov x16, #0 +;; stur x16, [x28] +;; mov x16, #1 +;; mov w0, w16 +;; stur w0, [x28, #4] +;; mov x16, #2 +;; mov w0, w16 +;; stur w0, [x28] +;; ldur w0, [x28] +;; ldur w1, [x28, #4] +;; asr w1, w1, w0 +;; mov w0, w1 +;; add sp, sp, #0x18 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_shr_s/params.wat b/tests/disas/winch/aarch64/i32_shr_s/params.wat new file mode 100644 index 0000000000..2642370d5e --- /dev/null +++ b/tests/disas/winch/aarch64/i32_shr_s/params.wat @@ -0,0 +1,29 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (param i32) (param i32) (result i32) + (local.get 0) + (local.get 1) + (i32.shr_s) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x18 +;; mov x28, sp +;; stur x0, [x28, #0x10] +;; stur x1, [x28, #8] +;; stur w2, [x28, #4] +;; stur w3, [x28] +;; ldur w0, [x28] +;; ldur w1, [x28, #4] +;; asr w1, w1, w0 +;; mov w0, w1 +;; add sp, sp, #0x18 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_shr_u/16_const.wat b/tests/disas/winch/aarch64/i32_shr_u/16_const.wat new file mode 100644 index 0000000000..a66a99857f --- /dev/null +++ b/tests/disas/winch/aarch64/i32_shr_u/16_const.wat @@ -0,0 +1,27 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i32) + (i32.const 1) + (i32.const 512) + (i32.shr_u) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; mov x16, #1 +;; mov w0, w16 +;; mov x16, #0x200 +;; lsr w0, w0, w16 +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_shr_u/8_const.wat b/tests/disas/winch/aarch64/i32_shr_u/8_const.wat new file mode 100644 index 0000000000..c3bcff0c78 --- /dev/null +++ b/tests/disas/winch/aarch64/i32_shr_u/8_const.wat @@ -0,0 +1,26 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i32) + (i32.const 1) + (i32.const 2) + (i32.shr_u) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; mov x16, #1 +;; mov w0, w16 +;; lsr w0, w0, #2 +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_shr_u/locals.wat b/tests/disas/winch/aarch64/i32_shr_u/locals.wat new file mode 100644 index 0000000000..25045070d1 --- /dev/null +++ b/tests/disas/winch/aarch64/i32_shr_u/locals.wat @@ -0,0 +1,44 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i32) + (local $foo i32) + (local $bar i32) + + (i32.const 1) + (local.set $foo) + + (i32.const 2) + (local.set $bar) + + (local.get $foo) + (local.get $bar) + (i32.shr_u) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x18 +;; mov x28, sp +;; stur x0, [x28, #0x10] +;; stur x1, [x28, #8] +;; mov x16, #0 +;; stur x16, [x28] +;; mov x16, #1 +;; mov w0, w16 +;; stur w0, [x28, #4] +;; mov x16, #2 +;; mov w0, w16 +;; stur w0, [x28] +;; ldur w0, [x28] +;; ldur w1, [x28, #4] +;; lsr w1, w1, w0 +;; mov w0, w1 +;; add sp, sp, #0x18 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_shr_u/params.wat b/tests/disas/winch/aarch64/i32_shr_u/params.wat new file mode 100644 index 0000000000..e5658d3700 --- /dev/null +++ b/tests/disas/winch/aarch64/i32_shr_u/params.wat @@ -0,0 +1,29 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (param i32) (param i32) (result i32) + (local.get 0) + (local.get 1) + (i32.shr_u) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x18 +;; mov x28, sp +;; stur x0, [x28, #0x10] +;; stur x1, [x28, #8] +;; stur w2, [x28, #4] +;; stur w3, [x28] +;; ldur w0, [x28] +;; ldur w1, [x28, #4] +;; lsr w1, w1, w0 +;; mov w0, w1 +;; add sp, sp, #0x18 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_xor/const.wat b/tests/disas/winch/aarch64/i32_xor/const.wat new file mode 100644 index 0000000000..76bbd4b68d --- /dev/null +++ b/tests/disas/winch/aarch64/i32_xor/const.wat @@ -0,0 +1,26 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i32) + (i32.const 1) + (i32.const 2) + (i32.xor) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; mov x16, #1 +;; mov w0, w16 +;; eor w0, w0, #2 +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_xor/locals.wat b/tests/disas/winch/aarch64/i32_xor/locals.wat new file mode 100644 index 0000000000..7cede8bad7 --- /dev/null +++ b/tests/disas/winch/aarch64/i32_xor/locals.wat @@ -0,0 +1,44 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i32) + (local $foo i32) + (local $bar i32) + + (i32.const 1) + (local.set $foo) + + (i32.const 2) + (local.set $bar) + + (local.get $foo) + (local.get $bar) + (i32.xor) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x18 +;; mov x28, sp +;; stur x0, [x28, #0x10] +;; stur x1, [x28, #8] +;; mov x16, #0 +;; stur x16, [x28] +;; mov x16, #1 +;; mov w0, w16 +;; stur w0, [x28, #4] +;; mov x16, #2 +;; mov w0, w16 +;; stur w0, [x28] +;; ldur w0, [x28] +;; ldur w1, [x28, #4] +;; eor w1, w1, w0 +;; mov w0, w1 +;; add sp, sp, #0x18 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i32_xor/params.wat b/tests/disas/winch/aarch64/i32_xor/params.wat new file mode 100644 index 0000000000..892e9abf6d --- /dev/null +++ b/tests/disas/winch/aarch64/i32_xor/params.wat @@ -0,0 +1,29 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (param i32) (param i32) (result i32) + (local.get 0) + (local.get 1) + (i32.xor) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x18 +;; mov x28, sp +;; stur x0, [x28, #0x10] +;; stur x1, [x28, #8] +;; stur w2, [x28, #4] +;; stur w3, [x28] +;; ldur w0, [x28] +;; ldur w1, [x28, #4] +;; eor w1, w1, w0 +;; mov w0, w1 +;; add sp, sp, #0x18 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_and/32_const.wat b/tests/disas/winch/aarch64/i64_and/32_const.wat new file mode 100644 index 0000000000..7e82c94f42 --- /dev/null +++ b/tests/disas/winch/aarch64/i64_and/32_const.wat @@ -0,0 +1,26 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i64) + (i64.const 2) + (i64.const 3) + (i64.and) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; mov x16, #2 +;; mov x0, x16 +;; and x0, x0, #3 +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_and/64_const.wat b/tests/disas/winch/aarch64/i64_and/64_const.wat new file mode 100644 index 0000000000..232bddd07e --- /dev/null +++ b/tests/disas/winch/aarch64/i64_and/64_const.wat @@ -0,0 +1,26 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i64) + (i64.const 9223372036854775806) + (i64.const 9223372036854775807) + (i64.and) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; orr x16, xzr, #0x7ffffffffffffffe +;; mov x0, x16 +;; and x0, x0, #0x7fffffffffffffff +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_and/locals.wat b/tests/disas/winch/aarch64/i64_and/locals.wat new file mode 100644 index 0000000000..6b0e94d70f --- /dev/null +++ b/tests/disas/winch/aarch64/i64_and/locals.wat @@ -0,0 +1,44 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i64) + (local $foo i64) + (local $bar i64) + + (i64.const 2) + (local.set $foo) + (i64.const 3) + (local.set $bar) + + (local.get $foo) + (local.get $bar) + (i64.and) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x20 +;; mov x28, sp +;; stur x0, [x28, #0x18] +;; stur x1, [x28, #0x10] +;; mov x16, #0 +;; stur x16, [x28, #8] +;; stur x16, [x28] +;; mov x16, #2 +;; mov x0, x16 +;; stur x0, [x28, #8] +;; mov x16, #3 +;; mov x0, x16 +;; stur x0, [x28] +;; ldur x0, [x28] +;; ldur x1, [x28, #8] +;; and x1, x1, x0 +;; mov x0, x1 +;; add sp, sp, #0x20 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_and/params.wat b/tests/disas/winch/aarch64/i64_and/params.wat new file mode 100644 index 0000000000..23e3fb6620 --- /dev/null +++ b/tests/disas/winch/aarch64/i64_and/params.wat @@ -0,0 +1,29 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (param i64) (param i64) (result i64) + (local.get 0) + (local.get 1) + (i64.and) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x20 +;; mov x28, sp +;; stur x0, [x28, #0x18] +;; stur x1, [x28, #0x10] +;; stur x2, [x28, #8] +;; stur x3, [x28] +;; ldur x0, [x28] +;; ldur x1, [x28, #8] +;; and x1, x1, x0 +;; mov x0, x1 +;; add sp, sp, #0x20 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_or/32_const.wat b/tests/disas/winch/aarch64/i64_or/32_const.wat new file mode 100644 index 0000000000..40a6e18644 --- /dev/null +++ b/tests/disas/winch/aarch64/i64_or/32_const.wat @@ -0,0 +1,26 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i64) + (i64.const 2) + (i64.const 3) + (i64.or) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; mov x16, #2 +;; mov x0, x16 +;; orr x0, x0, #3 +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_or/64_const.wat b/tests/disas/winch/aarch64/i64_or/64_const.wat new file mode 100644 index 0000000000..2e183b9866 --- /dev/null +++ b/tests/disas/winch/aarch64/i64_or/64_const.wat @@ -0,0 +1,26 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i64) + (i64.const 9223372036854775806) + (i64.const 9223372036854775807) + (i64.or) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; orr x16, xzr, #0x7ffffffffffffffe +;; mov x0, x16 +;; orr x0, x0, #0x7fffffffffffffff +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_or/locals.wat b/tests/disas/winch/aarch64/i64_or/locals.wat new file mode 100644 index 0000000000..02335a63bb --- /dev/null +++ b/tests/disas/winch/aarch64/i64_or/locals.wat @@ -0,0 +1,44 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i64) + (local $foo i64) + (local $bar i64) + + (i64.const 2) + (local.set $foo) + (i64.const 3) + (local.set $bar) + + (local.get $foo) + (local.get $bar) + (i64.or) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x20 +;; mov x28, sp +;; stur x0, [x28, #0x18] +;; stur x1, [x28, #0x10] +;; mov x16, #0 +;; stur x16, [x28, #8] +;; stur x16, [x28] +;; mov x16, #2 +;; mov x0, x16 +;; stur x0, [x28, #8] +;; mov x16, #3 +;; mov x0, x16 +;; stur x0, [x28] +;; ldur x0, [x28] +;; ldur x1, [x28, #8] +;; orr x1, x1, x0 +;; mov x0, x1 +;; add sp, sp, #0x20 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_or/params.wat b/tests/disas/winch/aarch64/i64_or/params.wat new file mode 100644 index 0000000000..65760cfbfd --- /dev/null +++ b/tests/disas/winch/aarch64/i64_or/params.wat @@ -0,0 +1,29 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (param i64) (param i64) (result i64) + (local.get 0) + (local.get 1) + (i64.or) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x20 +;; mov x28, sp +;; stur x0, [x28, #0x18] +;; stur x1, [x28, #0x10] +;; stur x2, [x28, #8] +;; stur x3, [x28] +;; ldur x0, [x28] +;; ldur x1, [x28, #8] +;; orr x1, x1, x0 +;; mov x0, x1 +;; add sp, sp, #0x20 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_rotl/16_const.wat b/tests/disas/winch/aarch64/i64_rotl/16_const.wat new file mode 100644 index 0000000000..54471ba1bb --- /dev/null +++ b/tests/disas/winch/aarch64/i64_rotl/16_const.wat @@ -0,0 +1,28 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i64) + (i64.const 1) + (i64.const 512) + (i64.rotl) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; mov x16, #1 +;; mov x0, x16 +;; sub x0, x0, xzr +;; mov x16, #0x200 +;; ror x0, x0, x16 +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_rotl/8_const.wat b/tests/disas/winch/aarch64/i64_rotl/8_const.wat new file mode 100644 index 0000000000..a61e486adc --- /dev/null +++ b/tests/disas/winch/aarch64/i64_rotl/8_const.wat @@ -0,0 +1,27 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i64) + (i64.const 1) + (i64.const 2) + (i64.rotl) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; mov x16, #1 +;; mov x0, x16 +;; sub x0, x0, xzr +;; ror x0, x0, #2 +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_rotl/locals.wat b/tests/disas/winch/aarch64/i64_rotl/locals.wat new file mode 100644 index 0000000000..9784c25095 --- /dev/null +++ b/tests/disas/winch/aarch64/i64_rotl/locals.wat @@ -0,0 +1,46 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i64) + (local $foo i64) + (local $bar i64) + + (i64.const 1) + (local.set $foo) + + (i64.const 2) + (local.set $bar) + + (local.get $foo) + (local.get $bar) + (i64.rotl) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x20 +;; mov x28, sp +;; stur x0, [x28, #0x18] +;; stur x1, [x28, #0x10] +;; mov x16, #0 +;; stur x16, [x28, #8] +;; stur x16, [x28] +;; mov x16, #1 +;; mov x0, x16 +;; stur x0, [x28, #8] +;; mov x16, #2 +;; mov x0, x16 +;; stur x0, [x28] +;; ldur x0, [x28] +;; ldur x1, [x28, #8] +;; sub x0, x0, xzr +;; ror x1, x1, x0 +;; mov x0, x1 +;; add sp, sp, #0x20 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_rotl/params.wat b/tests/disas/winch/aarch64/i64_rotl/params.wat new file mode 100644 index 0000000000..7ea35f4dac --- /dev/null +++ b/tests/disas/winch/aarch64/i64_rotl/params.wat @@ -0,0 +1,30 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (param i64) (param i64) (result i64) + (local.get 0) + (local.get 1) + (i64.rotl) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x20 +;; mov x28, sp +;; stur x0, [x28, #0x18] +;; stur x1, [x28, #0x10] +;; stur x2, [x28, #8] +;; stur x3, [x28] +;; ldur x0, [x28] +;; ldur x1, [x28, #8] +;; sub x0, x0, xzr +;; ror x1, x1, x0 +;; mov x0, x1 +;; add sp, sp, #0x20 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_rotr/16_const.wat b/tests/disas/winch/aarch64/i64_rotr/16_const.wat new file mode 100644 index 0000000000..c1ead62d5f --- /dev/null +++ b/tests/disas/winch/aarch64/i64_rotr/16_const.wat @@ -0,0 +1,27 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i64) + (i64.const 1) + (i64.const 512) + (i64.rotr) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; mov x16, #1 +;; mov x0, x16 +;; mov x16, #0x200 +;; ror x0, x0, x16 +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_rotr/8_const.wat b/tests/disas/winch/aarch64/i64_rotr/8_const.wat new file mode 100644 index 0000000000..287d7f1786 --- /dev/null +++ b/tests/disas/winch/aarch64/i64_rotr/8_const.wat @@ -0,0 +1,26 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i64) + (i64.const 1) + (i64.const 2) + (i64.rotr) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; mov x16, #1 +;; mov x0, x16 +;; ror x0, x0, #2 +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_rotr/locals.wat b/tests/disas/winch/aarch64/i64_rotr/locals.wat new file mode 100644 index 0000000000..31db682d8e --- /dev/null +++ b/tests/disas/winch/aarch64/i64_rotr/locals.wat @@ -0,0 +1,45 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i64) + (local $foo i64) + (local $bar i64) + + (i64.const 1) + (local.set $foo) + + (i64.const 2) + (local.set $bar) + + (local.get $foo) + (local.get $bar) + (i64.rotr) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x20 +;; mov x28, sp +;; stur x0, [x28, #0x18] +;; stur x1, [x28, #0x10] +;; mov x16, #0 +;; stur x16, [x28, #8] +;; stur x16, [x28] +;; mov x16, #1 +;; mov x0, x16 +;; stur x0, [x28, #8] +;; mov x16, #2 +;; mov x0, x16 +;; stur x0, [x28] +;; ldur x0, [x28] +;; ldur x1, [x28, #8] +;; ror x1, x1, x0 +;; mov x0, x1 +;; add sp, sp, #0x20 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_rotr/params.wat b/tests/disas/winch/aarch64/i64_rotr/params.wat new file mode 100644 index 0000000000..e44c129ea0 --- /dev/null +++ b/tests/disas/winch/aarch64/i64_rotr/params.wat @@ -0,0 +1,29 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (param i64) (param i64) (result i64) + (local.get 0) + (local.get 1) + (i64.rotr) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x20 +;; mov x28, sp +;; stur x0, [x28, #0x18] +;; stur x1, [x28, #0x10] +;; stur x2, [x28, #8] +;; stur x3, [x28] +;; ldur x0, [x28] +;; ldur x1, [x28, #8] +;; ror x1, x1, x0 +;; mov x0, x1 +;; add sp, sp, #0x20 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_shl/16_const.wat b/tests/disas/winch/aarch64/i64_shl/16_const.wat new file mode 100644 index 0000000000..e4e5d33e33 --- /dev/null +++ b/tests/disas/winch/aarch64/i64_shl/16_const.wat @@ -0,0 +1,27 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i64) + (i64.const 1) + (i64.const 512) + (i64.shl) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; mov x16, #1 +;; mov x0, x16 +;; mov x16, #0x200 +;; lsl x0, x0, x16 +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_shl/8_const.wat b/tests/disas/winch/aarch64/i64_shl/8_const.wat new file mode 100644 index 0000000000..362642f61e --- /dev/null +++ b/tests/disas/winch/aarch64/i64_shl/8_const.wat @@ -0,0 +1,26 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i64) + (i64.const 1) + (i64.const 2) + (i64.shl) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; mov x16, #1 +;; mov x0, x16 +;; lsl x0, x0, #2 +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_shl/locals.wat b/tests/disas/winch/aarch64/i64_shl/locals.wat new file mode 100644 index 0000000000..cd529ba3bd --- /dev/null +++ b/tests/disas/winch/aarch64/i64_shl/locals.wat @@ -0,0 +1,45 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i64) + (local $foo i64) + (local $bar i64) + + (i64.const 1) + (local.set $foo) + + (i64.const 2) + (local.set $bar) + + (local.get $foo) + (local.get $bar) + (i64.shl) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x20 +;; mov x28, sp +;; stur x0, [x28, #0x18] +;; stur x1, [x28, #0x10] +;; mov x16, #0 +;; stur x16, [x28, #8] +;; stur x16, [x28] +;; mov x16, #1 +;; mov x0, x16 +;; stur x0, [x28, #8] +;; mov x16, #2 +;; mov x0, x16 +;; stur x0, [x28] +;; ldur x0, [x28] +;; ldur x1, [x28, #8] +;; lsl x1, x1, x0 +;; mov x0, x1 +;; add sp, sp, #0x20 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_shl/params.wat b/tests/disas/winch/aarch64/i64_shl/params.wat new file mode 100644 index 0000000000..0de3ca97ef --- /dev/null +++ b/tests/disas/winch/aarch64/i64_shl/params.wat @@ -0,0 +1,29 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (param i64) (param i64) (result i64) + (local.get 0) + (local.get 1) + (i64.shl) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x20 +;; mov x28, sp +;; stur x0, [x28, #0x18] +;; stur x1, [x28, #0x10] +;; stur x2, [x28, #8] +;; stur x3, [x28] +;; ldur x0, [x28] +;; ldur x1, [x28, #8] +;; lsl x1, x1, x0 +;; mov x0, x1 +;; add sp, sp, #0x20 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_shr_s/16_const.wat b/tests/disas/winch/aarch64/i64_shr_s/16_const.wat new file mode 100644 index 0000000000..99d67d884b --- /dev/null +++ b/tests/disas/winch/aarch64/i64_shr_s/16_const.wat @@ -0,0 +1,27 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i64) + (i64.const 1) + (i64.const 512) + (i64.shr_s) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; mov x16, #1 +;; mov x0, x16 +;; mov x16, #0x200 +;; asr x0, x0, x16 +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_shr_s/8_const.wat b/tests/disas/winch/aarch64/i64_shr_s/8_const.wat new file mode 100644 index 0000000000..0b07f24afc --- /dev/null +++ b/tests/disas/winch/aarch64/i64_shr_s/8_const.wat @@ -0,0 +1,26 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i64) + (i64.const 1) + (i64.const 2) + (i64.shr_s) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; mov x16, #1 +;; mov x0, x16 +;; asr x0, x0, #2 +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_shr_s/locals.wat b/tests/disas/winch/aarch64/i64_shr_s/locals.wat new file mode 100644 index 0000000000..5db726218e --- /dev/null +++ b/tests/disas/winch/aarch64/i64_shr_s/locals.wat @@ -0,0 +1,45 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i64) + (local $foo i64) + (local $bar i64) + + (i64.const 1) + (local.set $foo) + + (i64.const 2) + (local.set $bar) + + (local.get $foo) + (local.get $bar) + (i64.shr_s) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x20 +;; mov x28, sp +;; stur x0, [x28, #0x18] +;; stur x1, [x28, #0x10] +;; mov x16, #0 +;; stur x16, [x28, #8] +;; stur x16, [x28] +;; mov x16, #1 +;; mov x0, x16 +;; stur x0, [x28, #8] +;; mov x16, #2 +;; mov x0, x16 +;; stur x0, [x28] +;; ldur x0, [x28] +;; ldur x1, [x28, #8] +;; asr x1, x1, x0 +;; mov x0, x1 +;; add sp, sp, #0x20 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_shr_s/params.wat b/tests/disas/winch/aarch64/i64_shr_s/params.wat new file mode 100644 index 0000000000..005f7e17e5 --- /dev/null +++ b/tests/disas/winch/aarch64/i64_shr_s/params.wat @@ -0,0 +1,29 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (param i64) (param i64) (result i64) + (local.get 0) + (local.get 1) + (i64.shr_s) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x20 +;; mov x28, sp +;; stur x0, [x28, #0x18] +;; stur x1, [x28, #0x10] +;; stur x2, [x28, #8] +;; stur x3, [x28] +;; ldur x0, [x28] +;; ldur x1, [x28, #8] +;; asr x1, x1, x0 +;; mov x0, x1 +;; add sp, sp, #0x20 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_shr_u/16_const.wat b/tests/disas/winch/aarch64/i64_shr_u/16_const.wat new file mode 100644 index 0000000000..b0a759fd60 --- /dev/null +++ b/tests/disas/winch/aarch64/i64_shr_u/16_const.wat @@ -0,0 +1,27 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i64) + (i64.const 1) + (i64.const 512) + (i64.shr_u) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; mov x16, #1 +;; mov x0, x16 +;; mov x16, #0x200 +;; lsr x0, x0, x16 +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_shr_u/8_const.wat b/tests/disas/winch/aarch64/i64_shr_u/8_const.wat new file mode 100644 index 0000000000..8c45f245f3 --- /dev/null +++ b/tests/disas/winch/aarch64/i64_shr_u/8_const.wat @@ -0,0 +1,26 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i64) + (i64.const 1) + (i64.const 2) + (i64.shr_u) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; mov x16, #1 +;; mov x0, x16 +;; lsr x0, x0, #2 +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_shr_u/locals.wat b/tests/disas/winch/aarch64/i64_shr_u/locals.wat new file mode 100644 index 0000000000..aa7906309b --- /dev/null +++ b/tests/disas/winch/aarch64/i64_shr_u/locals.wat @@ -0,0 +1,45 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i64) + (local $foo i64) + (local $bar i64) + + (i64.const 1) + (local.set $foo) + + (i64.const 2) + (local.set $bar) + + (local.get $foo) + (local.get $bar) + (i64.shr_u) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x20 +;; mov x28, sp +;; stur x0, [x28, #0x18] +;; stur x1, [x28, #0x10] +;; mov x16, #0 +;; stur x16, [x28, #8] +;; stur x16, [x28] +;; mov x16, #1 +;; mov x0, x16 +;; stur x0, [x28, #8] +;; mov x16, #2 +;; mov x0, x16 +;; stur x0, [x28] +;; ldur x0, [x28] +;; ldur x1, [x28, #8] +;; lsr x1, x1, x0 +;; mov x0, x1 +;; add sp, sp, #0x20 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_shr_u/params.wat b/tests/disas/winch/aarch64/i64_shr_u/params.wat new file mode 100644 index 0000000000..39bcda73b3 --- /dev/null +++ b/tests/disas/winch/aarch64/i64_shr_u/params.wat @@ -0,0 +1,29 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (param i64) (param i64) (result i64) + (local.get 0) + (local.get 1) + (i64.shr_u) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x20 +;; mov x28, sp +;; stur x0, [x28, #0x18] +;; stur x1, [x28, #0x10] +;; stur x2, [x28, #8] +;; stur x3, [x28] +;; ldur x0, [x28] +;; ldur x1, [x28, #8] +;; lsr x1, x1, x0 +;; mov x0, x1 +;; add sp, sp, #0x20 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_xor/32_const.wat b/tests/disas/winch/aarch64/i64_xor/32_const.wat new file mode 100644 index 0000000000..eb5235dff0 --- /dev/null +++ b/tests/disas/winch/aarch64/i64_xor/32_const.wat @@ -0,0 +1,26 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i64) + (i64.const 2) + (i64.const 3) + (i64.xor) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; mov x16, #2 +;; mov x0, x16 +;; eor x0, x0, #3 +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_xor/64_const.wat b/tests/disas/winch/aarch64/i64_xor/64_const.wat new file mode 100644 index 0000000000..f5bc49de7f --- /dev/null +++ b/tests/disas/winch/aarch64/i64_xor/64_const.wat @@ -0,0 +1,26 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i64) + (i64.const 9223372036854775806) + (i64.const 9223372036854775807) + (i64.xor) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x10 +;; mov x28, sp +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; orr x16, xzr, #0x7ffffffffffffffe +;; mov x0, x16 +;; eor x0, x0, #0x7fffffffffffffff +;; add sp, sp, #0x10 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_xor/locals.wat b/tests/disas/winch/aarch64/i64_xor/locals.wat new file mode 100644 index 0000000000..b8a1fa5a2e --- /dev/null +++ b/tests/disas/winch/aarch64/i64_xor/locals.wat @@ -0,0 +1,44 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (result i64) + (local $foo i64) + (local $bar i64) + + (i64.const 2) + (local.set $foo) + (i64.const 3) + (local.set $bar) + + (local.get $foo) + (local.get $bar) + (i64.xor) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x20 +;; mov x28, sp +;; stur x0, [x28, #0x18] +;; stur x1, [x28, #0x10] +;; mov x16, #0 +;; stur x16, [x28, #8] +;; stur x16, [x28] +;; mov x16, #2 +;; mov x0, x16 +;; stur x0, [x28, #8] +;; mov x16, #3 +;; mov x0, x16 +;; stur x0, [x28] +;; ldur x0, [x28] +;; ldur x1, [x28, #8] +;; eor x1, x1, x0 +;; mov x0, x1 +;; add sp, sp, #0x20 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/tests/disas/winch/aarch64/i64_xor/params.wat b/tests/disas/winch/aarch64/i64_xor/params.wat new file mode 100644 index 0000000000..047db61842 --- /dev/null +++ b/tests/disas/winch/aarch64/i64_xor/params.wat @@ -0,0 +1,29 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (func (param i64) (param i64) (result i64) + (local.get 0) + (local.get 1) + (i64.xor) + ) +) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; mov x28, sp +;; mov x9, x0 +;; sub sp, sp, #0x20 +;; mov x28, sp +;; stur x0, [x28, #0x18] +;; stur x1, [x28, #0x10] +;; stur x2, [x28, #8] +;; stur x3, [x28] +;; ldur x0, [x28] +;; ldur x1, [x28, #8] +;; eor x1, x1, x0 +;; mov x0, x1 +;; add sp, sp, #0x20 +;; mov x28, sp +;; ldp x29, x30, [sp], #0x10 +;; ret diff --git a/winch/codegen/src/codegen/context.rs b/winch/codegen/src/codegen/context.rs index dbac5b613a..f9a3ead31c 100644 --- a/winch/codegen/src/codegen/context.rs +++ b/winch/codegen/src/codegen/context.rs @@ -5,7 +5,7 @@ use crate::{ abi::{vmctx, ABIOperand, ABIResults, RetArea, ABI}, frame::Frame, isa::reg::RegClass, - masm::{MacroAssembler, OperandSize, RegImm, SPOffset, StackSlot}, + masm::{MacroAssembler, OperandSize, RegImm, SPOffset, ShiftKind, StackSlot}, reg::Reg, regalloc::RegAlloc, stack::{Stack, TypedReg, Val}, @@ -319,6 +319,57 @@ impl<'a> CodeGenContext<'a> { }; } + /// Prepares arguments for emitting an i32 shift operation. + pub fn i32_shift(&mut self, masm: &mut M, kind: ShiftKind) + where + M: MacroAssembler, + { + let top = self.stack.peek().expect("value at stack top"); + + if top.is_i32_const() { + let val = self + .stack + .pop_i32_const() + .expect("i32 const value at stack top"); + let typed_reg = self.pop_to_reg(masm, None); + masm.shift_ir( + typed_reg.reg, + val as u64, + typed_reg.reg, + kind, + OperandSize::S32, + ); + self.stack.push(typed_reg.into()); + } else { + masm.shift(self, kind, OperandSize::S32); + } + } + + /// Prepares arguments for emitting an i64 binary operation. + pub fn i64_shift(&mut self, masm: &mut M, kind: ShiftKind) + where + M: MacroAssembler, + { + let top = self.stack.peek().expect("value at stack top"); + if top.is_i64_const() { + let val = self + .stack + .pop_i64_const() + .expect("i64 const value at stack top"); + let typed_reg = self.pop_to_reg(masm, None); + masm.shift_ir( + typed_reg.reg, + val as u64, + typed_reg.reg, + kind, + OperandSize::S64, + ); + self.stack.push(typed_reg.into()); + } else { + masm.shift(self, kind, OperandSize::S64); + }; + } + /// Prepares arguments for emitting a convert operation. pub fn convert_op(&mut self, masm: &mut M, dst_ty: WasmValType, mut emit: F) where diff --git a/winch/codegen/src/codegen/mod.rs b/winch/codegen/src/codegen/mod.rs index 4752bdddcd..8ab22e69a9 100644 --- a/winch/codegen/src/codegen/mod.rs +++ b/winch/codegen/src/codegen/mod.rs @@ -5,7 +5,7 @@ use crate::{ masm::{ ExtendKind, IntCmpKind, MacroAssembler, OperandSize, RegImm, SPOffset, ShiftKind, TrapCode, }, - stack::{TypedReg, Val}, + stack::TypedReg, }; use anyhow::Result; use smallvec::SmallVec; @@ -848,24 +848,17 @@ where .masm .address_at_reg(base, heap_data.current_length_offset); self.masm.load_ptr(size_addr, size_reg); - // Prepare the stack to emit a shift to get the size in pages rather - // than in bytes. - self.context - .stack - .push(TypedReg::new(heap_data.ty, size_reg).into()); - + // Emit a shift to get the size in pages rather than in bytes. + let dst = TypedReg::new(heap_data.ty, size_reg); let pow = heap_data.page_size_log2; - - // Ensure that the constant is correctly typed according to the heap - // type to reduce register pressure when emitting the shift operation. - match heap_data.ty { - WasmValType::I32 => self.context.stack.push(Val::i32(i32::from(pow))), - WasmValType::I64 => self.context.stack.push(Val::i64(i64::from(pow))), - _ => unreachable!(), - } - - self.masm - .shift(&mut self.context, ShiftKind::ShrU, heap_data.ty.into()); + self.masm.shift_ir( + dst.reg, + pow as u64, + dst.into(), + ShiftKind::ShrU, + heap_data.ty.into(), + ); + self.context.stack.push(dst.into()); } } diff --git a/winch/codegen/src/isa/aarch64/asm.rs b/winch/codegen/src/isa/aarch64/asm.rs index a721b22bb5..547c676658 100644 --- a/winch/codegen/src/isa/aarch64/asm.rs +++ b/winch/codegen/src/isa/aarch64/asm.rs @@ -1,12 +1,12 @@ //! Assembler library implementation for Aarch64. use super::{address::Address, regs}; -use crate::masm::RoundingMode; +use crate::masm::{RoundingMode, ShiftKind}; use crate::{masm::OperandSize, reg::Reg}; use cranelift_codegen::isa::aarch64::inst::FPUOpRI::{UShr32, UShr64}; use cranelift_codegen::isa::aarch64::inst::{ - FPULeftShiftImm, FPUOp1, FPUOp2, FPUOpRI, FPUOpRIMod, FPURightShiftImm, FpuRoundMode, - ScalarSize, + FPULeftShiftImm, FPUOp1, FPUOp2, FPUOpRI, FPUOpRIMod, FPURightShiftImm, FpuRoundMode, ImmLogic, + ImmShift, ScalarSize, }; use cranelift_codegen::{ ir::{MemFlags, SourceLoc}, @@ -28,6 +28,7 @@ impl From for inst::OperandSize { } } } + impl Into for OperandSize { fn into(self) -> ScalarSize { match self { @@ -239,6 +240,79 @@ impl Assembler { self.emit_alu_rrrr(ALUOp3::MAdd, scratch, rn, rd, regs::zero(), size); } + /// And with three registers. + pub fn and_rrr(&mut self, rm: Reg, rn: Reg, rd: Reg, size: OperandSize) { + self.emit_alu_rrr(ALUOp::And, rm, rn, rd, size); + } + + /// And immediate and register. + pub fn and_ir(&mut self, imm: u64, rn: Reg, rd: Reg, size: OperandSize) { + let alu_op = ALUOp::And; + let cl_size: inst::OperandSize = size.into(); + if let Some(imm) = ImmLogic::maybe_from_u64(imm, cl_size.to_ty()) { + self.emit_alu_rri_logic(alu_op, imm, rn, rd, size); + } else { + let scratch = regs::scratch(); + self.load_constant(imm, scratch); + self.emit_alu_rrr(alu_op, scratch, rn, rd, size); + } + } + + /// Or with three registers. + pub fn or_rrr(&mut self, rm: Reg, rn: Reg, rd: Reg, size: OperandSize) { + self.emit_alu_rrr(ALUOp::Orr, rm, rn, rd, size); + } + + /// Or immediate and register. + pub fn or_ir(&mut self, imm: u64, rn: Reg, rd: Reg, size: OperandSize) { + let alu_op = ALUOp::Orr; + let cl_size: inst::OperandSize = size.into(); + if let Some(imm) = ImmLogic::maybe_from_u64(imm, cl_size.to_ty()) { + self.emit_alu_rri_logic(alu_op, imm, rn, rd, size); + } else { + let scratch = regs::scratch(); + self.load_constant(imm, scratch); + self.emit_alu_rrr(alu_op, scratch, rn, rd, size); + } + } + + /// Xor with three registers. + pub fn xor_rrr(&mut self, rm: Reg, rn: Reg, rd: Reg, size: OperandSize) { + self.emit_alu_rrr(ALUOp::Eor, rm, rn, rd, size); + } + + /// Xor immediate and register. + pub fn xor_ir(&mut self, imm: u64, rn: Reg, rd: Reg, size: OperandSize) { + let alu_op = ALUOp::Eor; + let cl_size: inst::OperandSize = size.into(); + if let Some(imm) = ImmLogic::maybe_from_u64(imm, cl_size.to_ty()) { + self.emit_alu_rri_logic(alu_op, imm, rn, rd, size); + } else { + let scratch = regs::scratch(); + self.load_constant(imm, scratch); + self.emit_alu_rrr(alu_op, scratch, rn, rd, size); + } + } + + /// Shift with three registers. + pub fn shift_rrr(&mut self, rm: Reg, rn: Reg, rd: Reg, kind: ShiftKind, size: OperandSize) { + let shift_op = self.shift_kind_to_alu_op(kind, rm, size); + self.emit_alu_rrr(shift_op, rm, rn, rd, size); + } + + /// Shift immediate and register. + pub fn shift_ir(&mut self, imm: u64, rn: Reg, rd: Reg, kind: ShiftKind, size: OperandSize) { + let shift_op = self.shift_kind_to_alu_op(kind, rn, size); + + if let Some(imm) = ImmShift::maybe_from_u64(imm) { + self.emit_alu_rri_shift(shift_op, imm, rn, rd, size); + } else { + let scratch = regs::scratch(); + self.load_constant(imm, scratch); + self.emit_alu_rrr(shift_op, scratch, rn, rd, size); + } + } + /// Float add with three registers. pub fn fadd_rrr(&mut self, rm: Reg, rn: Reg, rd: Reg, size: OperandSize) { self.emit_fpu_rrr(FPUOp2::Add, rm, rn, rd, size); @@ -346,6 +420,50 @@ impl Assembler { }); } + fn emit_alu_rri_logic( + &mut self, + op: ALUOp, + imm: ImmLogic, + rn: Reg, + rd: Reg, + size: OperandSize, + ) { + self.emit(Inst::AluRRImmLogic { + alu_op: op, + size: size.into(), + rd: Writable::from_reg(rd.into()), + rn: rn.into(), + imml: imm, + }); + } + + fn emit_alu_rri_shift( + &mut self, + op: ALUOp, + imm: ImmShift, + rn: Reg, + rd: Reg, + size: OperandSize, + ) { + self.emit(Inst::AluRRImmShift { + alu_op: op, + size: size.into(), + rd: Writable::from_reg(rd.into()), + rn: rn.into(), + immshift: imm, + }); + } + + fn emit_alu_rrr(&mut self, op: ALUOp, rm: Reg, rn: Reg, rd: Reg, size: OperandSize) { + self.emit(Inst::AluRRR { + alu_op: op, + size: size.into(), + rd: Writable::from_reg(rd.into()), + rn: rn.into(), + rm: rm.into(), + }); + } + fn emit_alu_rrr_extend(&mut self, op: ALUOp, rm: Reg, rn: Reg, rd: Reg, size: OperandSize) { self.emit(Inst::AluRRRExtend { alu_op: op, @@ -412,6 +530,22 @@ impl Assembler { }); } + // Convert ShiftKind to ALUOp. If kind == Rotl, then emulate it by emitting + // the negation of the given reg r, and returns ALUOp::RotR. + fn shift_kind_to_alu_op(&mut self, kind: ShiftKind, r: Reg, size: OperandSize) -> ALUOp { + match kind { + ShiftKind::Shl => ALUOp::Lsl, + ShiftKind::ShrS => ALUOp::Asr, + ShiftKind::ShrU => ALUOp::Lsr, + ShiftKind::Rotr => ALUOp::RotR, + ShiftKind::Rotl => { + // neg(r) is sub(zero, r). + self.emit_alu_rrr(ALUOp::Sub, regs::zero(), r, r, size); + ALUOp::RotR + } + } + } + /// Get a label from the underlying machine code buffer. pub fn get_label(&mut self) -> MachLabel { self.buffer.get_label() diff --git a/winch/codegen/src/isa/aarch64/masm.rs b/winch/codegen/src/isa/aarch64/masm.rs index d5d808b945..1db699f7a2 100644 --- a/winch/codegen/src/isa/aarch64/masm.rs +++ b/winch/codegen/src/isa/aarch64/masm.rs @@ -347,20 +347,73 @@ impl Masm for MacroAssembler { self.asm.fsqrt_rr(src, dst, size); } - fn and(&mut self, _dst: Reg, _lhs: Reg, _rhs: RegImm, _size: OperandSize) { - todo!() + fn and(&mut self, dst: Reg, lhs: Reg, rhs: RegImm, size: OperandSize) { + match (rhs, lhs, dst) { + (RegImm::Imm(v), rn, rd) => { + let imm = match v { + I::I32(v) => v as u64, + I::I64(v) => v, + _ => unreachable!(), + }; + + self.asm.and_ir(imm, rn, rd, size); + } + + (RegImm::Reg(rm), rn, rd) => { + self.asm.and_rrr(rm, rn, rd, size); + } + } } - fn or(&mut self, _dst: Reg, _lhs: Reg, _rhs: RegImm, _size: OperandSize) { - todo!() + fn or(&mut self, dst: Reg, lhs: Reg, rhs: RegImm, size: OperandSize) { + match (rhs, lhs, dst) { + (RegImm::Imm(v), rn, rd) => { + let imm = match v { + I::I32(v) => v as u64, + I::I64(v) => v, + _ => unreachable!(), + }; + + self.asm.or_ir(imm, rn, rd, size); + } + + (RegImm::Reg(rm), rn, rd) => { + self.asm.or_rrr(rm, rn, rd, size); + } + } } - fn xor(&mut self, _dst: Reg, _lhs: Reg, _rhs: RegImm, _size: OperandSize) { - todo!() + fn xor(&mut self, dst: Reg, lhs: Reg, rhs: RegImm, size: OperandSize) { + match (rhs, lhs, dst) { + (RegImm::Imm(v), rn, rd) => { + let imm = match v { + I::I32(v) => v as u64, + I::I64(v) => v, + _ => unreachable!(), + }; + + self.asm.xor_ir(imm, rn, rd, size); + } + + (RegImm::Reg(rm), rn, rd) => { + self.asm.xor_rrr(rm, rn, rd, size); + } + } } - fn shift(&mut self, _context: &mut CodeGenContext, _kind: ShiftKind, _size: OperandSize) { - todo!() + fn shift_ir(&mut self, dst: Reg, imm: u64, lhs: Reg, kind: ShiftKind, size: OperandSize) { + self.asm.shift_ir(imm, lhs, dst, kind, size) + } + + fn shift(&mut self, context: &mut CodeGenContext, kind: ShiftKind, size: OperandSize) { + let src = context.pop_to_reg(self, None); + let dst = context.pop_to_reg(self, None); + + self.asm + .shift_rrr(src.into(), dst.into(), dst.into(), kind, size); + + context.free_reg(src); + context.stack.push(dst.into()); } fn div(&mut self, _context: &mut CodeGenContext, _kind: DivKind, _size: OperandSize) { diff --git a/winch/codegen/src/isa/x64/masm.rs b/winch/codegen/src/isa/x64/masm.rs index 95baeb53a5..303d11ae59 100644 --- a/winch/codegen/src/isa/x64/masm.rs +++ b/winch/codegen/src/isa/x64/masm.rs @@ -530,39 +530,20 @@ impl Masm for MacroAssembler { } } - fn shift(&mut self, context: &mut CodeGenContext, kind: ShiftKind, size: OperandSize) { - let top = context.stack.peek().expect("value at stack top"); - - if size == OperandSize::S32 && top.is_i32_const() { - let val = context - .stack - .pop_i32_const() - .expect("i32 const value at stack top"); - let typed_reg = context.pop_to_reg(self, None); - - self.asm.shift_ir(val as u8, typed_reg.into(), kind, size); - - context.stack.push(typed_reg.into()); - } else if size == OperandSize::S64 && top.is_i64_const() { - let val = context - .stack - .pop_i64_const() - .expect("i64 const value at stack top"); - let typed_reg = context.pop_to_reg(self, None); - - self.asm.shift_ir(val as u8, typed_reg.into(), kind, size); + fn shift_ir(&mut self, dst: Reg, imm: u64, lhs: Reg, kind: ShiftKind, size: OperandSize) { + Self::ensure_two_argument_form(&dst, &lhs); + self.asm.shift_ir(imm as u8, dst, kind, size) + } - context.stack.push(typed_reg.into()); - } else { - // Number of bits to shift must be in the CL register. - let src = context.pop_to_reg(self, Some(regs::rcx())); - let dst = context.pop_to_reg(self, None); + fn shift(&mut self, context: &mut CodeGenContext, kind: ShiftKind, size: OperandSize) { + // Number of bits to shift must be in the CL register. + let src = context.pop_to_reg(self, Some(regs::rcx())); + let dst = context.pop_to_reg(self, None); - self.asm.shift_rr(src.into(), dst.into(), kind, size); + self.asm.shift_rr(src.into(), dst.into(), kind, size); - context.free_reg(src); - context.stack.push(dst.into()); - } + context.free_reg(src); + context.stack.push(dst.into()); } fn div(&mut self, context: &mut CodeGenContext, kind: DivKind, size: OperandSize) { diff --git a/winch/codegen/src/masm.rs b/winch/codegen/src/masm.rs index 2139a0ce01..eeb73b1325 100644 --- a/winch/codegen/src/masm.rs +++ b/winch/codegen/src/masm.rs @@ -137,6 +137,7 @@ pub(crate) enum FloatCmpKind { /// Kinds of shifts in WebAssembly.The [`masm`] implementation for each ISA is /// responsible for emitting the correct sequence of instructions when /// lowering to machine code. +#[derive(Debug, Clone, Copy, Eq, PartialEq)] pub(crate) enum ShiftKind { /// Left shift. Shl, @@ -694,8 +695,11 @@ pub(crate) trait MacroAssembler { /// Perform logical exclusive or operation. fn xor(&mut self, dst: Reg, lhs: Reg, rhs: RegImm, size: OperandSize); - /// Perform a shift operation. - /// Shift is special in that some architectures have specific expectations + /// Perform a shift operation between a register and an immediate. + fn shift_ir(&mut self, dst: Reg, imm: u64, lhs: Reg, kind: ShiftKind, size: OperandSize); + + /// Perform a shift operation between two registers. + /// This case is special in that some architectures have specific expectations /// regarding the location of the instruction arguments. To free the /// caller from having to deal with the architecture specific constraints /// we give this function access to the code generation context, allowing diff --git a/winch/codegen/src/visitor.rs b/winch/codegen/src/visitor.rs index fae3189df8..85bdbce735 100644 --- a/winch/codegen/src/visitor.rs +++ b/winch/codegen/src/visitor.rs @@ -1070,73 +1070,63 @@ where } fn visit_i32_shl(&mut self) { - use OperandSize::*; use ShiftKind::*; - self.masm.shift(&mut self.context, Shl, S32); + self.context.i32_shift(self.masm, Shl); } fn visit_i64_shl(&mut self) { - use OperandSize::*; use ShiftKind::*; - self.masm.shift(&mut self.context, Shl, S64); + self.context.i64_shift(self.masm, Shl); } fn visit_i32_shr_s(&mut self) { - use OperandSize::*; use ShiftKind::*; - self.masm.shift(&mut self.context, ShrS, S32); + self.context.i32_shift(self.masm, ShrS); } fn visit_i64_shr_s(&mut self) { - use OperandSize::*; use ShiftKind::*; - self.masm.shift(&mut self.context, ShrS, S64); + self.context.i64_shift(self.masm, ShrS); } fn visit_i32_shr_u(&mut self) { - use OperandSize::*; use ShiftKind::*; - self.masm.shift(&mut self.context, ShrU, S32); + self.context.i32_shift(self.masm, ShrU); } fn visit_i64_shr_u(&mut self) { - use OperandSize::*; use ShiftKind::*; - self.masm.shift(&mut self.context, ShrU, S64); + self.context.i64_shift(self.masm, ShrU); } fn visit_i32_rotl(&mut self) { - use OperandSize::*; use ShiftKind::*; - self.masm.shift(&mut self.context, Rotl, S32); + self.context.i32_shift(self.masm, Rotl); } fn visit_i64_rotl(&mut self) { - use OperandSize::*; use ShiftKind::*; - self.masm.shift(&mut self.context, Rotl, S64); + self.context.i64_shift(self.masm, Rotl); } fn visit_i32_rotr(&mut self) { - use OperandSize::*; use ShiftKind::*; - self.masm.shift(&mut self.context, Rotr, S32); + self.context.i32_shift(self.masm, Rotr); } fn visit_i64_rotr(&mut self) { - use OperandSize::*; use ShiftKind::*; - self.masm.shift(&mut self.context, Rotr, S64); + self.context.i64_shift(self.masm, Rotr); } fn visit_end(&mut self) {