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cranelift: Remove nominal-sp (#8643)

* Update the frame layout comment

* Remove more references to nominal SP

* Remove the nominal_sp_offset from backend emit states

* Continue removing references to the nominal sp

* Remove nominal-sp from the aarch64 backend

* Remove nominal-sp from the s390x backend

* Remove nominal-sp from the riscv64 backend

* Remove old comment
pull/8646/head
Trevor Elliott 6 months ago
committed by GitHub
parent
commit
e165106b1a
No known key found for this signature in database GPG Key ID: B5690EEEBB952194
  1. 7
      cranelift/codegen/src/isa/aarch64/abi.rs
  2. 12
      cranelift/codegen/src/isa/aarch64/inst.isle
  3. 2
      cranelift/codegen/src/isa/aarch64/inst/args.rs
  4. 15
      cranelift/codegen/src/isa/aarch64/inst/emit.rs
  5. 2
      cranelift/codegen/src/isa/aarch64/inst/mod.rs
  6. 2
      cranelift/codegen/src/isa/aarch64/pcc.rs
  7. 5
      cranelift/codegen/src/isa/riscv64/abi.rs
  8. 26
      cranelift/codegen/src/isa/riscv64/inst/args.rs
  9. 2
      cranelift/codegen/src/isa/riscv64/inst/emit.rs
  10. 5
      cranelift/codegen/src/isa/riscv64/lower/isle.rs
  11. 13
      cranelift/codegen/src/isa/s390x/abi.rs
  12. 16
      cranelift/codegen/src/isa/s390x/inst/args.rs
  13. 8
      cranelift/codegen/src/isa/s390x/inst/emit.rs
  14. 2
      cranelift/codegen/src/isa/s390x/inst/mod.rs
  15. 12
      cranelift/codegen/src/isa/x64/abi.rs
  16. 22
      cranelift/codegen/src/isa/x64/inst/args.rs
  17. 7
      cranelift/codegen/src/isa/x64/inst/emit_state.rs
  18. 65
      cranelift/codegen/src/machinst/abi.rs
  19. 4
      cranelift/codegen/src/machinst/buffer.rs
  20. 4
      cranelift/codegen/src/machinst/mod.rs
  21. 6
      cranelift/filetests/filetests/isa/riscv64/c-inline-probestack.clif
  22. 6
      cranelift/filetests/filetests/isa/riscv64/inline-probestack.clif
  23. 106
      cranelift/filetests/filetests/isa/riscv64/issue-6954.clif
  24. 12
      cranelift/filetests/filetests/isa/riscv64/reftypes.clif
  25. 12
      cranelift/filetests/filetests/isa/riscv64/return-call-indirect.clif
  26. 26
      cranelift/filetests/filetests/isa/riscv64/return-call.clif
  27. 4
      cranelift/filetests/filetests/isa/riscv64/simd-abi-large-spill.clif
  28. 8
      cranelift/filetests/filetests/isa/riscv64/simd-abi.clif
  29. 172
      cranelift/filetests/filetests/isa/riscv64/stack.clif
  30. 44
      cranelift/filetests/filetests/isa/riscv64/tail-call-conv.clif
  31. 26
      cranelift/filetests/filetests/isa/riscv64/zca.clif
  32. 4
      cranelift/filetests/filetests/isa/riscv64/zcd.clif

7
cranelift/codegen/src/isa/aarch64/abi.rs

@ -38,7 +38,7 @@ impl Into<AMode> for StackAMode {
StackAMode::IncomingArg(off, stack_args_size) => AMode::IncomingArg {
off: i64::from(stack_args_size) - off,
},
StackAMode::Slot(off) => AMode::NominalSPOffset { off },
StackAMode::Slot(off) => AMode::SlotOffset { off },
StackAMode::OutgoingArg(off) => AMode::SPOffset { off },
}
}
@ -1132,11 +1132,6 @@ impl ABIMachineSpec for AArch64MachineDeps {
}
}
/// Get the nominal-SP-to-FP offset from an instruction-emission state.
fn get_nominal_sp_to_fp(s: &EmitState) -> i64 {
s.nominal_sp_to_fp
}
fn get_machine_env(flags: &settings::Flags, _call_conv: isa::CallConv) -> &MachineEnv {
if flags.enable_pinned_reg() {
static MACHINE_ENV: OnceLock<MachineEnv> = OnceLock::new();

12
cranelift/codegen/src/isa/aarch64/inst.isle

@ -1178,19 +1178,17 @@
(IncomingArg
(off i64))
;; Offset from the "nominal stack pointer", which is where the real SP is
;; just after stack and spill slots are allocated in the function prologue.
;; Offset into the slot area of the stack, which lies just above the
;; outgoing argument area that's setup by the function prologue.
;; At emission time, this is converted to `SPOffset` with a fixup added to
;; the offset constant. The fixup is a running value that is tracked as
;; emission iterates through instructions in linear order, and can be
;; adjusted up and down with [Inst::VirtualSPOffsetAdj].
;;
;; The standard ABI is in charge of handling this (by emitting the
;; adjustment meta-instructions). It maintains the invariant that "nominal
;; SP" is where the actual SP is after the function prologue and before
;; clobber pushes. See the diagram in the documentation for
;; [crate::isa::aarch64::abi](the ABI module) for more details.
(NominalSPOffset
;; adjustment meta-instructions). See the diagram in the documentation
;; for [crate::isa::aarch64::abi](the ABI module) for more details.
(SlotOffset
(off i64))))
;; A memory argument to a load/store-pair.

2
cranelift/codegen/src/isa/aarch64/inst/args.rs

@ -400,7 +400,7 @@ impl PrettyPrint for AMode {
&AMode::SPOffset { .. }
| &AMode::FPOffset { .. }
| &AMode::IncomingArg { .. }
| &AMode::NominalSPOffset { .. }
| &AMode::SlotOffset { .. }
| &AMode::RegOffset { .. } => {
panic!("Unexpected pseudo mem-arg mode: {:?}", self)
}

15
cranelift/codegen/src/isa/aarch64/inst/emit.rs

@ -22,11 +22,11 @@ pub fn mem_finalize(
| &AMode::SPOffset { off }
| &AMode::FPOffset { off }
| &AMode::IncomingArg { off }
| &AMode::NominalSPOffset { off } => {
| &AMode::SlotOffset { off } => {
let basereg = match mem {
&AMode::RegOffset { rn, .. } => rn,
&AMode::SPOffset { .. }
| &AMode::NominalSPOffset { .. }
| &AMode::SlotOffset { .. }
| &AMode::IncomingArg { .. } => stack_reg(),
&AMode::FPOffset { .. } => fp_reg(),
_ => unreachable!(),
@ -42,10 +42,10 @@ pub fn mem_finalize(
+ frame_layout.outgoing_args_size,
) - off
}
&AMode::NominalSPOffset { .. } => {
&AMode::SlotOffset { .. } => {
let adj = i64::from(state.frame_layout().outgoing_args_size);
trace!(
"mem_finalize: nominal SP offset {} + adj {} -> {}",
"mem_finalize: slot offset {} + adj {} -> {}",
off,
adj,
off + adj
@ -651,8 +651,6 @@ fn enc_asimd_mod_imm(rd: Writable<Reg>, q_op: u32, cmode: u32, imm: u8) -> u32 {
/// State carried between emissions of a sequence of instructions.
#[derive(Default, Clone, Debug)]
pub struct EmitState {
/// Offset of FP from nominal-SP.
pub(crate) nominal_sp_to_fp: i64,
/// Safepoint stack map for upcoming instruction, as provided to `pre_safepoint()`.
stack_map: Option<StackMap>,
/// Only used during fuzz-testing. Otherwise, it is a zero-sized struct and
@ -664,7 +662,6 @@ pub struct EmitState {
impl MachInstEmitState<Inst> for EmitState {
fn new(abi: &Callee<AArch64MachineDeps>, ctrl_plane: ControlPlane) -> Self {
EmitState {
nominal_sp_to_fp: abi.frame_size() as i64,
stack_map: None,
ctrl_plane,
frame_layout: abi.frame_layout().clone(),
@ -1076,7 +1073,7 @@ impl MachInstEmit for Inst {
&AMode::SPOffset { .. }
| &AMode::FPOffset { .. }
| &AMode::IncomingArg { .. }
| &AMode::NominalSPOffset { .. }
| &AMode::SlotOffset { .. }
| &AMode::Const { .. }
| &AMode::RegOffset { .. } => {
panic!("Should not see {:?} here!", mem)
@ -1170,7 +1167,7 @@ impl MachInstEmit for Inst {
&AMode::SPOffset { .. }
| &AMode::FPOffset { .. }
| &AMode::IncomingArg { .. }
| &AMode::NominalSPOffset { .. }
| &AMode::SlotOffset { .. }
| &AMode::Const { .. }
| &AMode::RegOffset { .. } => {
panic!("Should not see {:?} here!", mem)

2
cranelift/codegen/src/isa/aarch64/inst/mod.rs

@ -411,7 +411,7 @@ fn memarg_operands(memarg: &mut AMode, collector: &mut impl OperandVisitor) {
AMode::Label { .. } => {}
AMode::SPPreIndexed { .. } | AMode::SPPostIndexed { .. } => {}
AMode::FPOffset { .. } | AMode::IncomingArg { .. } => {}
AMode::SPOffset { .. } | AMode::NominalSPOffset { .. } => {}
AMode::SPOffset { .. } | AMode::SlotOffset { .. } => {}
AMode::RegOffset { rn, .. } => {
collector.reg_use(rn);
}

2
cranelift/codegen/src/isa/aarch64/pcc.rs

@ -507,7 +507,7 @@ fn check_addr<'a>(
&AMode::SPOffset { .. }
| &AMode::FPOffset { .. }
| &AMode::IncomingArg { .. }
| &AMode::NominalSPOffset { .. }
| &AMode::SlotOffset { .. }
| &AMode::SPPostIndexed { .. }
| &AMode::SPPreIndexed { .. } => {
// We trust ABI code (for now!) and no lowering rules

5
cranelift/codegen/src/isa/riscv64/abi.rs

@ -682,11 +682,6 @@ impl ABIMachineSpec for Riscv64MachineDeps {
}
}
/// Get the nominal-SP-to-FP offset from an instruction-emission state.
fn get_nominal_sp_to_fp(s: &EmitState) -> i64 {
s.nominal_sp_to_fp
}
fn get_machine_env(_flags: &settings::Flags, _call_conv: isa::CallConv) -> &MachineEnv {
static MACHINE_ENV: OnceLock<MachineEnv> = OnceLock::new();
MACHINE_ENV.get_or_init(create_reg_enviroment)

26
cranelift/codegen/src/isa/riscv64/inst/args.rs

@ -87,19 +87,17 @@ pub enum AMode {
/// Offset from the frame pointer.
FPOffset(i64),
/// Offset from the "nominal stack pointer", which is where the real SP is
/// just after stack and spill slots are allocated in the function prologue.
/// Offset into the slot area of the stack, which lies just above the
/// outgoing argument area that's setup by the function prologue.
/// At emission time, this is converted to `SPOffset` with a fixup added to
/// the offset constant. The fixup is a running value that is tracked as
/// emission iterates through instructions in linear order, and can be
/// adjusted up and down with [Inst::VirtualSPOffsetAdj].
///
/// The standard ABI is in charge of handling this (by emitting the
/// adjustment meta-instructions). It maintains the invariant that "nominal
/// SP" is where the actual SP is after the function prologue and before
/// clobber pushes. See the diagram in the documentation for
/// [crate::isa::riscv64::abi](the ABI module) for more details.
NominalSPOffset(i64),
/// adjustment meta-instructions). See the diagram in the documentation
/// for [crate::isa::aarch64::abi](the ABI module) for more details.
SlotOffset(i64),
/// Offset into the argument area.
IncomingArg(i64),
@ -120,7 +118,7 @@ impl AMode {
// Registers used in these modes aren't allocatable.
AMode::SPOffset(..)
| AMode::FPOffset(..)
| AMode::NominalSPOffset(..)
| AMode::SlotOffset(..)
| AMode::IncomingArg(..)
| AMode::Const(..)
| AMode::Label(..) => {}
@ -132,7 +130,7 @@ impl AMode {
&AMode::RegOffset(reg, ..) => Some(reg),
&AMode::SPOffset(..) => Some(stack_reg()),
&AMode::FPOffset(..) => Some(fp_reg()),
&AMode::NominalSPOffset(..) => Some(stack_reg()),
&AMode::SlotOffset(..) => Some(stack_reg()),
&AMode::IncomingArg(..) => Some(stack_reg()),
&AMode::Const(..) | AMode::Label(..) => None,
}
@ -140,7 +138,7 @@ impl AMode {
pub(crate) fn get_offset_with_state(&self, state: &EmitState) -> i64 {
match self {
&AMode::NominalSPOffset(offset) => {
&AMode::SlotOffset(offset) => {
offset + i64::from(state.frame_layout().outgoing_args_size)
}
@ -171,7 +169,7 @@ impl AMode {
| &AMode::SPOffset(..)
| &AMode::FPOffset(..)
| &AMode::IncomingArg(..)
| &AMode::NominalSPOffset(..) => None,
| &AMode::SlotOffset(..) => None,
}
}
}
@ -185,8 +183,8 @@ impl Display for AMode {
&AMode::SPOffset(offset, ..) => {
write!(f, "{}(sp)", offset)
}
&AMode::NominalSPOffset(offset, ..) => {
write!(f, "{}(nominal_sp)", offset)
&AMode::SlotOffset(offset, ..) => {
write!(f, "{}(slot)", offset)
}
&AMode::IncomingArg(offset) => {
write!(f, "-{}(incoming_arg)", offset)
@ -211,7 +209,7 @@ impl Into<AMode> for StackAMode {
AMode::IncomingArg(i64::from(stack_args_size) - offset)
}
StackAMode::OutgoingArg(offset) => AMode::SPOffset(offset),
StackAMode::Slot(offset) => AMode::NominalSPOffset(offset),
StackAMode::Slot(offset) => AMode::SlotOffset(offset),
}
}
}

2
cranelift/codegen/src/isa/riscv64/inst/emit.rs

@ -46,7 +46,6 @@ pub enum EmitVState {
/// State carried between emissions of a sequence of instructions.
#[derive(Default, Clone, Debug)]
pub struct EmitState {
pub(crate) nominal_sp_to_fp: i64,
/// Safepoint stack map for upcoming instruction, as provided to `pre_safepoint()`.
stack_map: Option<StackMap>,
/// Only used during fuzz-testing. Otherwise, it is a zero-sized struct and
@ -70,7 +69,6 @@ impl MachInstEmitState<Inst> for EmitState {
ctrl_plane: ControlPlane,
) -> Self {
EmitState {
nominal_sp_to_fp: abi.frame_size() as i64,
stack_map: None,
ctrl_plane,
vstate: EmitVState::Unknown,

5
cranelift/codegen/src/isa/riscv64/lower/isle.rs

@ -412,11 +412,10 @@ impl generated_code::Context for RV64IsleContext<'_, '_, MInst, Riscv64Backend>
}
fn gen_stack_slot_amode(&mut self, ss: StackSlot, offset: i64) -> AMode {
// Offset from beginning of stackslot area, which is at nominal SP (see
// [MemArg::NominalSPOffset] for more details on nominal SP tracking).
// Offset from beginning of stackslot area.
let stack_off = self.lower_ctx.abi().sized_stackslot_offsets()[ss] as i64;
let sp_off: i64 = stack_off + offset;
AMode::NominalSPOffset(sp_off)
AMode::SlotOffset(sp_off)
}
fn gen_const_amode(&mut self, c: VCodeConstant) -> AMode {

13
cranelift/codegen/src/isa/s390x/abi.rs

@ -50,11 +50,11 @@
//! +---------------------------+
//! | ... |
//! | spill slots |
//! | (accessed via nominal SP) |
//! | (accessed via SP) |
//! | ... |
//! | stack slots |
//! | (accessed via nominal SP) |
//! nominal SP ---------------> | (alloc'd by prologue) |
//! | (accessed via SP) |
//! | (alloc'd by prologue) |
//! +---------------------------+
//! | ... |
//! | args for call |
@ -193,7 +193,7 @@ impl Into<MemArg> for StackAMode {
match self {
// Argument area always begins at the initial SP.
StackAMode::IncomingArg(off, _) => MemArg::InitialSPOffset { off },
StackAMode::Slot(off) => MemArg::NominalSPOffset { off },
StackAMode::Slot(off) => MemArg::SlotOffset { off },
StackAMode::OutgoingArg(off) => {
MemArg::reg_plus_off(stack_reg(), off, MemFlags::trusted())
}
@ -765,11 +765,6 @@ impl ABIMachineSpec for S390xMachineDeps {
}
}
/// Get the nominal-SP-to-FP offset from an instruction-emission state.
fn get_nominal_sp_to_fp(s: &EmitState) -> i64 {
s.initial_sp_offset
}
fn get_machine_env(_flags: &settings::Flags, _call_conv: isa::CallConv) -> &MachineEnv {
static MACHINE_ENV: OnceLock<MachineEnv> = OnceLock::new();
MACHINE_ENV.get_or_init(create_machine_env)

16
cranelift/codegen/src/isa/s390x/inst/args.rs

@ -49,19 +49,17 @@ pub enum MemArg {
/// Offset from the stack pointer at function entry.
InitialSPOffset { off: i64 },
/// Offset from the "nominal stack pointer", which is where the real SP is
/// just after stack and spill slots are allocated in the function prologue.
/// Offset into the slot area of the stack, which lies just above the
/// outgoing argument area that's setup by the function prologue.
/// At emission time, this is converted to `SPOffset` with a fixup added to
/// the offset constant. The fixup is a running value that is tracked as
/// emission iterates through instructions in linear order, and can be
/// adjusted up and down with [Inst::VirtualSPOffsetAdj].
///
/// The standard ABI is in charge of handling this (by emitting the
/// adjustment meta-instructions). It maintains the invariant that "nominal
/// SP" is where the actual SP is after the function prologue and before
/// clobber pushes. See the diagram in the documentation for
/// [crate::isa::s390x::abi](the ABI module) for more details.
NominalSPOffset { off: i64 },
/// adjustment meta-instructions). See the diagram in the documentation
/// for [crate::isa::aarch64::abi](the ABI module) for more details.
SlotOffset { off: i64 },
}
impl MemArg {
@ -98,7 +96,7 @@ impl MemArg {
MemArg::Label { .. } => MemFlags::trusted(),
MemArg::Symbol { flags, .. } => *flags,
MemArg::InitialSPOffset { .. } => MemFlags::trusted(),
MemArg::NominalSPOffset { .. } => MemFlags::trusted(),
MemArg::SlotOffset { .. } => MemFlags::trusted(),
}
}
}
@ -268,7 +266,7 @@ impl PrettyPrint for MemArg {
} => format!("{} + {}", name.display(None), offset),
// Eliminated by `mem_finalize()`.
&MemArg::InitialSPOffset { .. }
| &MemArg::NominalSPOffset { .. }
| &MemArg::SlotOffset { .. }
| &MemArg::RegOffset { .. } => {
panic!("Unexpected pseudo mem-arg mode (stack-offset or generic reg-offset)!")
}

8
cranelift/codegen/src/isa/s390x/inst/emit.rs

@ -68,19 +68,17 @@ pub fn mem_finalize(
let mem = match mem {
&MemArg::RegOffset { off, .. }
| &MemArg::InitialSPOffset { off }
| &MemArg::NominalSPOffset { off } => {
| &MemArg::SlotOffset { off } => {
let base = match mem {
&MemArg::RegOffset { reg, .. } => reg,
&MemArg::InitialSPOffset { .. } | &MemArg::NominalSPOffset { .. } => stack_reg(),
&MemArg::InitialSPOffset { .. } | &MemArg::SlotOffset { .. } => stack_reg(),
_ => unreachable!(),
};
let adj = match mem {
&MemArg::InitialSPOffset { .. } => {
state.initial_sp_offset + i64::from(state.frame_layout().outgoing_args_size)
}
&MemArg::NominalSPOffset { .. } => {
i64::from(state.frame_layout().outgoing_args_size)
}
&MemArg::SlotOffset { .. } => i64::from(state.frame_layout().outgoing_args_size),
_ => 0,
};
let off = off + adj;

2
cranelift/codegen/src/isa/s390x/inst/mod.rs

@ -398,7 +398,7 @@ fn memarg_operands(memarg: &mut MemArg, collector: &mut impl OperandVisitor) {
MemArg::RegOffset { reg, .. } => {
collector.reg_use(reg);
}
MemArg::InitialSPOffset { .. } | MemArg::NominalSPOffset { .. } => {}
MemArg::InitialSPOffset { .. } | MemArg::SlotOffset { .. } => {}
}
// mem_finalize might require %r1 to hold (part of) the address.
// Conservatively assume this will always be necessary here.

12
cranelift/codegen/src/isa/x64/abi.rs

@ -753,9 +753,9 @@ impl ABIMachineSpec for X64ABIMachineSpec {
) -> SmallVec<[Self::I; 16]> {
let mut insts = SmallVec::new();
// Restore regs by loading from offsets of RSP. RSP will be
// returned to nominal-RSP at this point, so we can use the
// same offsets that we used when saving clobbers above.
// Restore regs by loading from offsets of RSP. We compute the offset from
// the same base as above in clobber_save, as RSP won't change between the
// prologue and epilogue.
let mut cur_offset =
frame_layout.fixed_frame_storage_size + frame_layout.outgoing_args_size;
for reg in &frame_layout.clobbered_callee_saves {
@ -916,10 +916,6 @@ impl ABIMachineSpec for X64ABIMachineSpec {
}
}
fn get_nominal_sp_to_fp(s: &<Self::I as MachInstEmit>::State) -> i64 {
s.nominal_sp_to_fp()
}
fn get_machine_env(flags: &settings::Flags, _call_conv: isa::CallConv) -> &MachineEnv {
if flags.enable_pinned_reg() {
static MACHINE_ENV: OnceLock<MachineEnv> = OnceLock::new();
@ -1058,7 +1054,7 @@ impl From<StackAMode> for SyntheticAmode {
StackAMode::Slot(off) => {
let off = i32::try_from(off)
.expect("Offset in Slot is greater than 2GB; should hit impl limit first");
SyntheticAmode::nominal_sp_offset(off)
SyntheticAmode::slot_offset(off)
}
StackAMode::OutgoingArg(off) => {
let off = i32::try_from(off).expect(

22
cranelift/codegen/src/isa/x64/inst/args.rs

@ -463,10 +463,10 @@ pub enum SyntheticAmode {
offset: u32,
},
/// A (virtual) offset to the "nominal SP" value, which will be recomputed as we push and pop
/// within the function.
NominalSPOffset {
/// The nominal stack pointer value.
/// A (virtual) offset to the slot area of the function frame, which lies just above the
/// outgoing arguments.
SlotOffset {
/// The offset into the slot area.
simm32: i32,
},
@ -480,8 +480,8 @@ impl SyntheticAmode {
Self::Real(amode)
}
pub(crate) fn nominal_sp_offset(simm32: i32) -> Self {
SyntheticAmode::NominalSPOffset { simm32 }
pub(crate) fn slot_offset(simm32: i32) -> Self {
SyntheticAmode::SlotOffset { simm32 }
}
/// Add the registers mentioned by `self` to `collector`.
@ -491,7 +491,7 @@ impl SyntheticAmode {
SyntheticAmode::IncomingArg { .. } => {
// Nothing to do; the base is known and isn't involved in regalloc.
}
SyntheticAmode::NominalSPOffset { .. } => {
SyntheticAmode::SlotOffset { .. } => {
// Nothing to do; the base is SP and isn't involved in regalloc.
}
SyntheticAmode::ConstantOffset(_) => {}
@ -505,7 +505,7 @@ impl SyntheticAmode {
SyntheticAmode::IncomingArg { .. } => {
// Nothing to do; the base is known and isn't involved in regalloc.
}
SyntheticAmode::NominalSPOffset { .. } => {
SyntheticAmode::SlotOffset { .. } => {
// Nothing to do; the base is SP and isn't involved in regalloc.
}
SyntheticAmode::ConstantOffset(_) => {}
@ -525,7 +525,7 @@ impl SyntheticAmode {
regs::rbp(),
)
}
SyntheticAmode::NominalSPOffset { simm32 } => {
SyntheticAmode::SlotOffset { simm32 } => {
let off = *simm32 as i64 + i64::from(state.frame_layout().outgoing_args_size);
Amode::imm_reg(off.try_into().expect("invalid sp offset"), regs::rsp())
}
@ -539,7 +539,7 @@ impl SyntheticAmode {
match self {
SyntheticAmode::Real(addr) => addr.aligned(),
&SyntheticAmode::IncomingArg { .. }
| SyntheticAmode::NominalSPOffset { .. }
| SyntheticAmode::SlotOffset { .. }
| SyntheticAmode::ConstantOffset { .. } => true,
}
}
@ -565,7 +565,7 @@ impl PrettyPrint for SyntheticAmode {
&SyntheticAmode::IncomingArg { offset } => {
format!("rbp(stack args max - {offset})")
}
SyntheticAmode::NominalSPOffset { simm32 } => {
SyntheticAmode::SlotOffset { simm32 } => {
format!("rsp({} + virtual offset)", *simm32)
}
SyntheticAmode::ConstantOffset(c) => format!("const({})", c.as_u32()),

7
cranelift/codegen/src/isa/x64/inst/emit_state.rs

@ -4,8 +4,6 @@ use cranelift_control::ControlPlane;
/// State carried between emissions of a sequence of instructions.
#[derive(Default, Clone, Debug)]
pub struct EmitState {
/// Offset of FP from nominal-SP.
nominal_sp_to_fp: i64,
/// Safepoint stack map for upcoming instruction, as provided to `pre_safepoint()`.
stack_map: Option<StackMap>,
/// Only used during fuzz-testing. Otherwise, it is a zero-sized struct and
@ -20,7 +18,6 @@ pub struct EmitState {
impl MachInstEmitState<Inst> for EmitState {
fn new(abi: &Callee<X64ABIMachineSpec>, ctrl_plane: ControlPlane) -> Self {
EmitState {
nominal_sp_to_fp: abi.frame_size() as i64,
stack_map: None,
ctrl_plane,
frame_layout: abi.frame_layout().clone(),
@ -52,8 +49,4 @@ impl EmitState {
pub(crate) fn clear_post_insn(&mut self) {
self.stack_map = None;
}
pub(crate) fn nominal_sp_to_fp(&self) -> i64 {
self.nominal_sp_to_fp
}
}

65
cranelift/codegen/src/machinst/abi.rs

@ -38,28 +38,20 @@
//! We assume that a prologue first pushes the frame pointer (and
//! return address above that, if the machine does not do that in
//! hardware). We set FP to point to this two-word frame record. We
//! store all other frame slots below this two-word frame record, with
//! the stack pointer remaining at or below this fixed frame storage
//! for the rest of the function. We can then access frame storage
//! slots using positive offsets from SP. In order to allow codegen
//! for the latter before knowing how SP might be adjusted around
//! callsites, we implement a "nominal SP" tracking feature by which a
//! fixup (distance between actual SP and a "nominal" SP) is known at
//! each instruction. When the prologue is finished, SP is expected
//! to point at the bottom of the outgoing argument area, and will
//! only move again directly around function calls. This allows the
//! use of fixed offsets from SP for the rest of the function body.
//! store all other frame slots below this two-word frame record, as
//! well as enough space for arguments to the largest possible
//! function call. The stack pointer then remains at this position
//! for the duration of the function, allowing us to address all
//! frame storage at positive offsets from SP.
//!
//! Note that if we ever support dynamic stack-space allocation (for
//! `alloca`), we will need a way to reference spill slots and stack
//! slots without "nominal SP", because we will no longer be able to
//! know a static offset from SP to the slots at any particular
//! slots relative to a dynamic SP, because we will no longer be able
//! to know a static offset from SP to the slots at any particular
//! program point. Probably the best solution at that point will be to
//! revert to using the frame pointer as the reference for all slots,
//! and creating a "nominal FP" synthetic addressing mode (analogous
//! to "nominal SP" today) to allow generating spill/reload and
//! stackslot accesses before we know how large the clobber-saves will
//! be.
//! to allow generating spill/reload and stackslot accesses before we
//! know how large the clobber-saves will be.
//!
//! # Stack Layout
//!
@ -71,7 +63,7 @@
//! +---------------------------+
//! | ... |
//! | stack args |
//! | (accessed via FP) |
//! Canonical Frame Address --> | (accessed via FP) |
//! +---------------------------+
//! SP at function entry -----> | return address |
//! +---------------------------+
@ -83,16 +75,16 @@
//! +---------------------------+
//! | ... |
//! | spill slots |
//! | (accessed via nominal SP) |
//! | (accessed via SP) |
//! | ... |
//! | stack slots |
//! | (accessed via nominal SP) |
//! nominal SP ---------------> | (alloc'd by prologue) |
//! | (accessed via SP) |
//! | (alloc'd by prologue) |
//! +---------------------------+
//! | [alignment as needed] |
//! | ... |
//! | args for call |
//! SP -----------------------> | (pushed at callsite) |
//! | args for largest call |
//! SP -----------------------> | (alloc'd by prologue) |
//! +---------------------------+
//!
//! (low address)
@ -577,9 +569,6 @@ pub trait ABIMachineSpec {
isa_flags: &Self::F,
) -> u32;
/// Get the "nominal SP to FP" offset from an instruction-emission state.
fn get_nominal_sp_to_fp(s: &<Self::I as MachInstEmit>::State) -> i64;
/// Get the ABI-dependent MachineEnv for managing register allocation.
fn get_machine_env(flags: &settings::Flags, call_conv: isa::CallConv) -> &MachineEnv;
@ -994,8 +983,7 @@ pub struct FrameLayout {
pub clobber_size: u32,
/// Storage allocated for the fixed part of the stack frame.
/// This contains stack slots and spill slots. The "nominal SP"
/// during execution of the function points to the bottom of this.
/// This contains stack slots and spill slots.
pub fixed_frame_storage_size: u32,
/// Stack size to be reserved for outgoing arguments, if used by
@ -1665,8 +1653,7 @@ impl<M: ABIMachineSpec> Callee<M> {
offset: u32,
into_reg: Writable<Reg>,
) -> M::I {
// Offset from beginning of stackslot area, which is at nominal SP (see
// [MemArg::NominalSPOffset] for more details on nominal SP tracking).
// Offset from beginning of stackslot area.
let stack_off = self.sized_stackslots[slot] as i64;
let sp_off: i64 = stack_off + (offset as i64);
M::gen_get_stack_addr(StackAMode::Slot(sp_off), into_reg)
@ -1708,13 +1695,13 @@ impl<M: ABIMachineSpec> Callee<M> {
) -> StackMap {
let frame_layout = state.frame_layout();
let outgoing_args_size = frame_layout.outgoing_args_size;
let nominal_sp_to_fp = M::get_nominal_sp_to_fp(state);
let clobbers_and_slots = frame_layout.fixed_frame_storage_size + frame_layout.clobber_size;
trace!(
"spillslots_to_stackmap: slots = {:?}, state = {:?}",
slots,
state
);
let map_size = outgoing_args_size + u32::try_from(nominal_sp_to_fp).unwrap();
let map_size = outgoing_args_size + clobbers_and_slots;
let bytes = M::word_bytes();
let map_words = (map_size + bytes - 1) / bytes;
let mut bits = std::iter::repeat(false)
@ -1823,10 +1810,6 @@ impl<M: ABIMachineSpec> Callee<M> {
&frame_layout,
));
// N.B.: "nominal SP", which we use to refer to stackslots and
// spillslots, is defined to be equal to the stack pointer at this point
// in the prologue.
insts
}
@ -1846,12 +1829,6 @@ impl<M: ABIMachineSpec> Callee<M> {
&frame_layout,
));
// N.B.: we do *not* emit a nominal SP adjustment here, because (i) there will be no
// references to nominal SP offsets before the return below, and (ii) the instruction
// emission tracks running SP offset linearly (in straight-line order), not according to
// the CFG, so early returns in the middle of function bodies would cause an incorrect
// offset for the rest of the body.
// Tear down frame.
insts.extend(M::gen_epilogue_frame_restore(
self.call_conv,
@ -1917,9 +1894,9 @@ impl<M: ABIMachineSpec> Callee<M> {
M::get_number_of_spillslots_for_value(rc, max, &self.isa_flags)
}
/// Get the spill slot offset relative to nominal SP.
/// Get the spill slot offset relative to the fixed allocation area start.
pub fn get_spillslot_offset(&self, slot: SpillSlot) -> i64 {
// Offset from beginning of spillslot area, which is at nominal SP + stackslots_size.
// Offset from beginning of spillslot area.
let islot = slot.index() as i64;
let spill_off = islot * M::word_bytes() as i64;
let sp_off = self.stackslots_size as i64 + spill_off;

4
cranelift/codegen/src/machinst/buffer.rs

@ -1659,10 +1659,6 @@ impl<I: VCodeInst> MachBuffer<I> {
/// Add stack map metadata for this program point: a set of stack offsets
/// (from SP upward) that contain live references.
///
/// The `offset_to_fp` value is the offset from the nominal SP (at which the `stack_offsets`
/// are based) and the FP value. By subtracting `offset_to_fp` from each `stack_offsets`
/// element, one can obtain live-reference offsets from FP instead.
pub fn add_stack_map(&mut self, extent: StackMapExtent, stack_map: StackMap) {
let (start, end) = match extent {
StackMapExtent::UpcomingBytes(insn_len) => {

4
cranelift/codegen/src/machinst/mod.rs

@ -39,8 +39,8 @@
//! | by instruction emission code.
//! | - prologue and epilogue(s) built and emitted
//! | directly during emission.
//! | - nominal-SP-relative offsets resolved
//! | by tracking EmitState.)
//! | - SP-relative offsets resolved by tracking
//! | EmitState.)
//!
//! ```

6
cranelift/filetests/filetests/isa/riscv64/c-inline-probestack.clif

@ -22,7 +22,7 @@ block0:
; mv fp,sp
; addi sp,sp,-2048
; block0:
; load_addr a0,0(nominal_sp)
; load_addr a0,0(slot)
; lui t6,1
; addi t6,t6,-2048
; add sp,sp,t6
@ -73,7 +73,7 @@ block0:
; lui t6,-3
; add sp,sp,t6
; block0:
; load_addr a0,0(nominal_sp)
; load_addr a0,0(slot)
; lui t6,3
; add sp,sp,t6
; ld ra,8(sp)
@ -125,7 +125,7 @@ block0:
; addi t6,t6,-1696
; add sp,sp,t6
; block0:
; load_addr a0,0(nominal_sp)
; load_addr a0,0(slot)
; lui t6,24
; addi t6,t6,1696
; add sp,sp,t6

6
cranelift/filetests/filetests/isa/riscv64/inline-probestack.clif

@ -22,7 +22,7 @@ block0:
; mv fp,sp
; addi sp,sp,-2048
; block0:
; load_addr a0,0(nominal_sp)
; load_addr a0,0(slot)
; lui t6,1
; addi t6,t6,-2048
; add sp,sp,t6
@ -73,7 +73,7 @@ block0:
; lui t6,-3
; add sp,sp,t6
; block0:
; load_addr a0,0(nominal_sp)
; load_addr a0,0(slot)
; lui t6,3
; add sp,sp,t6
; ld ra,8(sp)
@ -125,7 +125,7 @@ block0:
; addi t6,t6,-1696
; add sp,sp,t6
; block0:
; load_addr a0,0(nominal_sp)
; load_addr a0,0(slot)
; lui t6,24
; addi t6,t6,1696
; add sp,sp,t6

106
cranelift/filetests/filetests/isa/riscv64/issue-6954.clif

@ -132,57 +132,57 @@ block0(v0: i16, v1: f32, v2: f64x2, v3: i32, v4: i8, v5: i64x2, v6: i8, v7: f32x
; li a3,0
; li a4,0
; li a0,0
; sd a4,0(nominal_sp)
; sd a0,8(nominal_sp)
; sd a4,16(nominal_sp)
; sd a0,24(nominal_sp)
; sd a4,32(nominal_sp)
; sd a0,40(nominal_sp)
; sd a4,48(nominal_sp)
; sd a0,56(nominal_sp)
; sd a4,64(nominal_sp)
; sd a0,72(nominal_sp)
; sd a4,80(nominal_sp)
; sd a0,88(nominal_sp)
; sd a4,96(nominal_sp)
; sd a0,104(nominal_sp)
; sd a4,112(nominal_sp)
; sw a3,120(nominal_sp)
; sh a2,124(nominal_sp)
; sd a4,128(nominal_sp)
; sd a0,136(nominal_sp)
; sd a4,144(nominal_sp)
; sd a0,152(nominal_sp)
; sd a4,160(nominal_sp)
; sd a0,168(nominal_sp)
; sd a4,176(nominal_sp)
; sd a0,184(nominal_sp)
; sd a4,192(nominal_sp)
; sd a0,200(nominal_sp)
; sd a4,208(nominal_sp)
; sd a0,216(nominal_sp)
; sd a4,224(nominal_sp)
; sd a0,232(nominal_sp)
; sd a4,240(nominal_sp)
; sw a3,248(nominal_sp)
; sh a2,252(nominal_sp)
; sd a4,256(nominal_sp)
; sd a0,264(nominal_sp)
; sd a4,272(nominal_sp)
; sd a0,280(nominal_sp)
; sd a4,288(nominal_sp)
; sd a0,296(nominal_sp)
; sd a4,304(nominal_sp)
; sd a0,312(nominal_sp)
; sd a4,320(nominal_sp)
; sd a0,328(nominal_sp)
; sd a4,336(nominal_sp)
; sd a0,344(nominal_sp)
; sd a4,352(nominal_sp)
; sd a0,360(nominal_sp)
; sd a4,368(nominal_sp)
; sw a3,376(nominal_sp)
; sh a2,380(nominal_sp)
; sd a4,0(slot)
; sd a0,8(slot)
; sd a4,16(slot)
; sd a0,24(slot)
; sd a4,32(slot)
; sd a0,40(slot)
; sd a4,48(slot)
; sd a0,56(slot)
; sd a4,64(slot)
; sd a0,72(slot)
; sd a4,80(slot)
; sd a0,88(slot)
; sd a4,96(slot)
; sd a0,104(slot)
; sd a4,112(slot)
; sw a3,120(slot)
; sh a2,124(slot)
; sd a4,128(slot)
; sd a0,136(slot)
; sd a4,144(slot)
; sd a0,152(slot)
; sd a4,160(slot)
; sd a0,168(slot)
; sd a4,176(slot)
; sd a0,184(slot)
; sd a4,192(slot)
; sd a0,200(slot)
; sd a4,208(slot)
; sd a0,216(slot)
; sd a4,224(slot)
; sd a0,232(slot)
; sd a4,240(slot)
; sw a3,248(slot)
; sh a2,252(slot)
; sd a4,256(slot)
; sd a0,264(slot)
; sd a4,272(slot)
; sd a0,280(slot)
; sd a4,288(slot)
; sd a0,296(slot)
; sd a4,304(slot)
; sd a0,312(slot)
; sd a4,320(slot)
; sd a0,328(slot)
; sd a4,336(slot)
; sd a0,344(slot)
; sd a4,352(slot)
; sd a0,360(slot)
; sd a4,368(slot)
; sw a3,376(slot)
; sh a2,380(slot)
; sext.w a4,a1
; select v14,v15,v15##condition=(a4 ne zero)
; sext.w a4,a1
@ -227,7 +227,7 @@ block0(v0: i16, v1: f32, v2: f64x2, v3: i32, v4: i8, v5: i64x2, v6: i8, v7: f32x
; select v15,v15,v15##condition=(a0 ne zero)
; vmax.vv v13,v13,v13 #avl=2, #vtype=(e64, m1, ta, ma)
; select v15,v15,v15##condition=(a0 ne zero)
; load_addr a1,3(nominal_sp)
; load_addr a1,3(slot)
; addi a1,a1,0
; andi a3,a1,3
; slli a2,a3,3
@ -241,7 +241,7 @@ block0(v0: i16, v1: f32, v2: f64x2, v3: i32, v4: i8, v5: i64x2, v6: i8, v7: f32x
; select v12,v12,v12##condition=(a0 ne zero)
; select v12,v12,v12##condition=(a0 ne zero)
; select v12,v12,v12##condition=(a0 ne zero)
; vse64.v v13,33(nominal_sp) #avl=2, #vtype=(e64, m1, ta, ma)
; vse64.v v13,33(slot) #avl=2, #vtype=(e64, m1, ta, ma)
; select v13,v12,v12##condition=(a0 ne zero)
; select v13,v13,v13##condition=(a0 ne zero)
; select v13,v13,v13##condition=(a0 ne zero)

12
cranelift/filetests/filetests/isa/riscv64/reftypes.clif

@ -96,26 +96,26 @@ block3(v7: r64, v8: r64):
; block0:
; mv a3,a0
; mv s5,a2
; sd a1,16(nominal_sp)
; sd a1,16(slot)
; mv a0,a3
; mv s9,a3
; load_sym a5,%f+0
; sd s9,8(nominal_sp)
; sd s9,8(slot)
; callind a5
; mv a3,s9
; sd a3,0(nominal_sp)
; sd a3,0(slot)
; andi a5,a0,255
; bne a5,zero,taken(label2),not_taken(label1)
; block1:
; ld a0,16(nominal_sp)
; ld a0,16(slot)
; mv a1,s9
; j label3
; block2:
; mv a0,s9
; ld a1,16(nominal_sp)
; ld a1,16(slot)
; j label3
; block3:
; ld a2,0(nominal_sp)
; ld a2,0(slot)
; mv a3,s5
; sd a2,0(a3)
; ld s5,40(sp)

12
cranelift/filetests/filetests/isa/riscv64/return-call-indirect.clif

@ -268,11 +268,11 @@ block0:
; sd s11,40(sp)
; block0:
; li a0,10
; sd a0,16(nominal_sp)
; sd a0,16(slot)
; li a1,15
; sd a1,8(nominal_sp)
; sd a1,8(slot)
; li a2,20
; sd a2,0(nominal_sp)
; sd a2,0(slot)
; li a3,25
; li a4,30
; li a5,35
@ -315,10 +315,10 @@ block0:
; sd s1,-24(incoming_arg)
; sd a0,-16(incoming_arg)
; sd a1,-8(incoming_arg)
; ld a1,8(nominal_sp)
; ld a0,16(nominal_sp)
; ld a1,8(slot)
; ld a0,16(slot)
; mv t0,a2
; ld a2,0(nominal_sp)
; ld a2,0(slot)
; return_call_ind t0 new_stack_arg_size:144 a0=a0 a1=a1 a2=a2 a3=a3 a4=a4 a5=a5 a6=a6 a7=a7
;
; Disassembled:

26
cranelift/filetests/filetests/isa/riscv64/return-call.clif

@ -286,9 +286,9 @@ block0:
; sd s11,24(sp)
; block0:
; li a0,10
; sd a0,8(nominal_sp)
; sd a0,8(slot)
; li a1,15
; sd a1,0(nominal_sp)
; sd a1,0(slot)
; li a2,20
; li a3,25
; li a4,30
@ -332,8 +332,8 @@ block0:
; sd a0,-16(incoming_arg)
; sd a1,-8(incoming_arg)
; load_sym t0,%tail_callee_stack_args+0
; ld a0,8(nominal_sp)
; ld a1,0(nominal_sp)
; ld a0,8(slot)
; ld a1,0(slot)
; return_call_ind t0 new_stack_arg_size:144 a0=a0 a1=a1 a2=a2 a3=a3 a4=a4 a5=a5 a6=a6 a7=a7
;
; Disassembled:
@ -560,11 +560,11 @@ block2:
; sd s11,40(sp)
; block0:
; li a1,10
; sd a1,16(nominal_sp)
; sd a1,16(slot)
; li a1,15
; sd a1,8(nominal_sp)
; sd a1,8(slot)
; li a2,20
; sd a2,0(nominal_sp)
; sd a2,0(slot)
; li a3,25
; li a4,30
; li a5,35
@ -611,12 +611,12 @@ block2:
; sd s6,-24(incoming_arg)
; sd a0,-16(incoming_arg)
; load_sym t0,%different_callee2+0
; ld a0,16(nominal_sp)
; ld a1,8(nominal_sp)
; ld a2,0(nominal_sp)
; ld a0,16(slot)
; ld a1,8(slot)
; ld a2,0(slot)
; return_call_ind t0 new_stack_arg_size:160 a0=a0 a1=a1 a2=a2 a3=a3 a4=a4 a5=a5 a6=a6 a7=a7
; block2:
; ld a0,16(nominal_sp)
; ld a0,16(slot)
; sd a2,-144(incoming_arg)
; sd a1,-136(incoming_arg)
; sd s5,-128(incoming_arg)
@ -636,8 +636,8 @@ block2:
; sd s7,-16(incoming_arg)
; sd s6,-8(incoming_arg)
; load_sym t0,%different_callee1+0
; ld a1,8(nominal_sp)
; ld a2,0(nominal_sp)
; ld a1,8(slot)
; ld a2,0(slot)
; return_call_ind t0 new_stack_arg_size:144 a0=a0 a1=a1 a2=a2 a3=a3 a4=a4 a5=a5 a6=a6 a7=a7
;
; Disassembled:

4
cranelift/filetests/filetests/isa/riscv64/simd-abi-large-spill.clif

@ -25,10 +25,10 @@ block0:
; block0:
; mv s1,a0
; vle16.v v11,[const(0)] #avl=8, #vtype=(e16, m1, ta, ma)
; vse8.v v11,0(nominal_sp) #avl=16, #vtype=(e8, m1, ta, ma)
; vse8.v v11,0(slot) #avl=16, #vtype=(e8, m1, ta, ma)
; call userextname0
; mv a0,s1
; vle8.v v11,0(nominal_sp) #avl=16, #vtype=(e8, m1, ta, ma)
; vle8.v v11,0(slot) #avl=16, #vtype=(e8, m1, ta, ma)
; vse8.v v11,0(a0) #avl=16, #vtype=(e8, m1, ta, ma)
; ld s1,1032(sp)
; addi sp,sp,1040

8
cranelift/filetests/filetests/isa/riscv64/simd-abi.clif

@ -40,9 +40,9 @@ block0(
; addi sp,sp,-256
; block0:
; vle8.v v11,-544(incoming_arg) #avl=16, #vtype=(e8, m1, ta, ma)
; vse8.v v11,0(nominal_sp) #avl=16, #vtype=(e8, m1, ta, ma)
; vse8.v v11,0(slot) #avl=16, #vtype=(e8, m1, ta, ma)
; vle8.v v13,-528(incoming_arg) #avl=16, #vtype=(e8, m1, ta, ma)
; vse8.v v13,128(nominal_sp) #avl=16, #vtype=(e8, m1, ta, ma)
; vse8.v v13,128(slot) #avl=16, #vtype=(e8, m1, ta, ma)
; vle8.v v13,-512(incoming_arg) #avl=16, #vtype=(e8, m1, ta, ma)
; vle8.v v15,-496(incoming_arg) #avl=16, #vtype=(e8, m1, ta, ma)
; vle8.v v10,-480(incoming_arg) #avl=16, #vtype=(e8, m1, ta, ma)
@ -107,9 +107,9 @@ block0(
; vse8.v v10,464(a0) #avl=16, #vtype=(e8, m1, ta, ma)
; vse8.v v15,480(a0) #avl=16, #vtype=(e8, m1, ta, ma)
; vse8.v v13,496(a0) #avl=16, #vtype=(e8, m1, ta, ma)
; vle8.v v13,128(nominal_sp) #avl=16, #vtype=(e8, m1, ta, ma)
; vle8.v v13,128(slot) #avl=16, #vtype=(e8, m1, ta, ma)
; vse8.v v13,512(a0) #avl=16, #vtype=(e8, m1, ta, ma)
; vle8.v v11,0(nominal_sp) #avl=16, #vtype=(e8, m1, ta, ma)
; vle8.v v11,0(slot) #avl=16, #vtype=(e8, m1, ta, ma)
; vse8.v v11,528(a0) #avl=16, #vtype=(e8, m1, ta, ma)
; addi sp,sp,256
; ld ra,8(sp)

172
cranelift/filetests/filetests/isa/riscv64/stack.clif

@ -18,7 +18,7 @@ block0:
; mv fp,sp
; addi sp,sp,-16
; block0:
; load_addr a0,0(nominal_sp)
; load_addr a0,0(slot)
; addi sp,sp,16
; ld ra,8(sp)
; ld fp,0(sp)
@ -61,7 +61,7 @@ block0:
; addi t6,t6,-1712
; add sp,sp,t6
; block0:
; load_addr a0,0(nominal_sp)
; load_addr a0,0(slot)
; lui t6,24
; addi t6,t6,1712
; add sp,sp,t6
@ -108,7 +108,7 @@ block0:
; mv fp,sp
; addi sp,sp,-16
; block0:
; ld a0,0(nominal_sp)
; ld a0,0(slot)
; addi sp,sp,16
; ld ra,8(sp)
; ld fp,0(sp)
@ -151,7 +151,7 @@ block0:
; addi t6,t6,-1712
; add sp,sp,t6
; block0:
; ld a0,0(nominal_sp)
; ld a0,0(slot)
; lui t6,24
; addi t6,t6,1712
; add sp,sp,t6
@ -198,7 +198,7 @@ block0(v0: i64):
; mv fp,sp
; addi sp,sp,-16
; block0:
; sd a0,0(nominal_sp)
; sd a0,0(slot)
; addi sp,sp,16
; ld ra,8(sp)
; ld fp,0(sp)
@ -241,7 +241,7 @@ block0(v0: i64):
; addi t6,t6,-1712
; add sp,sp,t6
; block0:
; sd a0,0(nominal_sp)
; sd a0,0(slot)
; lui t6,24
; addi t6,t6,1712
; add sp,sp,t6
@ -442,9 +442,9 @@ block0(v0: i8):
; sd s10,1280(sp)
; sd s11,1272(sp)
; block0:
; sd a0,1000(nominal_sp)
; sd a0,1000(slot)
; li a2,2
; sd a2,1008(nominal_sp)
; sd a2,1008(slot)
; li a2,4
; li a3,6
; li a4,8
@ -469,125 +469,125 @@ block0(v0: i8):
; li s6,36
; li a0,38
; li a1,30
; sd a1,1256(nominal_sp)
; sd a1,1256(slot)
; li a1,32
; sd a1,1248(nominal_sp)
; sd a1,1248(slot)
; li a1,34
; sd a1,1240(nominal_sp)
; sd a1,1240(slot)
; li a1,36
; sd a1,1232(nominal_sp)
; sd a1,1232(slot)
; li a1,38
; sd a1,1224(nominal_sp)
; sd a1,1224(slot)
; li a1,30
; sd a1,1216(nominal_sp)
; sd a1,1216(slot)
; li a1,32
; sd a1,1208(nominal_sp)
; sd a1,1208(slot)
; li a1,34
; sd a1,1200(nominal_sp)
; sd a1,1200(slot)
; li a1,36
; sd a1,1192(nominal_sp)
; sd a1,1192(slot)
; li a1,38
; sd a1,1184(nominal_sp)
; ld a1,1008(nominal_sp)
; sd a1,1184(slot)
; ld a1,1008(slot)
; addi a1,a1,1
; sd a1,1176(nominal_sp)
; sd a1,1176(slot)
; addi a1,a2,3
; sd a1,1168(nominal_sp)
; sd a1,1168(slot)
; addi a1,a3,5
; sd a1,1160(nominal_sp)
; sd a1,1160(slot)
; addi a1,a4,7
; sd a1,1152(nominal_sp)
; sd a1,1152(slot)
; addi a1,a5,9
; sd a1,1144(nominal_sp)
; sd a1,1144(slot)
; addi a1,s7,11
; sd a1,1136(nominal_sp)
; sd a1,1136(slot)
; addi a1,s8,13
; sd a1,1128(nominal_sp)
; sd a1,1128(slot)
; addi a1,s9,15
; sd a1,1120(nominal_sp)
; sd a1,1120(slot)
; addi a1,s10,17
; sd a1,1112(nominal_sp)
; sd a1,1112(slot)
; addi a1,s11,19
; sd a1,1104(nominal_sp)
; sd a1,1104(slot)
; addi a1,t0,21
; sd a1,1096(nominal_sp)
; sd a1,1096(slot)
; addi a1,t1,23
; sd a1,1088(nominal_sp)
; sd a1,1088(slot)
; addi a1,t2,25
; sd a1,1080(nominal_sp)
; sd a1,1080(slot)
; addi a1,a6,27
; sd a1,1072(nominal_sp)
; sd a1,1072(slot)
; addi a1,a7,29
; sd a1,1064(nominal_sp)
; sd a1,1064(slot)
; addi a1,t3,31
; sd a1,1056(nominal_sp)
; sd a1,1056(slot)
; addi a1,t4,33
; sd a1,1048(nominal_sp)
; sd a1,1048(slot)
; addi a1,s1,35
; sd a1,1040(nominal_sp)
; sd a1,1040(slot)
; addi a1,s2,37
; sd a1,1032(nominal_sp)
; sd a1,1032(slot)
; addi a1,s3,39
; sd a1,1024(nominal_sp)
; sd a1,1024(slot)
; addi a1,s4,31
; sd a1,1016(nominal_sp)
; sd a1,1016(slot)
; addi a1,s5,33
; sd a1,1008(nominal_sp)
; sd a1,1008(slot)
; addi s6,s6,35
; addi a0,a0,37
; ld a1,1256(nominal_sp)
; ld a1,1256(slot)
; addi a1,a1,39
; ld a5,1248(nominal_sp)
; ld a5,1248(slot)
; addi a2,a5,31
; ld a3,1240(nominal_sp)
; ld a3,1240(slot)
; addi a3,a3,33
; ld a5,1232(nominal_sp)
; ld a5,1232(slot)
; addi a4,a5,35
; ld a5,1224(nominal_sp)
; ld a5,1224(slot)
; addi a5,a5,37
; ld s11,1216(nominal_sp)
; ld s11,1216(slot)
; addi s7,s11,39
; ld t2,1208(nominal_sp)
; ld t2,1208(slot)
; addi s8,t2,31
; ld t3,1200(nominal_sp)
; ld t3,1200(slot)
; addi s9,t3,33
; ld s2,1192(nominal_sp)
; ld s2,1192(slot)
; addi s10,s2,35
; ld s5,1184(nominal_sp)
; ld s5,1184(slot)
; addi s11,s5,37
; ld t0,1176(nominal_sp)
; ld t0,1176(slot)
; addi t0,t0,39
; ld t1,1160(nominal_sp)
; ld t2,1168(nominal_sp)
; ld t1,1160(slot)
; ld t2,1168(slot)
; add t1,t2,t1
; ld a7,1152(nominal_sp)
; ld t4,1144(nominal_sp)
; ld a7,1152(slot)
; ld t4,1144(slot)
; add t2,a7,t4
; ld s3,1136(nominal_sp)
; ld s5,1128(nominal_sp)
; ld s3,1136(slot)
; ld s5,1128(slot)
; add a6,s3,s5
; ld a7,1112(nominal_sp)
; ld t3,1120(nominal_sp)
; ld a7,1112(slot)
; ld t3,1120(slot)
; add a7,t3,a7
; ld t3,1096(nominal_sp)
; ld t4,1104(nominal_sp)
; ld t3,1096(slot)
; ld t4,1104(slot)
; add t3,t4,t3
; ld s2,1080(nominal_sp)
; ld t4,1088(nominal_sp)
; ld s2,1080(slot)
; ld t4,1088(slot)
; add t4,t4,s2
; ld s1,1064(nominal_sp)
; ld s5,1072(nominal_sp)
; ld s1,1064(slot)
; ld s5,1072(slot)
; add s1,s5,s1
; ld s2,1048(nominal_sp)
; ld s3,1056(nominal_sp)
; ld s2,1048(slot)
; ld s3,1056(slot)
; add s2,s3,s2
; ld s3,1032(nominal_sp)
; ld s4,1040(nominal_sp)
; ld s3,1032(slot)
; ld s4,1040(slot)
; add s3,s4,s3
; ld s4,1024(nominal_sp)
; ld s5,1016(nominal_sp)
; ld s4,1024(slot)
; ld s5,1016(slot)
; add s4,s4,s5
; ld s5,1008(nominal_sp)
; ld s5,1008(slot)
; add s5,s5,s6
; add a1,a0,a1
; add a2,a2,a3
@ -611,7 +611,7 @@ block0(v0: i8):
; add a3,a5,a0
; add a1,a1,a2
; add a1,a3,a1
; ld a0,1000(nominal_sp)
; ld a0,1000(slot)
; ld s1,1352(sp)
; ld s2,1344(sp)
; ld s3,1336(sp)
@ -850,8 +850,8 @@ block0(v0: i128):
; mv fp,sp
; addi sp,sp,-16
; block0:
; sd a0,0(nominal_sp)
; sd a1,8(nominal_sp)
; sd a0,0(slot)
; sd a1,8(slot)
; addi sp,sp,16
; ld ra,8(sp)
; ld fp,0(sp)
@ -890,8 +890,8 @@ block0(v0: i128):
; mv fp,sp
; addi sp,sp,-32
; block0:
; sd a0,32(nominal_sp)
; sd a1,40(nominal_sp)
; sd a0,32(slot)
; sd a1,40(slot)
; addi sp,sp,32
; ld ra,8(sp)
; ld fp,0(sp)
@ -935,8 +935,8 @@ block0(v0: i128):
; addi t6,t6,-1712
; add sp,sp,t6
; block0:
; sd a0,0(nominal_sp)
; sd a1,8(nominal_sp)
; sd a0,0(slot)
; sd a1,8(slot)
; lui t6,24
; addi t6,t6,1712
; add sp,sp,t6
@ -984,8 +984,8 @@ block0:
; mv fp,sp
; addi sp,sp,-16
; block0:
; ld a0,0(nominal_sp)
; ld a1,8(nominal_sp)
; ld a0,0(slot)
; ld a1,8(slot)
; addi sp,sp,16
; ld ra,8(sp)
; ld fp,0(sp)
@ -1024,8 +1024,8 @@ block0:
; mv fp,sp
; addi sp,sp,-32
; block0:
; ld a0,32(nominal_sp)
; ld a1,40(nominal_sp)
; ld a0,32(slot)
; ld a1,40(slot)
; addi sp,sp,32
; ld ra,8(sp)
; ld fp,0(sp)
@ -1069,8 +1069,8 @@ block0:
; addi t6,t6,-1712
; add sp,sp,t6
; block0:
; ld a0,0(nominal_sp)
; ld a1,8(nominal_sp)
; ld a0,0(slot)
; ld a1,8(slot)
; lui t6,24
; addi t6,t6,1712
; add sp,sp,t6

44
cranelift/filetests/filetests/isa/riscv64/tail-call-conv.clif

@ -88,9 +88,9 @@ block0:
; sd s11,168(sp)
; block0:
; li a0,10
; sd a0,8(nominal_sp)
; sd a0,8(slot)
; li a1,15
; sd a1,0(nominal_sp)
; sd a1,0(slot)
; li a2,20
; li a3,25
; li a4,30
@ -134,8 +134,8 @@ block0:
; sd a0,128(sp)
; sd a1,136(sp)
; load_sym s3,%tail_callee_stack_args+0
; ld a0,8(nominal_sp)
; ld a1,0(nominal_sp)
; ld a0,8(slot)
; ld a1,0(slot)
; callind s3
; ld s1,248(sp)
; ld s2,240(sp)
@ -297,11 +297,11 @@ block0:
; sd s11,40(sp)
; block0:
; li a3,10
; sd a3,24(nominal_sp)
; sd a3,24(slot)
; li a1,15
; sd a1,16(nominal_sp)
; sd a1,16(slot)
; li a4,20
; sd a4,8(nominal_sp)
; sd a4,8(slot)
; li a4,25
; li a5,30
; li a2,35
@ -325,8 +325,8 @@ block0:
; li s2,125
; li a1,130
; li a3,135
; sd a3,0(nominal_sp)
; ld a3,8(nominal_sp)
; sd a3,0(slot)
; ld a3,8(slot)
; sd a3,0(a0)
; sd a4,8(a0)
; sd a5,16(a0)
@ -350,10 +350,10 @@ block0:
; sd s1,160(a0)
; sd s2,168(a0)
; sd a1,176(a0)
; ld a3,0(nominal_sp)
; ld a3,0(slot)
; sd a3,184(a0)
; ld a0,24(nominal_sp)
; ld a1,16(nominal_sp)
; ld a0,24(slot)
; ld a1,16(slot)
; ld s1,120(sp)
; ld s2,112(sp)
; ld s3,104(sp)
@ -584,8 +584,8 @@ block0(v0: i64, v1: i64, v2: i64, v3: i64, v4: i64, v5: i64, v6: i64, v7: i64, v
; sd s10,48(sp)
; sd s11,40(sp)
; block0:
; sd a0,0(nominal_sp)
; sd a1,8(nominal_sp)
; sd a0,0(slot)
; sd a1,8(slot)
; ld s4,-160(incoming_arg)
; ld s6,-152(incoming_arg)
; ld s8,-144(incoming_arg)
@ -604,7 +604,7 @@ block0(v0: i64, v1: i64, v2: i64, v3: i64, v4: i64, v5: i64, v6: i64, v7: i64, v
; ld a0,-40(incoming_arg)
; ld s2,-32(incoming_arg)
; ld t2,-24(incoming_arg)
; sd t2,16(nominal_sp)
; sd t2,16(slot)
; ld t2,-16(incoming_arg)
; sd a2,0(t2)
; sd a3,8(t2)
@ -629,10 +629,10 @@ block0(v0: i64, v1: i64, v2: i64, v3: i64, v4: i64, v5: i64, v6: i64, v7: i64, v
; sd a1,160(t2)
; sd a0,168(t2)
; sd s2,176(t2)
; ld a1,16(nominal_sp)
; ld a1,16(slot)
; sd a1,184(t2)
; ld a0,0(nominal_sp)
; ld a1,8(nominal_sp)
; ld a0,0(slot)
; ld a1,8(slot)
; ld s1,120(sp)
; ld s2,112(sp)
; ld s3,104(sp)
@ -790,9 +790,9 @@ block0:
; sd s11,376(sp)
; block0:
; li a0,10
; sd a0,8(nominal_sp)
; sd a0,8(slot)
; li a1,15
; sd a1,0(nominal_sp)
; sd a1,0(slot)
; li a2,20
; li a3,25
; li a4,30
@ -838,8 +838,8 @@ block0:
; load_addr a0,160(sp)
; sd a0,144(sp)
; load_sym t1,%tail_callee_stack_args_and_rets+0
; ld a0,8(nominal_sp)
; ld a1,0(nominal_sp)
; ld a0,8(slot)
; ld a1,0(slot)
; callind t1
; ld a2,160(sp)
; ld a4,168(sp)

26
cranelift/filetests/filetests/isa/riscv64/zca.clif

@ -361,7 +361,7 @@ block0:
; mv fp,sp
; addi sp,sp,-16
; block0:
; load_addr a0,0(nominal_sp)
; load_addr a0,0(slot)
; addi sp,sp,16
; ld ra,8(sp)
; ld fp,0(sp)
@ -450,12 +450,12 @@ block0:
; mv fp,sp
; addi sp,sp,-2048
; block0:
; load_addr a1,1020(nominal_sp)
; load_addr a1,1020(slot)
; mv a5,a1
; load_addr a1,4(nominal_sp)
; load_addr a2,512(nominal_sp)
; load_addr a3,256(nominal_sp)
; load_addr a4,64(nominal_sp)
; load_addr a1,4(slot)
; load_addr a2,512(slot)
; load_addr a3,256(slot)
; load_addr a4,64(slot)
; sd a2,0(a0)
; sd a3,8(a0)
; sd a4,16(a0)
@ -510,8 +510,8 @@ block0:
; mv fp,sp
; addi sp,sp,-2048
; block0:
; load_addr a0,1024(nominal_sp)
; load_addr a1,0(nominal_sp)
; load_addr a0,1024(slot)
; load_addr a1,0(slot)
; lui t6,1
; addi t6,t6,-2048
; add sp,sp,t6
@ -553,7 +553,7 @@ block0:
; mv fp,sp
; addi sp,sp,-1024
; block0:
; load_addr a0,512(nominal_sp)
; load_addr a0,512(slot)
; addi sp,sp,1024
; ld ra,8(sp)
; ld fp,0(sp)
@ -702,7 +702,7 @@ block0:
; mv fp,sp
; addi sp,sp,-16
; block0:
; lw a0,12(nominal_sp)
; lw a0,12(slot)
; addi sp,sp,16
; ld ra,8(sp)
; ld fp,0(sp)
@ -739,7 +739,7 @@ block0:
; mv fp,sp
; addi sp,sp,-128
; block0:
; ld a0,64(nominal_sp)
; ld a0,64(slot)
; addi sp,sp,128
; ld ra,8(sp)
; ld fp,0(sp)
@ -776,7 +776,7 @@ block0(v0: i32):
; mv fp,sp
; addi sp,sp,-16
; block0:
; sw a0,12(nominal_sp)
; sw a0,12(slot)
; addi sp,sp,16
; ld ra,8(sp)
; ld fp,0(sp)
@ -813,7 +813,7 @@ block0(v0: i64):
; mv fp,sp
; addi sp,sp,-128
; block0:
; sd a0,64(nominal_sp)
; sd a0,64(slot)
; addi sp,sp,128
; ld ra,8(sp)
; ld fp,0(sp)

4
cranelift/filetests/filetests/isa/riscv64/zcd.clif

@ -17,7 +17,7 @@ block0:
; mv fp,sp
; addi sp,sp,-16
; block0:
; fld fa0,8(nominal_sp)
; fld fa0,8(slot)
; addi sp,sp,16
; ld ra,8(sp)
; ld fp,0(sp)
@ -54,7 +54,7 @@ block0(v0: f64):
; mv fp,sp
; addi sp,sp,-128
; block0:
; fsd fa0,64(nominal_sp)
; fsd fa0,64(slot)
; addi sp,sp,128
; ld ra,8(sp)
; ld fp,0(sp)

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