riscv64: Refactor how immediates are stored and used (#7045)

I was curious to poke around the riscv64 backend and I wanted to touch up the handling of `Imm{12,20}` a bit after reading it. This commit is a refactoring of these two types with the following changes: * The payload of these types is now unsigned and guarantees that irrelevant bits are set to zero. For example `Imm12` is stored as `u16` where the upper four bits are guaranteed to be zero. This fixes a discrepancy where `Imm12::maybe_from_i64` was masked for example but `Imm12::from_bits` wasn't. * The `Neg for Imm12` impl was removed because -2048 is a valid `Imm12` but 2048 is not in-range for `Imm12` meaning that it is not an infallible operation. * Accessors are now named `bits` to get the `u32` representation suitable to be encoded into an instruction. Acquiring the underlying value is now done with `as_i{16,32}` depending on the type. The signed accessor does sign-extension as required to produce the semantically equivalent value. * Manual constructors were renamed to `from_{i16,i32}` instead of `from_bits`. This in theory helps convey that they're constructors for logical values rather than literal bit-wise values. Additionally asserts are now placed in these constructors asserting that the provided value is in-range. * The `FALSE` and `TRUE` constants were renamed `ZERO` and `ONE` and `Imm20::ZERO` was added. This commit ended up changing many runtests, but only their CLIF printing rather than their encoding. This change is due to the fact that `Display` now prints the logical value of the immediate rather than the raw bit representation as a base 10 integer. It's not intended that this commit actually changes any behavior, instead it should purely be internal refactorings.
1 year ago · fa999e4d57
45 changed files with 264 additions and 252 deletions
--- a/cranelift/codegen/src/isa/riscv64/inst/args.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/args.rs
@ -1093,7 +1093,7 @@ impl AluOPRRI {
    }

    pub(crate) fn imm12(self, imm12: Imm12) -> u32 {
-        let x = imm12.as_u32();
+        let x = imm12.bits();
        if let Some(func) = self.option_funct6() {
            func << 6 | (x & 0b11_1111)
        } else if let Some(func) = self.option_funct7() {
@ -1770,19 +1770,19 @@ impl FloatSelectOP {
    // move qnan bits into int register.
    pub(crate) fn snan_bits(self, rd: Writable<Reg>, ty: Type) -> SmallInstVec<Inst> {
        let mut insts = SmallInstVec::new();
-        insts.push(Inst::load_imm12(rd, Imm12::from_bits(-1)));
+        insts.push(Inst::load_imm12(rd, Imm12::from_i16(-1)));
        let x = if ty == F32 { 22 } else { 51 };
        insts.push(Inst::AluRRImm12 {
            alu_op: AluOPRRI::Srli,
            rd: rd,
            rs: rd.to_reg(),
-            imm12: Imm12::from_bits(x),
+            imm12: Imm12::from_i16(x),
        });
        insts.push(Inst::AluRRImm12 {
            alu_op: AluOPRRI::Slli,
            rd: rd,
            rs: rd.to_reg(),
-            imm12: Imm12::from_bits(x),
+            imm12: Imm12::from_i16(x),
        });
        insts
    }
@ -1882,7 +1882,7 @@ impl Display for CsrImmOP {

 impl CSR {
    pub(crate) fn bits(self) -> Imm12 {
-        Imm12::from_bits(match self {
+        Imm12::from_i16(match self {
            CSR::Frm => 0x0002,
        })
    }
--- a/cranelift/codegen/src/isa/riscv64/inst/emit.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/emit.rs
@ -120,10 +120,10 @@ impl Inst {
        assert!(ty.is_int() && ty.bits() <= 64);
        match ty {
            I64 => {
-                insts.push(Inst::load_imm12(rd, Imm12::from_bits(-1)));
+                insts.push(Inst::load_imm12(rd, Imm12::from_i16(-1)));
            }
            I32 | I16 => {
-                insts.push(Inst::load_imm12(rd, Imm12::from_bits(-1)));
+                insts.push(Inst::load_imm12(rd, Imm12::from_i16(-1)));
                insts.push(Inst::Extend {
                    rd: rd,
                    rn: rd.to_reg(),
@ -133,7 +133,7 @@ impl Inst {
                });
            }
            I8 => {
-                insts.push(Inst::load_imm12(rd, Imm12::from_bits(255)));
+                insts.push(Inst::load_imm12(rd, Imm12::from_i16(255)));
            }
            _ => unreachable!("ty:{:?}", ty),
        }
@ -145,7 +145,7 @@ impl Inst {
            alu_op: AluOPRRI::Xori,
            rd,
            rs,
-            imm12: Imm12::from_bits(-1),
+            imm12: Imm12::from_i16(-1),
        }
    }

@ -201,7 +201,7 @@ impl Inst {
            alu_op: AluOPRRI::Andi,
            rd: tmp,
            rs: tmp.to_reg(),
-            imm12: Imm12::from_bits(FClassResult::is_zero_bits() as i16),
+            imm12: Imm12::from_i16(FClassResult::is_zero_bits() as i16),
        });
        insts.push(Inst::CondBr {
            taken,
@ -533,7 +533,7 @@ impl Inst {
            Inst::Jal { label } if has_zca => {
                sink.use_label_at_offset(*start_off, label, LabelUse::RVCJump);
                sink.add_uncond_branch(*start_off, *start_off + 2, label);
-                sink.put2(encode_cj_type(CjOp::CJ, Imm12::zero()));
+                sink.put2(encode_cj_type(CjOp::CJ, Imm12::ZERO));
            }

            // c.jr
@ -579,7 +579,7 @@ impl Inst {
                    alu_op: AluOPRRI::Addi,
                    rd: Writable::from_reg(zero_reg()),
                    rs: zero_reg(),
-                    imm12: Imm12::zero(),
+                    imm12: Imm12::ZERO,
                };
                x.emit(&[], sink, emit_info, state)
            }
@ -593,7 +593,7 @@ impl Inst {
                sink.put_data(&data[..]);
            }
            &Inst::Lui { rd, ref imm } => {
-                let x: u32 = 0b0110111 | reg_to_gpr_num(rd.to_reg()) << 7 | (imm.as_u32() << 12);
+                let x: u32 = 0b0110111 | reg_to_gpr_num(rd.to_reg()) << 7 | (imm.bits() << 12);
                sink.put4(x);
            }
            &Inst::LoadInlineConst { rd, ty, imm } => {
@ -737,7 +737,7 @@ impl Inst {
                    (Some(_), None, None) => {
                        let tmp = writable_spilltmp_reg();
                        Inst::LoadAddr { rd: tmp, mem: from }.emit(&[], sink, emit_info, state);
-                        (tmp.to_reg(), Imm12::zero())
+                        (tmp.to_reg(), Imm12::ZERO)
                    }

                    // If the AMode contains a label we can emit an internal relocation that gets
@ -749,7 +749,7 @@ impl Inst {
                        sink.use_label_at_offset(sink.cur_offset(), label, LabelUse::PCRelHi20);
                        Inst::Auipc {
                            rd,
-                            imm: Imm20::from_bits(0),
+                            imm: Imm20::ZERO,
                        }
                        .emit_uncompressed(sink, emit_info, state, start_off);

@ -757,7 +757,7 @@ impl Inst {
                        sink.use_label_at_offset(sink.cur_offset(), label, LabelUse::PCRelLo12I);

                        // Imm12 here is meaningless since it's going to get replaced.
-                        (rd.to_reg(), Imm12::zero())
+                        (rd.to_reg(), Imm12::ZERO)
                    }

                    // These cases are impossible with the current AModes that we have. We either
@ -791,7 +791,7 @@ impl Inst {
                    _ => {
                        let tmp = writable_spilltmp_reg();
                        Inst::LoadAddr { rd: tmp, mem: to }.emit(&[], sink, emit_info, state);
-                        (tmp.to_reg(), Imm12::zero())
+                        (tmp.to_reg(), Imm12::ZERO)
                    }
                };

@ -813,7 +813,7 @@ impl Inst {
                Inst::Jalr {
                    rd: writable_zero_reg(),
                    base: link_reg(),
-                    offset: Imm12::zero(),
+                    offset: Imm12::ZERO,
                }
                .emit(&[], sink, emit_info, state);
            }
@ -834,14 +834,14 @@ impl Inst {
                        alu_op: AluOPRRI::Andi,
                        rd,
                        rs: rn,
-                        imm12: Imm12::from_bits(255),
+                        imm12: Imm12::from_i16(255),
                    });
                } else {
                    insts.push(Inst::AluRRImm12 {
                        alu_op: AluOPRRI::Slli,
                        rd,
                        rs: rn,
-                        imm12: Imm12::from_bits(shift_bits),
+                        imm12: Imm12::from_i16(shift_bits),
                    });
                    insts.push(Inst::AluRRImm12 {
                        alu_op: if signed {
@ -851,7 +851,7 @@ impl Inst {
                        },
                        rd,
                        rs: rd.to_reg(),
-                        imm12: Imm12::from_bits(shift_bits),
+                        imm12: Imm12::from_i16(shift_bits),
                    });
                }
                insts
@ -945,7 +945,7 @@ impl Inst {
                Inst::Jalr {
                    rd: writable_link_reg(),
                    base: info.rn,
-                    offset: Imm12::zero(),
+                    offset: Imm12::ZERO,
                }
                .emit(&[], sink, emit_info, state);

@ -1001,7 +1001,7 @@ impl Inst {
                Inst::Jalr {
                    rd: writable_zero_reg(),
                    base: callee,
-                    offset: Imm12::zero(),
+                    offset: Imm12::ZERO,
                }
                .emit(&[], sink, emit_info, state);

@ -1050,7 +1050,7 @@ impl Inst {
                        alu_op: AluOPRRI::Addi,
                        rd: rd,
                        rs: rm,
-                        imm12: Imm12::zero(),
+                        imm12: Imm12::ZERO,
                    },
                    RegClass::Float => Inst::FpuRRR {
                        alu_op: if ty == F32 {
@ -1165,7 +1165,7 @@ impl Inst {
                // Get the current PC.
                Inst::Auipc {
                    rd: tmp1,
-                    imm: Imm20::from_bits(0),
+                    imm: Imm20::ZERO,
                }
                .emit_uncompressed(sink, emit_info, state, start_off);

@ -1178,7 +1178,7 @@ impl Inst {
                    alu_op: AluOPRRI::Slli,
                    rd: tmp2,
                    rs: ext_index.to_reg(),
-                    imm12: Imm12::from_bits(3),
+                    imm12: Imm12::from_i16(3),
                }
                .emit_uncompressed(sink, emit_info, state, start_off);

@ -1197,7 +1197,7 @@ impl Inst {
                Inst::Jalr {
                    rd: writable_zero_reg(),
                    base: tmp1.to_reg(),
-                    offset: Imm12::from_bits((4 * Inst::UNCOMPRESSED_INSTRUCTION_SIZE) as i16),
+                    offset: Imm12::from_i16((4 * Inst::UNCOMPRESSED_INSTRUCTION_SIZE) as i16),
                }
                .emit_uncompressed(sink, emit_info, state, start_off);

@ -1311,7 +1311,7 @@ impl Inst {
                        sink.use_label_at_offset(sink.cur_offset(), label, LabelUse::PCRelHi20);
                        let inst = Inst::Auipc {
                            rd,
-                            imm: Imm20::from_bits(0),
+                            imm: Imm20::ZERO,
                        };
                        inst.emit_uncompressed(sink, emit_info, state, start_off);

@ -1322,7 +1322,7 @@ impl Inst {
                            alu_op: AluOPRRI::Addi,
                            rd,
                            rs: rd.to_reg(),
-                            imm12: Imm12::zero(),
+                            imm12: Imm12::ZERO,
                        }
                        .emit_uncompressed(sink, emit_info, state, start_off);
                    }
@ -1390,10 +1390,10 @@ impl Inst {
                .for_each(|i| i.emit(&[], sink, emit_info, state));

                sink.bind_label(label_true, &mut state.ctrl_plane);
-                Inst::load_imm12(rd, Imm12::TRUE).emit(&[], sink, emit_info, state);
+                Inst::load_imm12(rd, Imm12::ONE).emit(&[], sink, emit_info, state);
                Inst::gen_jump(label_end).emit(&[], sink, emit_info, state);
                sink.bind_label(label_false, &mut state.ctrl_plane);
-                Inst::load_imm12(rd, Imm12::FALSE).emit(&[], sink, emit_info, state);
+                Inst::load_imm12(rd, Imm12::ZERO).emit(&[], sink, emit_info, state);
                sink.bind_label(label_end, &mut state.ctrl_plane);
            }
            &Inst::AtomicCas {
@ -1890,14 +1890,14 @@ impl Inst {
                        alu_op: AluOPRRI::Srli,
                        rd: rd,
                        rs: rd.to_reg(),
-                        imm12: Imm12::from_bits(31),
+                        imm12: Imm12::from_i16(31),
                    }
                    .emit(&[], sink, emit_info, state);
                    Inst::AluRRImm12 {
                        alu_op: AluOPRRI::Slli,
                        rd: rd,
                        rs: rd.to_reg(),
-                        imm12: Imm12::from_bits(if 16 == out_type.bits() {
+                        imm12: Imm12::from_i16(if 16 == out_type.bits() {
                            15
                        } else {
                            // I8
@ -1920,7 +1920,7 @@ impl Inst {
                // here is nan , move 0 into rd register
                sink.bind_label(label_nan, &mut state.ctrl_plane);
                if is_sat {
-                    Inst::load_imm12(rd, Imm12::from_bits(0)).emit(&[], sink, emit_info, state);
+                    Inst::load_imm12(rd, Imm12::ZERO).emit(&[], sink, emit_info, state);
                } else {
                    // here is ud2.
                    Inst::Udf {
@ -2303,19 +2303,19 @@ impl Inst {
                // load 0 to sum , init.
                Inst::gen_move(sum, zero_reg(), I64).emit(&[], sink, emit_info, state);
                // load
-                Inst::load_imm12(step, Imm12::from_bits(ty.bits() as i16)).emit(
+                Inst::load_imm12(step, Imm12::from_i16(ty.bits() as i16)).emit(
                    &[],
                    sink,
                    emit_info,
                    state,
                );
                //
-                Inst::load_imm12(tmp, Imm12::from_bits(1)).emit(&[], sink, emit_info, state);
+                Inst::load_imm12(tmp, Imm12::ONE).emit(&[], sink, emit_info, state);
                Inst::AluRRImm12 {
                    alu_op: AluOPRRI::Slli,
                    rd: tmp,
                    rs: tmp.to_reg(),
-                    imm12: Imm12::from_bits((ty.bits() - 1) as i16),
+                    imm12: Imm12::from_i16((ty.bits() - 1) as i16),
                }
                .emit(&[], sink, emit_info, state);
                let label_done = sink.get_label();
@ -2355,7 +2355,7 @@ impl Inst {
                        alu_op: AluOPRRI::Addi,
                        rd: sum,
                        rs: sum.to_reg(),
-                        imm12: Imm12::from_bits(1),
+                        imm12: Imm12::ONE,
                    }
                    .emit(&[], sink, emit_info, state);
                    sink.bind_label(label_over, &mut state.ctrl_plane);
@ -2366,14 +2366,14 @@ impl Inst {
                        alu_op: AluOPRRI::Addi,
                        rd: step,
                        rs: step.to_reg(),
-                        imm12: Imm12::from_bits(-1),
+                        imm12: Imm12::from_i16(-1),
                    }
                    .emit(&[], sink, emit_info, state);
                    Inst::AluRRImm12 {
                        alu_op: AluOPRRI::Srli,
                        rd: tmp,
                        rs: tmp.to_reg(),
-                        imm12: Imm12::from_bits(1),
+                        imm12: Imm12::ONE,
                    }
                    .emit(&[], sink, emit_info, state);
                    Inst::gen_jump(label_loop).emit(&[], sink, emit_info, state);
@ -2385,7 +2385,7 @@ impl Inst {
                Inst::gen_move(rd, zero_reg(), I64).emit(&[], sink, emit_info, state);
                Inst::gen_move(tmp, rs, I64).emit(&[], sink, emit_info, state);
                // load 56 to step.
-                Inst::load_imm12(step, Imm12::from_bits(56)).emit(&[], sink, emit_info, state);
+                Inst::load_imm12(step, Imm12::from_i16(56)).emit(&[], sink, emit_info, state);
                let label_done = sink.get_label();
                let label_loop = sink.get_label();
                sink.bind_label(label_loop, &mut state.ctrl_plane);
@ -2403,7 +2403,7 @@ impl Inst {
                    alu_op: AluOPRRI::Andi,
                    rd: writable_spilltmp_reg(),
                    rs: tmp.to_reg(),
-                    imm12: Imm12::from_bits(255),
+                    imm12: Imm12::from_i16(255),
                }
                .emit(&[], sink, emit_info, state);
                Inst::AluRRR {
@ -2428,7 +2428,7 @@ impl Inst {
                        alu_op: AluOPRRI::Addi,
                        rd: step,
                        rs: step.to_reg(),
-                        imm12: Imm12::from_bits(-8),
+                        imm12: Imm12::from_i16(-8),
                    }
                    .emit(&[], sink, emit_info, state);
                    //reset tmp.
@ -2436,7 +2436,7 @@ impl Inst {
                        alu_op: AluOPRRI::Srli,
                        rd: tmp,
                        rs: tmp.to_reg(),
-                        imm12: Imm12::from_bits(8),
+                        imm12: Imm12::from_i16(8),
                    }
                    .emit(&[], sink, emit_info, state);
                    // loop.
@ -2456,20 +2456,20 @@ impl Inst {
                // load 0 to sum , init.
                Inst::gen_move(sum, zero_reg(), I64).emit(&[], sink, emit_info, state);
                // load
-                Inst::load_imm12(step, Imm12::from_bits(ty.bits() as i16)).emit(
+                Inst::load_imm12(step, Imm12::from_i16(ty.bits() as i16)).emit(
                    &[],
                    sink,
                    emit_info,
                    state,
                );
                //
-                Inst::load_imm12(tmp, Imm12::from_bits(1)).emit(&[], sink, emit_info, state);
+                Inst::load_imm12(tmp, Imm12::ONE).emit(&[], sink, emit_info, state);
                if leading {
                    Inst::AluRRImm12 {
                        alu_op: AluOPRRI::Slli,
                        rd: tmp,
                        rs: tmp.to_reg(),
-                        imm12: Imm12::from_bits((ty.bits() - 1) as i16),
+                        imm12: Imm12::from_i16((ty.bits() - 1) as i16),
                    }
                    .emit(&[], sink, emit_info, state);
                }
@ -2509,7 +2509,7 @@ impl Inst {
                        alu_op: AluOPRRI::Addi,
                        rd: sum,
                        rs: sum.to_reg(),
-                        imm12: Imm12::from_bits(1),
+                        imm12: Imm12::ONE,
                    }
                    .emit(&[], sink, emit_info, state);
                }
@ -2519,7 +2519,7 @@ impl Inst {
                        alu_op: AluOPRRI::Addi,
                        rd: step,
                        rs: step.to_reg(),
-                        imm12: Imm12::from_bits(-1),
+                        imm12: Imm12::from_i16(-1),
                    }
                    .emit(&[], sink, emit_info, state);
                    Inst::AluRRImm12 {
@ -2530,7 +2530,7 @@ impl Inst {
                        },
                        rd: tmp,
                        rs: tmp.to_reg(),
-                        imm12: Imm12::from_bits(1),
+                        imm12: Imm12::ONE,
                    }
                    .emit(&[], sink, emit_info, state);
                    Inst::gen_jump(label_loop).emit(&[], sink, emit_info, state);
@ -2546,27 +2546,27 @@ impl Inst {
                rd,
            } => {
                Inst::gen_move(rd, zero_reg(), I64).emit(&[], sink, emit_info, state);
-                Inst::load_imm12(step, Imm12::from_bits(ty.bits() as i16)).emit(
+                Inst::load_imm12(step, Imm12::from_i16(ty.bits() as i16)).emit(
                    &[],
                    sink,
                    emit_info,
                    state,
                );
                //
-                Inst::load_imm12(tmp, Imm12::from_bits(1)).emit(&[], sink, emit_info, state);
+                Inst::load_imm12(tmp, Imm12::ONE).emit(&[], sink, emit_info, state);
                Inst::AluRRImm12 {
                    alu_op: AluOPRRI::Slli,
                    rd: tmp,
                    rs: tmp.to_reg(),
-                    imm12: Imm12::from_bits((ty.bits() - 1) as i16),
+                    imm12: Imm12::from_i16((ty.bits() - 1) as i16),
                }
                .emit(&[], sink, emit_info, state);
-                Inst::load_imm12(tmp2, Imm12::from_bits(1)).emit(&[], sink, emit_info, state);
+                Inst::load_imm12(tmp2, Imm12::ONE).emit(&[], sink, emit_info, state);
                Inst::AluRRImm12 {
                    alu_op: AluOPRRI::Slli,
                    rd: tmp2,
                    rs: tmp2.to_reg(),
-                    imm12: Imm12::from_bits((ty.bits() - 8) as i16),
+                    imm12: Imm12::from_i16((ty.bits() - 8) as i16),
                }
                .emit(&[], sink, emit_info, state);

@ -2618,14 +2618,14 @@ impl Inst {
                        alu_op: AluOPRRI::Addi,
                        rd: step,
                        rs: step.to_reg(),
-                        imm12: Imm12::from_bits(-1),
+                        imm12: Imm12::from_i16(-1),
                    }
                    .emit(&[], sink, emit_info, state);
                    Inst::AluRRImm12 {
                        alu_op: AluOPRRI::Srli,
                        rd: tmp,
                        rs: tmp.to_reg(),
-                        imm12: Imm12::from_bits(1),
+                        imm12: Imm12::ONE,
                    }
                    .emit(&[], sink, emit_info, state);
                    {
@ -2634,7 +2634,7 @@ impl Inst {
                        // if (step %=8 != 0) then tmp2 = tmp2 << 1
                        let label_over = sink.get_label();
                        let label_sll_1 = sink.get_label();
-                        Inst::load_imm12(writable_spilltmp_reg2(), Imm12::from_bits(8)).emit(
+                        Inst::load_imm12(writable_spilltmp_reg2(), Imm12::from_i16(8)).emit(
                            &[],
                            sink,
                            emit_info,
@ -2661,7 +2661,7 @@ impl Inst {
                            alu_op: AluOPRRI::Srli,
                            rd: tmp2,
                            rs: tmp2.to_reg(),
-                            imm12: Imm12::from_bits(15),
+                            imm12: Imm12::from_i16(15),
                        }
                        .emit(&[], sink, emit_info, state);
                        Inst::gen_jump(label_over).emit(&[], sink, emit_info, state);
@ -2670,7 +2670,7 @@ impl Inst {
                            alu_op: AluOPRRI::Slli,
                            rd: tmp2,
                            rs: tmp2.to_reg(),
-                            imm12: Imm12::from_bits(1),
+                            imm12: Imm12::ONE,
                        }
                        .emit(&[], sink, emit_info, state);
                        sink.bind_label(label_over, &mut state.ctrl_plane);
--- a/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs
@ -69,7 +69,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Brev8,
            rd: writable_a1(),
            rs: a0(),
-            imm12: Imm12::zero(),
+            imm12: Imm12::ZERO,
        },
        "brev8 a1,a0",
        0x68755593,
@ -79,7 +79,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Rev8,
            rd: writable_a1(),
            rs: a0(),
-            imm12: Imm12::zero(),
+            imm12: Imm12::ZERO,
        },
        "rev8 a1,a0",
        0x6b855593,
@ -91,7 +91,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Bclri,
            rd: writable_a1(),
            rs: a0(),
-            imm12: Imm12::from_bits(5),
+            imm12: Imm12::from_i16(5),
        },
        "bclri a1,a0,5",
        0x48551593,
@ -101,7 +101,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Bexti,
            rd: writable_a1(),
            rs: a0(),
-            imm12: Imm12::from_bits(5),
+            imm12: Imm12::from_i16(5),
        },
        "bexti a1,a0,5",
        0x48555593,
@ -112,7 +112,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Binvi,
            rd: writable_a1(),
            rs: a0(),
-            imm12: Imm12::from_bits(5),
+            imm12: Imm12::from_i16(5),
        },
        "binvi a1,a0,5",
        0x68551593,
@ -123,7 +123,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Bseti,
            rd: writable_a1(),
            rs: a0(),
-            imm12: Imm12::from_bits(5),
+            imm12: Imm12::from_i16(5),
        },
        "bseti a1,a0,5",
        0x28551593,
@ -134,7 +134,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Rori,
            rd: writable_a1(),
            rs: a0(),
-            imm12: Imm12::from_bits(5),
+            imm12: Imm12::from_i16(5),
        },
        "rori a1,a0,5",
        0x60555593,
@ -144,7 +144,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Roriw,
            rd: writable_a1(),
            rs: a0(),
-            imm12: Imm12::from_bits(5),
+            imm12: Imm12::from_i16(5),
        },
        "roriw a1,a0,5",
        0x6055559b,
@ -155,7 +155,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::SlliUw,
            rd: writable_a1(),
            rs: a0(),
-            imm12: Imm12::from_bits(5),
+            imm12: Imm12::from_i16(5),
        },
        "slli.uw a1,a0,5",
        0x855159b,
@ -166,7 +166,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Clz,
            rd: writable_a1(),
            rs: a0(),
-            imm12: Imm12::zero(),
+            imm12: Imm12::ZERO,
        },
        "clz a1,a0",
        0x60051593,
@ -177,7 +177,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Clzw,
            rd: writable_a1(),
            rs: a0(),
-            imm12: Imm12::zero(),
+            imm12: Imm12::ZERO,
        },
        "clzw a1,a0",
        0x6005159b,
@ -188,7 +188,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Cpop,
            rd: writable_a1(),
            rs: a0(),
-            imm12: Imm12::zero(),
+            imm12: Imm12::ZERO,
        },
        "cpop a1,a0",
        0x60251593,
@ -199,7 +199,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Cpopw,
            rd: writable_a1(),
            rs: a0(),
-            imm12: Imm12::zero(),
+            imm12: Imm12::ZERO,
        },
        "cpopw a1,a0",
        0x6025159b,
@ -210,7 +210,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Ctz,
            rd: writable_a1(),
            rs: a0(),
-            imm12: Imm12::zero(),
+            imm12: Imm12::ZERO,
        },
        "ctz a1,a0",
        0x60151593,
@ -221,7 +221,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Ctzw,
            rd: writable_a1(),
            rs: a0(),
-            imm12: Imm12::zero(),
+            imm12: Imm12::ZERO,
        },
        "ctzw a1,a0",
        0x6015159b,
@ -232,7 +232,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Sextb,
            rd: writable_a1(),
            rs: a0(),
-            imm12: Imm12::zero(),
+            imm12: Imm12::ZERO,
        },
        "sext.b a1,a0",
        0x60451593,
@ -242,7 +242,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Sexth,
            rd: writable_a1(),
            rs: a0(),
-            imm12: Imm12::zero(),
+            imm12: Imm12::ZERO,
        },
        "sext.h a1,a0",
        0x60551593,
@ -252,7 +252,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Zexth,
            rd: writable_a1(),
            rs: a0(),
-            imm12: Imm12::zero(),
+            imm12: Imm12::ZERO,
        },
        "zext.h a1,a0",
        0x80545bb,
@ -262,7 +262,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Orcb,
            rd: writable_a1(),
            rs: a0(),
-            imm12: Imm12::zero(),
+            imm12: Imm12::ZERO,
        },
        "orc.b a1,a0",
        0x28755593,
@ -600,7 +600,7 @@ fn test_riscv64_binemit() {
    insns.push(TestUnit::new(
        Inst::Lui {
            rd: writable_zero_reg(),
-            imm: Imm20::from_bits(120),
+            imm: Imm20::from_i32(120),
        },
        "lui zero,120",
        0x78037,
@ -608,7 +608,7 @@ fn test_riscv64_binemit() {
    insns.push(TestUnit::new(
        Inst::Auipc {
            rd: writable_zero_reg(),
-            imm: Imm20::from_bits(120),
+            imm: Imm20::from_i32(120),
        },
        "auipc zero,120",
        0x78017,
@ -618,7 +618,7 @@ fn test_riscv64_binemit() {
        Inst::Jalr {
            rd: writable_a0(),
            base: a0(),
-            offset: Imm12::from_bits(100),
+            offset: Imm12::from_i16(100),
        },
        "jalr a0,100(a0)",
        0x6450567,
@ -752,7 +752,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Addi,
            rd: writable_a0(),
            rs: a0(),
-            imm12: Imm12::from_bits(100),
+            imm12: Imm12::from_i16(100),
        },
        "addi a0,a0,100",
        0x6450513,
@ -762,7 +762,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Slti,
            rd: writable_a0(),
            rs: a0(),
-            imm12: Imm12::from_bits(100),
+            imm12: Imm12::from_i16(100),
        },
        "slti a0,a0,100",
        0x6452513,
@ -772,7 +772,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::SltiU,
            rd: writable_a0(),
            rs: a0(),
-            imm12: Imm12::from_bits(100),
+            imm12: Imm12::from_i16(100),
        },
        "sltiu a0,a0,100",
        0x6453513,
@ -782,7 +782,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Xori,
            rd: writable_a0(),
            rs: a0(),
-            imm12: Imm12::from_bits(100),
+            imm12: Imm12::from_i16(100),
        },
        "xori a0,a0,100",
        0x6454513,
@ -792,7 +792,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Andi,
            rd: writable_a0(),
            rs: a0(),
-            imm12: Imm12::from_bits(100),
+            imm12: Imm12::from_i16(100),
        },
        "andi a0,a0,100",
        0x6457513,
@ -802,7 +802,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Slli,
            rd: writable_a0(),
            rs: a0(),
-            imm12: Imm12::from_bits(5),
+            imm12: Imm12::from_i16(5),
        },
        "slli a0,a0,5",
        0x551513,
@ -812,7 +812,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Srli,
            rd: writable_a0(),
            rs: a0(),
-            imm12: Imm12::from_bits(5),
+            imm12: Imm12::from_i16(5),
        },
        "srli a0,a0,5",
        0x555513,
@ -822,7 +822,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Srai,
            rd: writable_a0(),
            rs: a0(),
-            imm12: Imm12::from_bits(5),
+            imm12: Imm12::from_i16(5),
        },
        "srai a0,a0,5",
        0x40555513,
@ -832,7 +832,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Addiw,
            rd: writable_a0(),
            rs: a0(),
-            imm12: Imm12::from_bits(120),
+            imm12: Imm12::from_i16(120),
        },
        "addiw a0,a0,120",
        0x785051b,
@ -842,7 +842,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Slliw,
            rd: writable_a0(),
            rs: a0(),
-            imm12: Imm12::from_bits(5),
+            imm12: Imm12::from_i16(5),
        },
        "slliw a0,a0,5",
        0x55151b,
@ -852,7 +852,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::SrliW,
            rd: writable_a0(),
            rs: a0(),
-            imm12: Imm12::from_bits(5),
+            imm12: Imm12::from_i16(5),
        },
        "srliw a0,a0,5",
        0x55551b,
@ -862,7 +862,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Sraiw,
            rd: writable_a0(),
            rs: a0(),
-            imm12: Imm12::from_bits(5),
+            imm12: Imm12::from_i16(5),
        },
        "sraiw a0,a0,5",
        0x4055551b,
@ -873,7 +873,7 @@ fn test_riscv64_binemit() {
            alu_op: AluOPRRI::Sraiw,
            rd: writable_a0(),
            rs: a0(),
-            imm12: Imm12::from_bits(5),
+            imm12: Imm12::from_i16(5),
        },
        "sraiw a0,a0,5",
        0x4055551b,
--- a/cranelift/codegen/src/isa/riscv64/inst/encode.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/encode.rs
@ -73,7 +73,7 @@ pub fn encode_i_type(opcode: u32, rd: WritableReg, width: u32, rs1: Reg, offset:
        reg_to_gpr_num(rd.to_reg()),
        width,
        reg_to_gpr_num(rs1),
-        offset.as_u32(),
+        offset.bits(),
    )
 }

@ -85,11 +85,11 @@ pub fn encode_i_type(opcode: u32, rd: WritableReg, width: u32, rs1: Reg, offset:
 pub fn encode_s_type(opcode: u32, width: u32, base: Reg, src: Reg, offset: Imm12) -> u32 {
    let mut bits = 0;
    bits |= unsigned_field_width(opcode, 7);
-    bits |= (offset.as_u32() & 0b11111) << 7;
+    bits |= (offset.bits() & 0b11111) << 7;
    bits |= unsigned_field_width(width, 3) << 12;
    bits |= reg_to_gpr_num(base) << 15;
    bits |= reg_to_gpr_num(src) << 20;
-    bits |= unsigned_field_width(offset.as_u32() >> 5, 7) << 25;
+    bits |= unsigned_field_width(offset.bits() >> 5, 7) << 25;
    bits
 }

@ -321,7 +321,7 @@ pub fn encode_csr_imm(op: CsrImmOP, rd: WritableReg, csr: CSR, imm: UImm5) -> u3
        reg_to_gpr_num(rd.to_reg()),
        op.funct3(),
        imm.bits(),
-        csr.bits().as_u32(),
+        csr.bits().bits(),
    )
 }

@ -367,7 +367,7 @@ pub fn encode_ca_type(op: CaOp, rd: WritableReg, rs2: Reg) -> u16 {
 // 0--1-2-----12-13--------15
 // |op |  imm   |  funct3  |
 pub fn encode_cj_type(op: CjOp, imm: Imm12) -> u16 {
-    let imm = imm.as_u32();
+    let imm = imm.bits();
    debug_assert!(imm & 1 == 0);

    // The offset bits are in rather weird positions.
--- a/cranelift/codegen/src/isa/riscv64/inst/imms.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/imms.rs
@ -7,12 +7,15 @@ use std::fmt::{Debug, Display, Formatter, Result};

 #[derive(Copy, Clone, Debug, Default)]
 pub struct Imm12 {
-    pub bits: i16,
+    /// 16-bit container where the low 12 bits are the data payload.
+    ///
+    /// Acquiring the underlying value requires sign-extending the 12th bit.
+    bits: u16,
 }

 impl Imm12 {
-    pub(crate) const FALSE: Self = Self { bits: 0 };
-    pub(crate) const TRUE: Self = Self { bits: 1 };
+    pub(crate) const ZERO: Self = Self { bits: 0 };
+    pub(crate) const ONE: Self = Self { bits: 1 };

    pub fn maybe_from_u64(val: u64) -> Option<Imm12> {
        Self::maybe_from_i64(val as i64)
@ -20,74 +23,79 @@ impl Imm12 {

    pub fn maybe_from_i64(val: i64) -> Option<Imm12> {
        if val >= -2048 && val <= 2047 {
-            Some(Imm12 { bits: val as i16 })
+            Some(Imm12 {
+                bits: val as u16 & 0xfff,
+            })
        } else {
            None
        }
    }

    #[inline]
-    pub fn from_bits(bits: i16) -> Self {
-        Self { bits: bits & 0xfff }
-    }
-    /// Create a zero immediate of this format.
-    #[inline]
-    pub fn zero() -> Self {
-        Imm12 { bits: 0 }
+    pub fn from_i16(bits: i16) -> Self {
+        assert!(bits >= -2048 && bits <= 2047);
+        Self {
+            bits: (bits & 0xfff) as u16,
+        }
    }
+
    #[inline]
    pub fn as_i16(self) -> i16 {
-        self.bits
+        (self.bits << 4) as i16 >> 4
    }
+
    #[inline]
-    pub fn as_u32(&self) -> u32 {
-        (self.bits as u32) & 0xfff
+    pub fn bits(&self) -> u32 {
+        self.bits.into()
    }
 }

 impl Into<i64> for Imm12 {
    fn into(self) -> i64 {
-        self.bits as i64
+        self.as_i16().into()
    }
 }

 impl Display for Imm12 {
    fn fmt(&self, f: &mut Formatter<'_>) -> Result {
-        write!(f, "{:+}", self.bits)
-    }
-}
-
-impl std::ops::Neg for Imm12 {
-    type Output = Self;
-    fn neg(self) -> Self::Output {
-        Self { bits: -self.bits }
+        write!(f, "{:+}", self.as_i16())
    }
 }

 // singed
 #[derive(Clone, Copy, Default)]
 pub struct Imm20 {
-    /// The immediate bits.
-    pub bits: i32,
+    /// 32-bit container where the low 20 bits are the data payload.
+    ///
+    /// Acquiring the underlying value requires sign-extending the 20th bit.
+    bits: u32,
 }

 impl Imm20 {
+    pub(crate) const ZERO: Self = Self { bits: 0 };
+
    #[inline]
-    pub fn from_bits(bits: i32) -> Self {
+    pub fn from_i32(bits: i32) -> Self {
+        assert!(bits >= -(0x7_ffff + 1) && bits <= 0x7_ffff);
        Self {
-            bits: bits & 0xf_ffff,
+            bits: (bits as u32) & 0xf_ffff,
        }
    }

    #[inline]
-    pub fn as_u32(&self) -> u32 {
-        (self.bits as u32) & 0xf_ffff
+    pub fn as_i32(&self) -> i32 {
+        ((self.bits << 12) as i32) >> 12
+    }
+
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
    }
 }

 impl Debug for Imm20 {
    fn fmt(&self, f: &mut Formatter<'_>) -> Result {
-        write!(f, "{}", self.bits)
+        write!(f, "{}", self.as_i32())
    }
 }

@ -179,7 +187,7 @@ impl Inst {
    pub(crate) fn generate_imm(value: u64) -> Option<(Imm20, Imm12)> {
        if let Some(imm12) = Imm12::maybe_from_u64(value) {
            // can be load using single imm12.
-            return Some((Imm20::from_bits(0), imm12));
+            return Some((Imm20::ZERO, imm12));
        }
        let value = value as i64;
        if !(value >= Self::imm_min() && value <= Self::imm_max()) {
@ -209,12 +217,10 @@ impl Inst {
            }
            (imm20, imm12)
        };
-        assert!(imm20 >= -(0x7_ffff + 1) && imm20 <= 0x7_ffff);
        assert!(imm20 != 0 || imm12 != 0);
-        Some((
-            Imm20::from_bits(imm20 as i32),
-            Imm12::from_bits(imm12 as i16),
-        ))
+        let imm20 = i32::try_from(imm20).unwrap();
+        let imm12 = i16::try_from(imm12).unwrap();
+        Some((Imm20::from_i32(imm20), Imm12::from_i16(imm12)))
    }
 }

@ -223,8 +229,8 @@ mod test {
    use super::*;
    #[test]
    fn test_imm12() {
-        let x = Imm12::zero();
-        assert_eq!(0, x.as_u32());
+        let x = Imm12::ZERO;
+        assert_eq!(0, x.bits());
        Imm12::maybe_from_u64(0xffff_ffff_ffff_ffff).unwrap();
    }

--- a/cranelift/codegen/src/isa/riscv64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/mod.rs
@ -136,7 +136,7 @@ impl Display for CondBrTarget {
 }

 pub(crate) fn enc_auipc(rd: Writable<Reg>, imm: Imm20) -> u32 {
-    let x = 0b0010111 | reg_to_gpr_num(rd.to_reg()) << 7 | imm.as_u32() << 12;
+    let x = 0b0010111 | reg_to_gpr_num(rd.to_reg()) << 7 | imm.bits() << 12;
    x
 }

@ -145,7 +145,7 @@ pub(crate) fn enc_jalr(rd: Writable<Reg>, base: Reg, offset: Imm12) -> u32 {
        | reg_to_gpr_num(rd.to_reg()) << 7
        | 0b000 << 12
        | reg_to_gpr_num(base) << 15
-        | offset.as_u32() << 20;
+        | offset.bits() << 20;
    x
 }

@ -182,7 +182,7 @@ impl Inst {
        Inst::generate_imm(value).map(|(imm20, imm12)| {
            let mut insts = SmallVec::new();

-            let imm20_is_zero = imm20.as_u32() == 0;
+            let imm20_is_zero = imm20.as_i32() == 0;
            let imm12_is_zero = imm12.as_i16() == 0;

            let rs = if !imm20_is_zero {
@ -1357,16 +1357,21 @@ impl Inst {
                    "{} {},{}",
                    "auipc",
                    format_reg(rd.to_reg(), allocs),
-                    imm.bits
+                    imm.as_i32(),
                )
            }
            &Inst::Jalr { rd, base, offset } => {
                let base = format_reg(base, allocs);
                let rd = format_reg(rd.to_reg(), allocs);
-                format!("{} {},{}({})", "jalr", rd, offset.bits, base)
+                format!("{} {},{}({})", "jalr", rd, offset.as_i16(), base)
            }
            &Inst::Lui { rd, ref imm } => {
-                format!("{} {},{}", "lui", format_reg(rd.to_reg(), allocs), imm.bits)
+                format!(
+                    "{} {},{}",
+                    "lui",
+                    format_reg(rd.to_reg(), allocs),
+                    imm.as_i32()
+                )
            }
            &Inst::LoadInlineConst { rd, imm, .. } => {
                let rd = format_reg(rd.to_reg(), allocs);
@ -2024,14 +2029,14 @@ impl MachInstLabelUse for LabelUse {
    ) -> (CodeOffset, LabelUse) {
        let base = writable_spilltmp_reg();
        {
-            let x = enc_auipc(base, Imm20::from_bits(0)).to_le_bytes();
+            let x = enc_auipc(base, Imm20::ZERO).to_le_bytes();
            buffer[0] = x[0];
            buffer[1] = x[1];
            buffer[2] = x[2];
            buffer[3] = x[3];
        }
        {
-            let x = enc_jalr(writable_zero_reg(), base.to_reg(), Imm12::from_bits(0)).to_le_bytes();
+            let x = enc_jalr(writable_zero_reg(), base.to_reg(), Imm12::ZERO).to_le_bytes();
            buffer[4] = x[0];
            buffer[5] = x[1];
            buffer[6] = x[2];
@ -2135,7 +2140,7 @@ impl LabelUse {

                buffer[0..2].clone_from_slice(&u16::to_le_bytes(encode_cj_type(
                    CjOp::CJ,
-                    Imm12::from_bits(i16::try_from(offset).unwrap()),
+                    Imm12::from_i16(i16::try_from(offset).unwrap()),
                )));
            }
        }
--- a/cranelift/codegen/src/isa/riscv64/lower/isle.rs
+++ b/cranelift/codegen/src/isa/riscv64/lower/isle.rs
@ -263,7 +263,7 @@ impl generated_code::Context for RV64IsleContext<'_, '_, MInst, Riscv64Backend>
    }

    fn imm12_and(&mut self, imm: Imm12, x: u64) -> Imm12 {
-        Imm12::from_bits(imm.as_i16() & (x as i16))
+        Imm12::from_i16(imm.as_i16() & (x as i16))
    }

    fn alloc_vec_writable(&mut self, ty: Type) -> VecWritableReg {
@ -298,7 +298,7 @@ impl generated_code::Context for RV64IsleContext<'_, '_, MInst, Riscv64Backend>
    }
    #[inline]
    fn imm12_is_zero(&mut self, imm: Imm12) -> Option<()> {
-        if imm.as_u32() == 0 {
+        if imm.as_i16() == 0 {
            Some(())
        } else {
            None
@ -307,7 +307,7 @@ impl generated_code::Context for RV64IsleContext<'_, '_, MInst, Riscv64Backend>

    #[inline]
    fn imm20_is_zero(&mut self, imm: Imm20) -> Option<()> {
-        if imm.as_u32() == 0 {
+        if imm.as_i32() == 0 {
            Some(())
        } else {
            None
@ -396,19 +396,20 @@ impl generated_code::Context for RV64IsleContext<'_, '_, MInst, Riscv64Backend>
    //
    fn gen_shamt(&mut self, ty: Type, shamt: XReg) -> ValueRegs {
        let ty_bits = if ty.bits() > 64 { 64 } else { ty.bits() };
+        let ty_bits = i16::try_from(ty_bits).unwrap();
        let shamt = {
            let tmp = self.temp_writable_reg(I64);
            self.emit(&MInst::AluRRImm12 {
                alu_op: AluOPRRI::Andi,
                rd: tmp,
                rs: shamt.to_reg(),
-                imm12: Imm12::from_bits((ty_bits - 1) as i16),
+                imm12: Imm12::from_i16(ty_bits - 1),
            });
            tmp.to_reg()
        };
        let len_sub_shamt = {
            let tmp = self.temp_writable_reg(I64);
-            self.emit(&MInst::load_imm12(tmp, Imm12::from_bits(ty_bits as i16)));
+            self.emit(&MInst::load_imm12(tmp, Imm12::from_i16(ty_bits)));
            let len_sub_shamt = self.temp_writable_reg(I64);
            self.emit(&MInst::AluRRR {
                alu_op: AluOPRRR::Sub,
@ -540,7 +541,7 @@ impl generated_code::Context for RV64IsleContext<'_, '_, MInst, Riscv64Backend>
            alu_op: AluOPRRI::Slli,
            rd: tmp,
            rs: v.to_reg(),
-            imm12: Imm12::from_bits((64 - ty.bits()) as i16),
+            imm12: Imm12::from_i16((64 - ty.bits()) as i16),
        });

        self.xreg_new(tmp.to_reg())
--- a/cranelift/filetests/filetests/isa/riscv64/amodes.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/amodes.clif
@ -232,7 +232,7 @@ block0(v0: i64):
 ; VCode:
 ; block0:
 ;   lui a4,244141
-;   addi a1,a4,2560
+;   addi a1,a4,-1536
 ;   add a5,a0,a1
 ;   lw a0,0(a5)
 ;   ret
@ -299,8 +299,8 @@ block0(v0: i64, v1: i64, v2: i64):

 ; VCode:
 ; block0:
-;   lui a1,1048575
-;   addi a3,a1,4094
+;   lui a1,-1
+;   addi a3,a1,-2
 ;   slli a1,a3,32
 ;   srli a3,a1,32
 ;   lh a0,0(a3)
@ -351,8 +351,8 @@ block0(v0: i64, v1: i64, v2: i64):

 ; VCode:
 ; block0:
-;   lui a0,1048575
-;   addi a2,a0,4094
+;   lui a0,-1
+;   addi a2,a0,-2
 ;   sext.w a1,a2
 ;   lh a0,0(a1)
 ;   ret
--- a/cranelift/filetests/filetests/isa/riscv64/constants.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/constants.clif
@ -59,7 +59,7 @@ block0:
 ; VCode:
 ; block0:
 ;   lui a0,16
-;   addi a0,a0,4095
+;   addi a0,a0,-1
 ;   ret
 ;
 ; Disassembled:
@ -152,7 +152,7 @@ block0:

 ; VCode:
 ; block0:
-;   lui a0,1048560
+;   lui a0,-16
 ;   ret
 ;
 ; Disassembled:
@ -491,7 +491,7 @@ block0:

 ; VCode:
 ; block0:
-;   lui a0,792576
+;   lui a0,-256000
 ;   fmv.w.x fa0,a0
 ;   ret
 ;
@ -510,7 +510,7 @@ block0:
 ; VCode:
 ; block0:
 ;   lui a0,1
-;   addi a0,a0,4095
+;   addi a0,a0,-1
 ;   ret
 ;
 ; Disassembled:
@ -528,7 +528,7 @@ block0:
 ; VCode:
 ; block0:
 ;   lui a0,1
-;   addi a0,a0,2048
+;   addi a0,a0,-2048
 ;   ret
 ;
 ; Disassembled:
--- a/cranelift/filetests/filetests/isa/riscv64/iconst-icmp-small.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/iconst-icmp-small.clif
@ -12,8 +12,8 @@ block0:

 ; VCode:
 ; block0:
-;   lui a5,1048574
-;   addi a1,a5,3532
+;   lui a5,-2
+;   addi a1,a5,-564
 ;   slli a2,a1,48
 ;   srli a4,a2,48
 ;   slli a0,a1,48
--- a/cranelift/filetests/filetests/isa/riscv64/simd-popcnt.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/simd-popcnt.clif
@ -96,7 +96,7 @@ block0(v0: i16x8):
 ;   vand.vx v14,v12,a4 #avl=8, #vtype=(e16, m1, ta, ma)
 ;   vadd.vv v8,v14,v13 #avl=8, #vtype=(e16, m1, ta, ma)
 ;   lui a2,1
-;   addi a4,a2,3855
+;   addi a4,a2,-241
 ;   vsrl.vi v14,v8,4 #avl=8, #vtype=(e16, m1, ta, ma)
 ;   vadd.vv v8,v8,v14 #avl=8, #vtype=(e16, m1, ta, ma)
 ;   vand.vx v10,v8,a4 #avl=8, #vtype=(e16, m1, ta, ma)
@ -173,7 +173,7 @@ block0(v0: i32x4):
 ;   vand.vx v14,v12,a4 #avl=4, #vtype=(e32, m1, ta, ma)
 ;   vadd.vv v8,v14,v13 #avl=4, #vtype=(e32, m1, ta, ma)
 ;   lui a2,61681
-;   addi a4,a2,3855
+;   addi a4,a2,-241
 ;   vsrl.vi v14,v8,4 #avl=4, #vtype=(e32, m1, ta, ma)
 ;   vadd.vv v8,v8,v14 #avl=4, #vtype=(e32, m1, ta, ma)
 ;   vand.vx v10,v8,a4 #avl=4, #vtype=(e32, m1, ta, ma)
--- a/cranelift/filetests/filetests/isa/riscv64/simd-vhighbits.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/simd-vhighbits.clif
@ -19,7 +19,7 @@ block0(v0: i8x16):
 ;   vmslt.vx v10,v8,zero #avl=16, #vtype=(e8, m1, ta, ma)
 ;   vmv.x.s a4,v10 #avl=2, #vtype=(e64, m1, ta, ma)
 ;   lui a0,16
-;   addi a2,a0,4095
+;   addi a2,a0,-1
 ;   and a0,a4,a2
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
--- a/cranelift/filetests/filetests/isa/riscv64/stack-limit.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/stack-limit.clif
@ -187,11 +187,11 @@ block0(v0: i64):
 ;   mv fp,sp
 ;   trap_ifc stk_ovf##(sp ult a0)
 ;   lui t5,98
-;   addi t5,t5,2688
+;   addi t5,t5,-1408
 ;   add t6,t5,a0
 ;   trap_ifc stk_ovf##(sp ult t6)
 ;   lui a0,98
-;   addi a0,a0,2688
+;   addi a0,a0,-1408
 ;   call %Probestack
 ;   add sp,-400000
 ; block0:
@ -299,11 +299,11 @@ block0(v0: i64):
 ;   ld t6,4(t6)
 ;   trap_ifc stk_ovf##(sp ult t6)
 ;   lui t5,98
-;   addi t5,t5,2688
+;   addi t5,t5,-1408
 ;   add t6,t5,t6
 ;   trap_ifc stk_ovf##(sp ult t6)
 ;   lui a0,98
-;   addi a0,a0,2688
+;   addi a0,a0,-1408
 ;   call %Probestack
 ;   add sp,-400000
 ; block0:
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0x1000_offset.wat
@ -44,8 +44,8 @@
 ;;   slli a3,a0,32
 ;;   srli a3,a3,32
 ;;   ld a4,8(a2)
-;;   lui a5,1048575
-;;   addi a5,a5,4092
+;;   lui a5,-1
+;;   addi a5,a5,-4
 ;;   add a4,a4,a5
 ;;   ugt a4,a3,a4##ty=i64
 ;;   bne a4,zero,taken(label3),not_taken(label1)
@ -66,8 +66,8 @@
 ;;   slli a2,a0,32
 ;;   srli a3,a2,32
 ;;   ld a2,8(a1)
-;;   lui a4,1048575
-;;   addi a4,a4,4092
+;;   lui a4,-1
+;;   addi a4,a4,-4
 ;;   add a2,a2,a4
 ;;   ugt a2,a3,a2##ty=i64
 ;;   bne a2,zero,taken(label3),not_taken(label1)
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@ -44,8 +44,8 @@
 ;;   slli a3,a0,32
 ;;   srli a3,a3,32
 ;;   ld a4,8(a2)
-;;   lui a5,1048575
-;;   addi a5,a5,4095
+;;   lui a5,-1
+;;   addi a5,a5,-1
 ;;   add a4,a4,a5
 ;;   ugt a4,a3,a4##ty=i64
 ;;   bne a4,zero,taken(label3),not_taken(label1)
@ -66,8 +66,8 @@
 ;;   slli a2,a0,32
 ;;   srli a3,a2,32
 ;;   ld a2,8(a1)
-;;   lui a4,1048575
-;;   addi a4,a4,4095
+;;   lui a4,-1
+;;   addi a4,a4,-1
 ;;   add a2,a2,a4
 ;;   ugt a2,a3,a2##ty=i64
 ;;   bne a2,zero,taken(label3),not_taken(label1)
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
@ -44,8 +44,8 @@
 ;;   slli a3,a0,32
 ;;   srli a5,a3,32
 ;;   ld a4,8(a2)
-;;   lui a3,1048575
-;;   addi a0,a3,4092
+;;   lui a3,-1
+;;   addi a0,a3,-4
 ;;   add a4,a4,a0
 ;;   ugt a0,a5,a4##ty=i64
 ;;   ld a4,0(a2)
@ -70,8 +70,8 @@
 ;;   slli a3,a0,32
 ;;   srli a5,a3,32
 ;;   ld a4,8(a1)
-;;   lui a3,1048575
-;;   addi a0,a3,4092
+;;   lui a3,-1
+;;   addi a0,a3,-4
 ;;   add a4,a4,a0
 ;;   ugt a0,a5,a4##ty=i64
 ;;   ld a4,0(a1)
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@ -44,8 +44,8 @@
 ;;   slli a3,a0,32
 ;;   srli a5,a3,32
 ;;   ld a4,8(a2)
-;;   lui a3,1048575
-;;   addi a0,a3,4095
+;;   lui a3,-1
+;;   addi a0,a3,-1
 ;;   add a4,a4,a0
 ;;   ugt a0,a5,a4##ty=i64
 ;;   ld a4,0(a2)
@ -70,8 +70,8 @@
 ;;   slli a3,a0,32
 ;;   srli a5,a3,32
 ;;   ld a4,8(a1)
-;;   lui a3,1048575
-;;   addi a0,a3,4095
+;;   lui a3,-1
+;;   addi a0,a3,-1
 ;;   add a4,a4,a0
 ;;   ugt a0,a5,a4##ty=i64
 ;;   ld a4,0(a1)
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0x1000_offset.wat
@ -42,8 +42,8 @@
 ;; function u0:0:
 ;; block0:
 ;;   ld a3,8(a2)
-;;   lui a5,1048575
-;;   addi a4,a5,4092
+;;   lui a5,-1
+;;   addi a4,a5,-4
 ;;   add a3,a3,a4
 ;;   ugt a3,a0,a3##ty=i64
 ;;   bne a3,zero,taken(label3),not_taken(label1)
@ -62,8 +62,8 @@
 ;; function u0:1:
 ;; block0:
 ;;   ld a2,8(a1)
-;;   lui a5,1048575
-;;   addi a3,a5,4092
+;;   lui a5,-1
+;;   addi a3,a5,-4
 ;;   add a2,a2,a3
 ;;   ugt a2,a0,a2##ty=i64
 ;;   bne a2,zero,taken(label3),not_taken(label1)
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@ -42,8 +42,8 @@
 ;; function u0:0:
 ;; block0:
 ;;   ld a3,8(a2)
-;;   lui a5,1048575
-;;   addi a4,a5,4095
+;;   lui a5,-1
+;;   addi a4,a5,-1
 ;;   add a3,a3,a4
 ;;   ugt a3,a0,a3##ty=i64
 ;;   bne a3,zero,taken(label3),not_taken(label1)
@ -62,8 +62,8 @@
 ;; function u0:1:
 ;; block0:
 ;;   ld a2,8(a1)
-;;   lui a5,1048575
-;;   addi a3,a5,4095
+;;   lui a5,-1
+;;   addi a3,a5,-1
 ;;   add a2,a2,a3
 ;;   ugt a2,a0,a2##ty=i64
 ;;   bne a2,zero,taken(label3),not_taken(label1)
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
@ -42,8 +42,8 @@
 ;; function u0:0:
 ;; block0:
 ;;   ld a3,8(a2)
-;;   lui a4,1048575
-;;   addi a4,a4,4092
+;;   lui a4,-1
+;;   addi a4,a4,-4
 ;;   add a3,a3,a4
 ;;   ugt a3,a0,a3##ty=i64
 ;;   ld a2,0(a2)
@ -66,8 +66,8 @@
 ;; function u0:1:
 ;; block0:
 ;;   ld a2,8(a1)
-;;   lui a3,1048575
-;;   addi a3,a3,4092
+;;   lui a3,-1
+;;   addi a3,a3,-4
 ;;   add a2,a2,a3
 ;;   ugt a3,a0,a2##ty=i64
 ;;   ld a2,0(a1)
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@ -42,8 +42,8 @@
 ;; function u0:0:
 ;; block0:
 ;;   ld a3,8(a2)
-;;   lui a4,1048575
-;;   addi a4,a4,4095
+;;   lui a4,-1
+;;   addi a4,a4,-1
 ;;   add a3,a3,a4
 ;;   ugt a3,a0,a3##ty=i64
 ;;   ld a2,0(a2)
@ -66,8 +66,8 @@
 ;; function u0:1:
 ;; block0:
 ;;   ld a2,8(a1)
-;;   lui a3,1048575
-;;   addi a3,a3,4095
+;;   lui a3,-1
+;;   addi a3,a3,-1
 ;;   add a2,a2,a3
 ;;   ugt a3,a0,a2##ty=i64
 ;;   ld a2,0(a1)
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i32_access_0_offset.wat
@ -42,7 +42,7 @@
 ;;   slli a3,a0,32
 ;;   srli a5,a3,32
 ;;   lui a3,65536
-;;   addi a0,a3,4092
+;;   addi a0,a3,-4
 ;;   ugt a4,a5,a0##ty=i64
 ;;   bne a4,zero,taken(label3),not_taken(label1)
 ;; block1:
@ -60,7 +60,7 @@
 ;;   slli a3,a0,32
 ;;   srli a5,a3,32
 ;;   lui a3,65536
-;;   addi a0,a3,4092
+;;   addi a0,a3,-4
 ;;   ugt a4,a5,a0##ty=i64
 ;;   bne a4,zero,taken(label3),not_taken(label1)
 ;; block1:
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i32_access_0x1000_offset.wat
@ -42,7 +42,7 @@
 ;;   slli a5,a0,32
 ;;   srli a3,a5,32
 ;;   lui a5,65535
-;;   addi a4,a5,4092
+;;   addi a4,a5,-4
 ;;   ugt a0,a3,a4##ty=i64
 ;;   bne a0,zero,taken(label3),not_taken(label1)
 ;; block1:
@ -62,7 +62,7 @@
 ;;   slli a5,a0,32
 ;;   srli a2,a5,32
 ;;   lui a5,65535
-;;   addi a3,a5,4092
+;;   addi a3,a5,-4
 ;;   ugt a0,a2,a3##ty=i64
 ;;   bne a0,zero,taken(label3),not_taken(label1)
 ;; block1:
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
@ -42,7 +42,7 @@
 ;;   slli a3,a0,32
 ;;   srli a5,a3,32
 ;;   lui a3,65536
-;;   addi a0,a3,4095
+;;   addi a0,a3,-1
 ;;   ugt a4,a5,a0##ty=i64
 ;;   bne a4,zero,taken(label3),not_taken(label1)
 ;; block1:
@ -60,7 +60,7 @@
 ;;   slli a3,a0,32
 ;;   srli a5,a3,32
 ;;   lui a3,65536
-;;   addi a0,a3,4095
+;;   addi a0,a3,-1
 ;;   ugt a4,a5,a0##ty=i64
 ;;   bne a4,zero,taken(label3),not_taken(label1)
 ;; block1:
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@ -42,7 +42,7 @@
 ;;   slli a5,a0,32
 ;;   srli a3,a5,32
 ;;   lui a5,65535
-;;   addi a4,a5,4095
+;;   addi a4,a5,-1
 ;;   ugt a0,a3,a4##ty=i64
 ;;   bne a0,zero,taken(label3),not_taken(label1)
 ;; block1:
@ -62,7 +62,7 @@
 ;;   slli a5,a0,32
 ;;   srli a2,a5,32
 ;;   lui a5,65535
-;;   addi a3,a5,4095
+;;   addi a3,a5,-1
 ;;   ugt a0,a2,a3##ty=i64
 ;;   bne a0,zero,taken(label3),not_taken(label1)
 ;; block1:
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat
@ -42,7 +42,7 @@
 ;;   slli a5,a0,32
 ;;   srli a3,a5,32
 ;;   lui a5,65536
-;;   addi a4,a5,4092
+;;   addi a4,a5,-4
 ;;   ugt a4,a3,a4##ty=i64
 ;;   ld a0,0(a2)
 ;;   add a0,a0,a3
@ -64,7 +64,7 @@
 ;;   slli a5,a0,32
 ;;   srli a2,a5,32
 ;;   lui a5,65536
-;;   addi a3,a5,4092
+;;   addi a3,a5,-4
 ;;   ugt a3,a2,a3##ty=i64
 ;;   ld a0,0(a1)
 ;;   add a0,a0,a2
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
@ -42,7 +42,7 @@
 ;;   slli a3,a0,32
 ;;   srli a4,a3,32
 ;;   lui a3,65535
-;;   addi a3,a3,4092
+;;   addi a3,a3,-4
 ;;   ugt a3,a4,a3##ty=i64
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a4
@ -66,7 +66,7 @@
 ;;   slli a2,a0,32
 ;;   srli a4,a2,32
 ;;   lui a2,65535
-;;   addi a3,a2,4092
+;;   addi a3,a2,-4
 ;;   ugt a3,a4,a3##ty=i64
 ;;   ld a2,0(a1)
 ;;   add a2,a2,a4
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
@ -42,7 +42,7 @@
 ;;   slli a5,a0,32
 ;;   srli a3,a5,32
 ;;   lui a5,65536
-;;   addi a4,a5,4095
+;;   addi a4,a5,-1
 ;;   ugt a4,a3,a4##ty=i64
 ;;   ld a0,0(a2)
 ;;   add a0,a0,a3
@ -64,7 +64,7 @@
 ;;   slli a5,a0,32
 ;;   srli a2,a5,32
 ;;   lui a5,65536
-;;   addi a3,a5,4095
+;;   addi a3,a5,-1
 ;;   ugt a3,a2,a3##ty=i64
 ;;   ld a0,0(a1)
 ;;   add a0,a0,a2
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@ -42,7 +42,7 @@
 ;;   slli a3,a0,32
 ;;   srli a4,a3,32
 ;;   lui a3,65535
-;;   addi a3,a3,4095
+;;   addi a3,a3,-1
 ;;   ugt a3,a4,a3##ty=i64
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a4
@ -66,7 +66,7 @@
 ;;   slli a2,a0,32
 ;;   srli a4,a2,32
 ;;   lui a2,65535
-;;   addi a3,a2,4095
+;;   addi a3,a2,-1
 ;;   ugt a3,a4,a3##ty=i64
 ;;   ld a2,0(a1)
 ;;   add a2,a2,a4
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_no_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_no_spectre_i32_access_0_offset.wat
@ -40,7 +40,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   lui a3,65536
-;;   addi a3,a3,4092
+;;   addi a3,a3,-4
 ;;   ugt a3,a0,a3##ty=i64
 ;;   bne a3,zero,taken(label3),not_taken(label1)
 ;; block1:
@ -56,7 +56,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   lui a2,65536
-;;   addi a3,a2,4092
+;;   addi a3,a2,-4
 ;;   ugt a2,a0,a3##ty=i64
 ;;   bne a2,zero,taken(label3),not_taken(label1)
 ;; block1:
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_no_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_no_spectre_i32_access_0x1000_offset.wat
@ -40,7 +40,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   lui a3,65535
-;;   addi a5,a3,4092
+;;   addi a5,a3,-4
 ;;   ugt a4,a0,a5##ty=i64
 ;;   bne a4,zero,taken(label3),not_taken(label1)
 ;; block1:
@ -58,7 +58,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   lui a3,65535
-;;   addi a5,a3,4092
+;;   addi a5,a3,-4
 ;;   ugt a4,a0,a5##ty=i64
 ;;   bne a4,zero,taken(label3),not_taken(label1)
 ;; block1:
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
@ -40,7 +40,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   lui a3,65536
-;;   addi a3,a3,4095
+;;   addi a3,a3,-1
 ;;   ugt a3,a0,a3##ty=i64
 ;;   bne a3,zero,taken(label3),not_taken(label1)
 ;; block1:
@ -56,7 +56,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   lui a2,65536
-;;   addi a3,a2,4095
+;;   addi a3,a2,-1
 ;;   ugt a2,a0,a3##ty=i64
 ;;   bne a2,zero,taken(label3),not_taken(label1)
 ;; block1:
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@ -40,7 +40,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   lui a3,65535
-;;   addi a5,a3,4095
+;;   addi a5,a3,-1
 ;;   ugt a4,a0,a5##ty=i64
 ;;   bne a4,zero,taken(label3),not_taken(label1)
 ;; block1:
@ -58,7 +58,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   lui a3,65535
-;;   addi a5,a3,4095
+;;   addi a5,a3,-1
 ;;   ugt a4,a0,a5##ty=i64
 ;;   bne a4,zero,taken(label3),not_taken(label1)
 ;; block1:
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat
@ -40,7 +40,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   lui a3,65536
-;;   addi a5,a3,4092
+;;   addi a5,a3,-4
 ;;   ugt a5,a0,a5##ty=i64
 ;;   ld a4,0(a2)
 ;;   add a4,a4,a0
@ -60,7 +60,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   lui a3,65536
-;;   addi a5,a3,4092
+;;   addi a5,a3,-4
 ;;   ugt a5,a0,a5##ty=i64
 ;;   ld a4,0(a1)
 ;;   add a4,a4,a0
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
@ -40,7 +40,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   lui a5,65535
-;;   addi a3,a5,4092
+;;   addi a3,a5,-4
 ;;   ugt a4,a0,a3##ty=i64
 ;;   ld a2,0(a2)
 ;;   add a0,a2,a0
@ -62,7 +62,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   lui a5,65535
-;;   addi a2,a5,4092
+;;   addi a2,a5,-4
 ;;   ugt a3,a0,a2##ty=i64
 ;;   ld a1,0(a1)
 ;;   add a0,a1,a0
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
@ -40,7 +40,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   lui a3,65536
-;;   addi a5,a3,4095
+;;   addi a5,a3,-1
 ;;   ugt a5,a0,a5##ty=i64
 ;;   ld a4,0(a2)
 ;;   add a4,a4,a0
@ -60,7 +60,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   lui a3,65536
-;;   addi a5,a3,4095
+;;   addi a5,a3,-1
 ;;   ugt a5,a0,a5##ty=i64
 ;;   ld a4,0(a1)
 ;;   add a4,a4,a0
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@ -40,7 +40,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   lui a5,65535
-;;   addi a3,a5,4095
+;;   addi a3,a5,-1
 ;;   ugt a4,a0,a3##ty=i64
 ;;   ld a2,0(a2)
 ;;   add a0,a2,a0
@ -62,7 +62,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   lui a5,65535
-;;   addi a2,a5,4095
+;;   addi a2,a5,-1
 ;;   ugt a3,a0,a2##ty=i64
 ;;   ld a1,0(a1)
 ;;   add a0,a1,a0
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0_offset.wat
@ -40,7 +40,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   lui a3,65536
-;;   addi a3,a3,4092
+;;   addi a3,a3,-4
 ;;   ugt a3,a0,a3##ty=i64
 ;;   bne a3,zero,taken(label3),not_taken(label1)
 ;; block1:
@ -56,7 +56,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   lui a2,65536
-;;   addi a3,a2,4092
+;;   addi a3,a2,-4
 ;;   ugt a2,a0,a3##ty=i64
 ;;   bne a2,zero,taken(label3),not_taken(label1)
 ;; block1:
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0x1000_offset.wat
@ -40,7 +40,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   lui a3,65535
-;;   addi a5,a3,4092
+;;   addi a5,a3,-4
 ;;   ugt a4,a0,a5##ty=i64
 ;;   bne a4,zero,taken(label3),not_taken(label1)
 ;; block1:
@ -58,7 +58,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   lui a3,65535
-;;   addi a5,a3,4092
+;;   addi a5,a3,-4
 ;;   ugt a4,a0,a5##ty=i64
 ;;   bne a4,zero,taken(label3),not_taken(label1)
 ;; block1:
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
@ -40,7 +40,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   lui a3,65536
-;;   addi a3,a3,4095
+;;   addi a3,a3,-1
 ;;   ugt a3,a0,a3##ty=i64
 ;;   bne a3,zero,taken(label3),not_taken(label1)
 ;; block1:
@ -56,7 +56,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   lui a2,65536
-;;   addi a3,a2,4095
+;;   addi a3,a2,-1
 ;;   ugt a2,a0,a3##ty=i64
 ;;   bne a2,zero,taken(label3),not_taken(label1)
 ;; block1:
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
@ -40,7 +40,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   lui a3,65535
-;;   addi a5,a3,4095
+;;   addi a5,a3,-1
 ;;   ugt a4,a0,a5##ty=i64
 ;;   bne a4,zero,taken(label3),not_taken(label1)
 ;; block1:
@ -58,7 +58,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   lui a3,65535
-;;   addi a5,a3,4095
+;;   addi a5,a3,-1
 ;;   ugt a4,a0,a5##ty=i64
 ;;   bne a4,zero,taken(label3),not_taken(label1)
 ;; block1:
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
@ -40,7 +40,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   lui a3,65536
-;;   addi a5,a3,4092
+;;   addi a5,a3,-4
 ;;   ugt a5,a0,a5##ty=i64
 ;;   ld a4,0(a2)
 ;;   add a4,a4,a0
@ -60,7 +60,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   lui a3,65536
-;;   addi a5,a3,4092
+;;   addi a5,a3,-4
 ;;   ugt a5,a0,a5##ty=i64
 ;;   ld a4,0(a1)
 ;;   add a4,a4,a0
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
@ -40,7 +40,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   lui a5,65535
-;;   addi a3,a5,4092
+;;   addi a3,a5,-4
 ;;   ugt a4,a0,a3##ty=i64
 ;;   ld a2,0(a2)
 ;;   add a0,a2,a0
@ -62,7 +62,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   lui a5,65535
-;;   addi a2,a5,4092
+;;   addi a2,a5,-4
 ;;   ugt a3,a0,a2##ty=i64
 ;;   ld a1,0(a1)
 ;;   add a0,a1,a0
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@ -40,7 +40,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   lui a3,65536
-;;   addi a5,a3,4095
+;;   addi a5,a3,-1
 ;;   ugt a5,a0,a5##ty=i64
 ;;   ld a4,0(a2)
 ;;   add a4,a4,a0
@ -60,7 +60,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   lui a3,65536
-;;   addi a5,a3,4095
+;;   addi a5,a3,-1
 ;;   ugt a5,a0,a5##ty=i64
 ;;   ld a4,0(a1)
 ;;   add a4,a4,a0
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@ -40,7 +40,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   lui a5,65535
-;;   addi a3,a5,4095
+;;   addi a3,a5,-1
 ;;   ugt a4,a0,a3##ty=i64
 ;;   ld a2,0(a2)
 ;;   add a0,a2,a0
@ -62,7 +62,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   lui a5,65535
-;;   addi a2,a5,4095
+;;   addi a2,a5,-1
 ;;   ugt a3,a0,a2##ty=i64
 ;;   ld a1,0(a1)
 ;;   add a0,a1,a0