Add support for two new type variable functions: half_vector() and
double_vector().
Use these two instructions to break down unsupported SIMD types and
build them up again.
Specify the location of arguments as well as the size of stack argument
array needed. The ABI annotations are optional, just like the value
locations.
Remove the Eq implementation for Signature which was only used by a
single parser test.
Every encoding recipe must specify register constraints on input and
output values.
Generate recipe constraint tables along with the other encoding tables.
We want to separate the Python classes that make up the DSL used to
define the Cretonne language from the concrete definitions.
- cdsl.types defines the ValueType class hierarchy.
- base.types defines the concrete types.
Include the test file preamble comments when building a filecheck
instance for every function in the file.
This makes it possible to define common regex variables in the preamble
and use these definitions for all the functions.
The copy/spill/fill instructions will be used by the register allocator
for splitting live ranges. The copy instruction is also useful when
rewriting values:
If a primary value is rewritten as a secondary result, a copy
instruction can be used instead:
a = foo x
=>
t, vx1 = call ...
a = copy vx1
Since a primary value must be the first value of an instruction, this
doesn't work:
a = foo x
=>
t, a = call ...
The 'lib/cretonne' directory will be the new root of a stand-alone
cretonne crate containg both Python and Rust sources.
This is in preparation for publishing crates on crates.io.
These refer to external functions and function signatures declared in
the preamble. Since we're already using the type names 'Signature' and
'Function', these entity references don't folow the usual EntityData /
Entity naming convention.
The isplit_lohi instruction breaks an integer into two halves. This will
typically be used to get the two halves of an `i64` value on 32-bit
CPUs.
The iconcat_lohi is the reverse operation. It reconstructs the `i64`
from the low and high bits.
Clarify terminology by always referring to a 'Target ISA' instead of just
'Target'. Use 'isa' as a module name instead of 'target' both in Rust and Python
code.
This is only to clarify terminology and not at all because Cargo insists on
using the 'target' sub-directory for build products. Oh, no. Not at all.
Move the CPUMode reference from EncRecipe to the Encoding itself, allowing
EncRecipes to be shared between CPU modes. At least RISC-V should be able to
share some recipes between RV32 and RV64 modes.
This was supposed to make verification fast, but WebAssembly is no longer in
this form since it's blocks can produce values.
Also, computing a flow graph and dominator tree is really fast anyway.
It is possible to return multiple values from a function, so ReturnData contains
a VariableArgs instance.
We don't want return instructions to appear as 'return (v1)', so tweak the
printing of VariableArgs so the parantheses are added externally.
Naming is interesting here. Since 'truncate' refers to removing the least
significant digits, use 'ireduce' instead. The 'extend' use is fairly
established. Don't abbreviate, avoid unfortunate modern vernacular.
This instruction uses two type variables: input and output. Make sure that our
parser can handle it. The output type variable annotation is mandatory.
Add a ValueTypeSet::example() method which is used to provide better diagnostics
for a missing type variable.
Add new intcc and floatcc operand types for the immediate condition codes on
these instructions.
Add new IntCompare and FloatCompare instruction formats.
Add a generic match_enum() parser function that can match any identifier-like
enumerated operand kind that implements FromStr.
Define the icmp and fcmp instructions in case.py. Include documentation for the
condition codes with these two instructions.
Jakob Stoklund Olesen
Andrea Canciani
Benjamin Bouvier
Jakob Stoklund Olesen