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@ -1481,17 +1481,17 @@ JIT_OP_ISIGN: |
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x86_clear_reg(inst, $1); |
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x86_clear_reg(inst, $1); |
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} |
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} |
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} |
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} |
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[reg, scratch reg] -> { |
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[=+reg, +reg] -> { |
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x86_clear_reg(inst, $2); |
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x86_clear_reg(inst, $1); |
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x86_test_reg_reg(inst, $1, $1); |
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x86_test_reg_reg(inst, $2, $2); |
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x86_set_reg(inst,X86_CC_GT, $2, 1); |
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x86_set_reg(inst, X86_CC_NZ, $1, 0); |
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x86_shift_reg_imm(inst, X86_SAR, $1, 31); |
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x86_shift_reg_imm(inst, X86_SAR, $2, 31); |
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x86_alu_reg_reg(inst, X86_ADD, $1, $2); |
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x86_alu_reg_reg(inst, X86_OR, $1, $2); |
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} |
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} |
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JIT_OP_LSIGN: |
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JIT_OP_LSIGN: |
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[=reg, imm] -> { |
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[=reg, imm] -> { |
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jit_int value = ((jit_int *)($2))[1]; |
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jit_long value = *((jit_long *)($2)); |
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if(value < 0) |
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if(value < 0) |
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{ |
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{ |
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x86_mov_reg_imm(inst, $1, -1); |
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x86_mov_reg_imm(inst, $1, -1); |
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@ -1505,12 +1505,12 @@ JIT_OP_LSIGN: |
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x86_clear_reg(inst, $1); |
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x86_clear_reg(inst, $1); |
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} |
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} |
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} |
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} |
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[=reg, lreg] -> { |
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[=+reg, +lreg] -> { |
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if($1 != %2) |
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x86_clear_reg(inst, $1); |
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{ |
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x86_alu_reg_reg(inst, X86_OR, $2, %2); |
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x86_mov_reg_reg(inst, $1, %2, 4); |
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x86_set_reg(inst, X86_CC_NZ, $1, 0); |
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} |
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x86_shift_reg_imm(inst, X86_SAR, %2, 31); |
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x86_shift_reg_imm(inst, X86_SAR, $1, 31); |
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x86_alu_reg_reg(inst, X86_OR, $1, %2); |
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} |
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} |
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/* |
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/* |
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