add JIT_OP_ISIGN and JIT_OP_LSIGN, optimize JIT_OP_LNEG;

fix bug freeing stack registers;

ChangeLog

@@ -1,3 +1,14 @@
+2006-11-25  Aleksey Demakov  <ademakov@gmail.com>
+
+	* jit/jit-reg-alloc.c (exch_stack_top, free_value): fix freeing
+	stack registers.
+
+2006-11-25  Kirill Kononenko  <Kirill.Kononenko@gmail.com>
+
+	* jit/jit-rules-x86.ins: add JIT_OP_ISIGN and JIT_OP_LSIGN rules
+	(patch #5533), optimize JIT_OP_LNEG rule (patch #5555). [with
+	some modifications by Aleksey Demakov.]
+
 2006-11-11  Aleksey Demakov  <ademakov@gmail.com>
 
 	* jit/jit-rules-x86.ins: add JIT_OP_IABS and JIT_OP_LABS rules.

jit/jit-reg-alloc.c

@@ -1740,6 +1740,7 @@ exch_stack_top(jit_gencode_t gen, int reg, int pop)
 		{
 			if(value2)
 			{
+				value2->in_register = 0;
 				value2->reg = -1;
 			}
 			gen->contents[top].values[index] = 0;
@@ -1806,6 +1807,7 @@ free_value(jit_gencode_t gen, jit_value_t value, int reg, int other_reg, int tem
 		{
 			/* Free stack register. */
 			exch_stack_top(gen, reg, 1);
+			return;
 		}
 #endif
 	}

jit/jit-rules-x86.ins

@@ -722,10 +722,18 @@ JIT_OP_LSUB: binary
 
 JIT_OP_LNEG: unary
 	[lreg] -> {
-		x86_not_reg(inst, $1);
-		x86_not_reg(inst, %1);
-		x86_alu_reg_imm(inst, X86_ADD, $1, 1);
+		/* TODO: gcc generates the first variant while
+		   AoA suggests the second. Figure out if one
+		   is better than other. */
+#if 1
+		x86_neg_reg(inst, $1);
 		x86_alu_reg_imm(inst, X86_ADC, %1, 0);
+		x86_neg_reg(inst, %1);
+#else
+		x86_neg_reg(inst, %1);
+		x86_neg_reg(inst, $1);
+		x86_alu_reg_imm(inst, X86_SBB, %1, 0);
+#endif
 	}
 
 JIT_OP_FADD, JIT_OP_DADD, JIT_OP_NFADD: binary, stack
@@ -1274,6 +1282,41 @@ JIT_OP_FABS, JIT_OP_DABS, JIT_OP_NFABS: unary, stack
 		x86_fabs(inst);
 	}
 
+JIT_OP_ISIGN:
+	[=reg, imm] -> {
+		if($2 < 0)
+		{
+			x86_mov_reg_imm(inst, $1, -1);
+		}
+		else
+		{
+			x86_clear_reg(inst, $1);
+		}
+	}
+	[reg] -> {
+		x86_shift_reg_imm(inst, X86_SAR, $1, 31);
+	}
+
+JIT_OP_LSIGN:
+	[=reg, imm] -> {
+		jit_int value = ((jit_int *)($2))[0];
+		if(value < 0)
+		{
+			x86_mov_reg_imm(inst, $1, -1);
+		}
+		else
+		{
+			x86_clear_reg(inst, $1);
+		}
+	}
+	[=reg, lreg] -> {
+		if($1 != $2)
+		{
+			x86_mov_reg_reg(inst, $1, %2, 4);
+		}
+		x86_shift_reg_imm(inst, X86_SAR, $1, 31);
+	}
+
 /*
  * Pointer check opcodes.
  */