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761 lines
23 KiB
761 lines
23 KiB
/*
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* arm_codegen.h - Code generation macros for the ARM processor.
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*
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* Copyright (C) 2003, 2004 Southern Storm Software, Pty Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _ARM_CODEGEN_H
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#define _ARM_CODEGEN_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Register numbers.
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*/
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typedef enum
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{
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ARM_R0 = 0,
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ARM_R1 = 1,
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ARM_R2 = 2,
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ARM_R3 = 3,
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ARM_R4 = 4,
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ARM_R5 = 5,
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ARM_R6 = 6,
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ARM_R7 = 7,
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ARM_R8 = 8,
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ARM_R9 = 9,
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ARM_R10 = 10,
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ARM_R11 = 11,
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ARM_R12 = 12,
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ARM_R13 = 13,
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ARM_R14 = 14,
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ARM_R15 = 15,
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ARM_FP = ARM_R11, /* Frame pointer */
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ARM_LINK = ARM_R14, /* Link register */
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ARM_PC = ARM_R15, /* Program counter */
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ARM_WORK = ARM_R12, /* Work register that we can destroy */
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ARM_SP = ARM_R13, /* Stack pointer */
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} ARM_REG;
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/*
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* Condition codes.
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*/
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typedef enum
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{
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ARM_CC_EQ = 0, /* Equal */
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ARM_CC_NE = 1, /* Not equal */
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ARM_CC_CS = 2, /* Carry set */
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ARM_CC_CC = 3, /* Carry clear */
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ARM_CC_MI = 4, /* Negative */
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ARM_CC_PL = 5, /* Positive */
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ARM_CC_VS = 6, /* Overflow set */
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ARM_CC_VC = 7, /* Overflow clear */
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ARM_CC_HI = 8, /* Higher */
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ARM_CC_LS = 9, /* Lower or same */
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ARM_CC_GE = 10, /* Signed greater than or equal */
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ARM_CC_LT = 11, /* Signed less than */
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ARM_CC_GT = 12, /* Signed greater than */
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ARM_CC_LE = 13, /* Signed less than or equal */
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ARM_CC_AL = 14, /* Always */
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ARM_CC_NV = 15, /* Never */
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ARM_CC_GE_UN = ARM_CC_CS, /* Unsigned greater than or equal */
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ARM_CC_LT_UN = ARM_CC_CC, /* Unsigned less than */
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ARM_CC_GT_UN = ARM_CC_HI, /* Unsigned greater than */
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ARM_CC_LE_UN = ARM_CC_LS, /* Unsigned less than or equal */
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} ARM_CC;
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/*
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* Arithmetic and logical operations.
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*/
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typedef enum
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{
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ARM_AND = 0, /* Bitwise AND */
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ARM_EOR = 1, /* Bitwise XOR */
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ARM_SUB = 2, /* Subtract */
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ARM_RSB = 3, /* Reverse subtract */
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ARM_ADD = 4, /* Add */
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ARM_ADC = 5, /* Add with carry */
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ARM_SBC = 6, /* Subtract with carry */
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ARM_RSC = 7, /* Reverse subtract with carry */
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ARM_TST = 8, /* Test with AND */
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ARM_TEQ = 9, /* Test with XOR */
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ARM_CMP = 10, /* Test with SUB (compare) */
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ARM_CMN = 11, /* Test with ADD */
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ARM_ORR = 12, /* Bitwise OR */
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ARM_MOV = 13, /* Move */
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ARM_BIC = 14, /* Test with Op1 & ~Op2 */
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ARM_MVN = 15, /* Bitwise NOT */
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} ARM_OP;
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/*
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* Shift operators.
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*/
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typedef enum
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{
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ARM_SHL = 0, /* Logical left */
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ARM_SHR = 1, /* Logical right */
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ARM_SAR = 2, /* Arithmetic right */
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ARM_ROR = 3, /* Rotate right */
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} ARM_SHIFT;
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/*
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* Number of registers that are used for parameters (r0-r3).
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*/
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#define ARM_NUM_PARAM_REGS 4
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/*
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* Type for instruction pointers (word-based, not byte-based).
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*/
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typedef unsigned int *arm_inst_ptr;
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/*
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* Build an instruction prefix from a condition code and a mask value.
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*/
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#define arm_build_prefix(cond,mask) \
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((((unsigned int)(cond)) << 28) | ((unsigned int)(mask)))
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/*
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* Build an "always" instruction prefix for a regular instruction.
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*/
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#define arm_prefix(mask) (arm_build_prefix(ARM_CC_AL, (mask)))
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/*
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* Build special "always" prefixes.
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*/
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#define arm_always (arm_build_prefix(ARM_CC_AL, 0))
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#define arm_always_cc (arm_build_prefix(ARM_CC_AL, (1 << 20)))
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#define arm_always_imm (arm_build_prefix(ARM_CC_AL, (1 << 25)))
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/*
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* Arithmetic or logical operation which doesn't set condition codes.
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*/
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#define arm_alu_reg_reg(inst,opc,dreg,sreg1,sreg2) \
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do { \
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*(inst)++ = arm_always | \
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(((unsigned int)(opc)) << 21) | \
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(((unsigned int)(dreg)) << 12) | \
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(((unsigned int)(sreg1)) << 16) | \
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((unsigned int)(sreg2)); \
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} while (0)
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#define arm_alu_reg_imm8(inst,opc,dreg,sreg,imm) \
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do { \
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*(inst)++ = arm_always_imm | \
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(((unsigned int)(opc)) << 21) | \
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(((unsigned int)(dreg)) << 12) | \
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(((unsigned int)(sreg)) << 16) | \
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((unsigned int)((imm) & 0xFF)); \
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} while (0)
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#define arm_alu_reg_imm8_cond(inst,opc,dreg,sreg,imm,cond) \
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do { \
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*(inst)++ = arm_build_prefix((cond), (1 << 25)) | \
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(((unsigned int)(opc)) << 21) | \
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(((unsigned int)(dreg)) << 12) | \
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(((unsigned int)(sreg)) << 16) | \
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((unsigned int)((imm) & 0xFF)); \
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} while (0)
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#define arm_alu_reg_imm8_rotate(inst,opc,dreg,sreg,imm,rotate) \
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do { \
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*(inst)++ = arm_always_imm | \
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(((unsigned int)(opc)) << 21) | \
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(((unsigned int)(dreg)) << 12) | \
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(((unsigned int)(sreg)) << 16) | \
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(((unsigned int)(rotate)) << 8) | \
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((unsigned int)((imm) & 0xFF)); \
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} while (0)
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extern arm_inst_ptr _arm_alu_reg_imm(arm_inst_ptr inst, int opc, int dreg,
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int sreg, int imm, int saveWork);
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#define arm_alu_reg_imm(inst,opc,dreg,sreg,imm) \
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do { \
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int __alu_imm = (int)(imm); \
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if(__alu_imm >= 0 && __alu_imm < 256) \
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{ \
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arm_alu_reg_imm8 \
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((inst), (opc), (dreg), (sreg), __alu_imm); \
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} \
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else \
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{ \
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(inst) = _arm_alu_reg_imm \
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((inst), (opc), (dreg), (sreg), __alu_imm, 0); \
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} \
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} while (0)
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#define arm_alu_reg_imm_save_work(inst,opc,dreg,sreg,imm) \
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do { \
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int __alu_imm_save = (int)(imm); \
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if(__alu_imm_save >= 0 && __alu_imm_save < 256) \
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{ \
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arm_alu_reg_imm8 \
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((inst), (opc), (dreg), (sreg), __alu_imm_save); \
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} \
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else \
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{ \
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(inst) = _arm_alu_reg_imm \
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((inst), (opc), (dreg), (sreg), __alu_imm_save, 1); \
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} \
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} while (0)
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#define arm_alu_reg(inst,opc,dreg,sreg) \
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do { \
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*(inst)++ = arm_always | \
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(((unsigned int)(opc)) << 21) | \
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(((unsigned int)(dreg)) << 12) | \
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((unsigned int)(sreg)); \
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} while (0)
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#define arm_alu_reg_cond(inst,opc,dreg,sreg,cond) \
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do { \
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*(inst)++ = arm_build_prefix((cond), 0) | \
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(((unsigned int)(opc)) << 21) | \
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(((unsigned int)(dreg)) << 12) | \
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((unsigned int)(sreg)); \
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} while (0)
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/*
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* Arithmetic or logical operation which sets condition codes.
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*/
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#define arm_alu_cc_reg_reg(inst,opc,dreg,sreg1,sreg2) \
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do { \
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*(inst)++ = arm_always_cc | \
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(((unsigned int)(opc)) << 21) | \
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(((unsigned int)(dreg)) << 12) | \
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(((unsigned int)(sreg1)) << 16) | \
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((unsigned int)(sreg2)); \
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} while (0)
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#define arm_alu_cc_reg_imm8(inst,opc,dreg,sreg,imm) \
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do { \
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*(inst)++ = arm_always_imm | arm_always_cc | \
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(((unsigned int)(opc)) << 21) | \
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(((unsigned int)(dreg)) << 12) | \
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(((unsigned int)(sreg)) << 16) | \
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((unsigned int)((imm) & 0xFF)); \
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} while (0)
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#define arm_alu_cc_reg(inst,opc,dreg,sreg) \
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do { \
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*(inst)++ = arm_always_cc | \
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(((unsigned int)(opc)) << 21) | \
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(((unsigned int)(dreg)) << 12) | \
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((unsigned int)(sreg)); \
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} while (0)
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/*
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* Test operation, which sets the condition codes but has no other result.
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*/
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#define arm_test_reg_reg(inst,opc,sreg1,sreg2) \
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do { \
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arm_alu_cc_reg_reg((inst), (opc), 0, (sreg1), (sreg2)); \
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} while (0)
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#define arm_test_reg_imm8(inst,opc,sreg,imm) \
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do { \
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arm_alu_cc_reg_imm8((inst), (opc), 0, (sreg), (imm)); \
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} while (0)
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#define arm_test_reg_imm(inst,opc,sreg,imm) \
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do { \
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int __test_imm = (int)(imm); \
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if(__test_imm >= 0 && __test_imm < 256) \
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{ \
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arm_alu_cc_reg_imm8((inst), (opc), 0, (sreg), __test_imm); \
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} \
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else \
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{ \
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arm_mov_reg_imm((inst), ARM_WORK, __test_imm); \
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arm_test_reg_reg((inst), (opc), (sreg), ARM_WORK); \
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} \
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} while (0)
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/*
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* Move a value between registers.
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*/
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#define arm_mov_reg_reg(inst,dreg,sreg) \
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do { \
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arm_alu_reg((inst), ARM_MOV, (dreg), (sreg)); \
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} while (0)
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/*
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* Move an immediate value into a register. This is hard because
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* ARM lacks an instruction to load a 32-bit immediate value directly.
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* We handle the simple cases and then bail out to a function for the rest.
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*/
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#define arm_mov_reg_imm8(inst,reg,imm) \
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do { \
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arm_alu_reg_imm8((inst), ARM_MOV, (reg), 0, (imm)); \
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} while (0)
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#define arm_mov_reg_imm8_rotate(inst,reg,imm,rotate) \
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do { \
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arm_alu_reg_imm8_rotate((inst), ARM_MOV, (reg), \
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0, (imm), (rotate)); \
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} while (0)
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extern arm_inst_ptr _arm_mov_reg_imm(arm_inst_ptr inst, int reg, int value);
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#define arm_mov_reg_imm(inst,reg,imm) \
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do { \
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int __imm = (int)(imm); \
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if(__imm >= 0 && __imm < 256) \
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{ \
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arm_mov_reg_imm8((inst), (reg), __imm); \
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} \
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else if((reg) == ARM_PC) \
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{ \
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(inst) = _arm_mov_reg_imm((inst), ARM_WORK, __imm); \
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arm_mov_reg_reg((inst), ARM_PC, ARM_WORK); \
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} \
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else if(__imm > -256 && __imm < 0) \
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{ \
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arm_mov_reg_imm8((inst), (reg), ~(__imm)); \
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arm_alu_reg((inst), ARM_MVN, (reg), (reg)); \
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} \
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else \
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{ \
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(inst) = _arm_mov_reg_imm((inst), (reg), __imm); \
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} \
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} while (0)
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/*
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* Clear a register to zero.
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*/
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#define arm_clear_reg(inst,reg) \
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do { \
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arm_mov_reg_imm8((inst), (reg), 0); \
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} while (0)
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/*
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* No-operation instruction.
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*/
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#define arm_nop(inst) arm_mov_reg_reg((inst), ARM_R0, ARM_R0)
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/*
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* Perform a shift operation.
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*/
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#define arm_shift_reg_reg(inst,opc,dreg,sreg1,sreg2) \
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do { \
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*(inst)++ = arm_always | \
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(((unsigned int)ARM_MOV) << 21) | \
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(((unsigned int)(dreg)) << 12) | \
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(((unsigned int)(sreg2)) << 8) | \
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(((unsigned int)(opc)) << 5) | \
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((unsigned int)(1 << 4)) | \
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((unsigned int)(sreg1)); \
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} while (0)
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#define arm_shift_reg_imm8(inst,opc,dreg,sreg,imm) \
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do { \
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*(inst)++ = arm_always | \
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(((unsigned int)ARM_MOV) << 21) | \
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(((unsigned int)(dreg)) << 12) | \
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(((unsigned int)(opc)) << 5) | \
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(((unsigned int)(imm)) << 7) | \
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((unsigned int)(sreg)); \
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} while (0)
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/*
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* Perform a multiplication instruction. Note: ARM instruction rules
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* say that dreg should not be the same as sreg2, so we swap the order
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* of the arguments if that situation occurs. We assume that sreg1
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* and sreg2 are distinct registers.
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*/
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#define arm_mul_reg_reg(inst,dreg,sreg1,sreg2) \
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do { \
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if((dreg) != (sreg2)) \
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{ \
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*(inst)++ = arm_prefix(0x00000090) | \
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(((unsigned int)(dreg)) << 16) | \
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(((unsigned int)(sreg1)) << 8) | \
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((unsigned int)(sreg2)); \
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} \
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else \
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{ \
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*(inst)++ = arm_prefix(0x00000090) | \
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(((unsigned int)(dreg)) << 16) | \
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(((unsigned int)(sreg2)) << 8) | \
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((unsigned int)(sreg1)); \
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} \
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} while (0)
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/*
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* Branch or jump immediate by a byte offset. The offset is
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* assumed to be +/- 32 Mbytes.
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*/
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#define arm_branch_imm(inst,cond,imm) \
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do { \
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*(inst)++ = arm_build_prefix((cond), 0x0A000000) | \
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(((unsigned int)(((int)(imm)) >> 2)) & \
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0x00FFFFFF); \
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} while (0)
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#define arm_jump_imm(inst,imm) arm_branch_imm((inst), ARM_CC_AL, (imm))
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/*
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* Branch or jump to a specific target location. The offset is
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* assumed to be +/- 32 Mbytes.
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*/
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#define arm_branch(inst,cond,target) \
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do { \
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int __br_offset = (int)(((unsigned char *)(target)) - \
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(((unsigned char *)(inst)) + 8)); \
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arm_branch_imm((inst), (cond), __br_offset); \
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} while (0)
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#define arm_jump(inst,target) arm_branch((inst), ARM_CC_AL, (target))
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/*
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* Jump to a specific target location that may be greater than
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* 32 Mbytes away from the current location.
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*/
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#define arm_jump_long(inst,target) \
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do { \
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int __jmp_offset = (int)(((unsigned char *)(target)) - \
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(((unsigned char *)(inst)) + 8)); \
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if(__jmp_offset >= -0x04000000 && __jmp_offset < 0x04000000) \
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{ \
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arm_jump_imm((inst), __jmp_offset); \
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} \
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else \
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{ \
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arm_mov_reg_imm((inst), ARM_PC, (int)(target)); \
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} \
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} while (0)
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/*
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* Back-patch a branch instruction.
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*/
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#define arm_patch(inst,target) \
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do { \
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int __p_offset = (int)(((unsigned char *)(target)) - \
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(((unsigned char *)(inst)) + 8)); \
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__p_offset = (__p_offset >> 2) & 0x00FFFFFF; \
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*((int *)(inst)) = (*((int *)(inst)) & 0xFF000000) | \
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__p_offset; \
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} while (0)
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/*
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* Call a subroutine immediate by a byte offset.
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*/
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#define arm_call_imm(inst,imm) \
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do { \
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*(inst)++ = arm_prefix(0x0B000000) | \
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(((unsigned int)(((int)(imm)) >> 2)) & \
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0x00FFFFFF); \
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} while (0)
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/*
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* Call a subroutine at a specific target location.
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*/
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#define arm_call(inst,target) \
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do { \
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int __call_offset = (int)(((unsigned char *)(target)) - \
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(((unsigned char *)(inst)) + 8)); \
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if(__call_offset >= -0x04000000 && __call_offset < 0x04000000) \
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{ \
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arm_call_imm((inst), __call_offset); \
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} \
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else \
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{ \
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arm_mov_reg_imm((inst), ARM_WORK, (int)(target)); \
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arm_mov_reg_reg((inst), ARM_LINK, ARM_PC); \
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arm_mov_reg_reg((inst), ARM_PC, ARM_WORK); \
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} \
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} while (0)
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/*
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* Return from a subroutine, where the return address is in the link register.
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*/
|
|
#define arm_return(inst) \
|
|
do { \
|
|
arm_mov_reg_reg((inst), ARM_PC, ARM_LINK); \
|
|
} while (0)
|
|
|
|
/*
|
|
* Push a register onto the system stack.
|
|
*/
|
|
#define arm_push_reg(inst,reg) \
|
|
do { \
|
|
*(inst)++ = arm_prefix(0x05200004) | \
|
|
(((unsigned int)ARM_SP) << 16) | \
|
|
(((unsigned int)(reg)) << 12); \
|
|
} while (0)
|
|
|
|
/*
|
|
* Pop a register from the system stack.
|
|
*/
|
|
#define arm_pop_reg(inst,reg) \
|
|
do { \
|
|
*(inst)++ = arm_prefix(0x04900004) | \
|
|
(((unsigned int)ARM_SP) << 16) | \
|
|
(((unsigned int)(reg)) << 12); \
|
|
} while (0)
|
|
|
|
/*
|
|
* Set up a local variable frame, and save the registers in "regset".
|
|
*/
|
|
#define arm_setup_frame(inst,regset) \
|
|
do { \
|
|
arm_mov_reg_reg((inst), ARM_WORK, ARM_SP); \
|
|
*(inst)++ = arm_prefix(0x0920D800) | \
|
|
(((unsigned int)ARM_SP) << 16) | \
|
|
(((unsigned int)(regset))); \
|
|
arm_alu_reg_imm8((inst), ARM_SUB, ARM_FP, ARM_WORK, 4); \
|
|
} while (0)
|
|
|
|
/*
|
|
* Pop a local variable frame, restore the registers in "regset",
|
|
* and return to the caller.
|
|
*/
|
|
#define arm_pop_frame(inst,regset) \
|
|
do { \
|
|
*(inst)++ = arm_prefix(0x0910A800) | \
|
|
(((unsigned int)ARM_FP) << 16) | \
|
|
(((unsigned int)(regset))); \
|
|
} while (0)
|
|
|
|
/*
|
|
* Pop a local variable frame, in preparation for a tail call.
|
|
* This restores "lr" to its original value, but does not set "pc".
|
|
*/
|
|
#define arm_pop_frame_tail(inst,regset) \
|
|
do { \
|
|
*(inst)++ = arm_prefix(0x09106800) | \
|
|
(((unsigned int)ARM_FP) << 16) | \
|
|
(((unsigned int)(regset))); \
|
|
} while (0)
|
|
|
|
/*
|
|
* Load a word value from a pointer and then advance the pointer.
|
|
*/
|
|
#define arm_load_advance(inst,dreg,sreg) \
|
|
do { \
|
|
*(inst)++ = arm_prefix(0x04900004) | \
|
|
(((unsigned int)(sreg)) << 16) | \
|
|
(((unsigned int)(dreg)) << 12); \
|
|
} while (0)
|
|
|
|
/*
|
|
* Load a value from an address into a register.
|
|
*/
|
|
#define arm_load_membase_either(inst,reg,basereg,imm,mask) \
|
|
do { \
|
|
int __mb_offset = (int)(imm); \
|
|
if(__mb_offset >= 0 && __mb_offset < (1 << 12)) \
|
|
{ \
|
|
*(inst)++ = arm_prefix(0x05900000 | (mask)) | \
|
|
(((unsigned int)(basereg)) << 16) | \
|
|
(((unsigned int)(reg)) << 12) | \
|
|
((unsigned int)__mb_offset); \
|
|
} \
|
|
else if(__mb_offset > -(1 << 12) && __mb_offset < 0) \
|
|
{ \
|
|
*(inst)++ = arm_prefix(0x05100000 | (mask)) | \
|
|
(((unsigned int)(basereg)) << 16) | \
|
|
(((unsigned int)(reg)) << 12) | \
|
|
((unsigned int)(-__mb_offset)); \
|
|
} \
|
|
else \
|
|
{ \
|
|
arm_mov_reg_imm((inst), ARM_WORK, __mb_offset); \
|
|
*(inst)++ = arm_prefix(0x07900000 | (mask)) | \
|
|
(((unsigned int)(basereg)) << 16) | \
|
|
(((unsigned int)(reg)) << 12) | \
|
|
((unsigned int)ARM_WORK); \
|
|
} \
|
|
} while (0)
|
|
#define arm_load_membase(inst,reg,basereg,imm) \
|
|
do { \
|
|
arm_load_membase_either((inst), (reg), (basereg), (imm), 0); \
|
|
} while (0)
|
|
#define arm_load_membase_byte(inst,reg,basereg,imm) \
|
|
do { \
|
|
arm_load_membase_either((inst), (reg), (basereg), (imm), \
|
|
0x00400000); \
|
|
} while (0)
|
|
#define arm_load_membase_sbyte(inst,reg,basereg,imm) \
|
|
do { \
|
|
arm_load_membase_either((inst), (reg), (basereg), (imm), \
|
|
0x00400000); \
|
|
arm_shift_reg_imm8((inst), ARM_SHL, (reg), (reg), 24); \
|
|
arm_shift_reg_imm8((inst), ARM_SAR, (reg), (reg), 24); \
|
|
} while (0)
|
|
#define arm_load_membase_ushort(inst,reg,basereg,imm) \
|
|
do { \
|
|
arm_load_membase_byte((inst), ARM_WORK, (basereg), (imm)); \
|
|
arm_load_membase_byte((inst), (reg), (basereg), (imm) + 1); \
|
|
arm_shift_reg_imm8((inst), ARM_SHL, (reg), (reg), 8); \
|
|
arm_alu_reg_reg((inst), ARM_ORR, (reg), (reg), ARM_WORK); \
|
|
} while (0)
|
|
#define arm_load_membase_short(inst,reg,basereg,imm) \
|
|
do { \
|
|
arm_load_membase_byte((inst), ARM_WORK, (basereg), (imm)); \
|
|
arm_load_membase_byte((inst), (reg), (basereg), (imm) + 1); \
|
|
arm_shift_reg_imm8((inst), ARM_SHL, (reg), (reg), 24); \
|
|
arm_shift_reg_imm8((inst), ARM_SAR, (reg), (reg), 16); \
|
|
arm_alu_reg_reg((inst), ARM_ORR, (reg), (reg), ARM_WORK); \
|
|
} while (0)
|
|
|
|
/*
|
|
* Store a value from a register into an address.
|
|
*
|
|
* Note: storing a 16-bit value destroys the value in the register.
|
|
*/
|
|
#define arm_store_membase_either(inst,reg,basereg,imm,mask) \
|
|
do { \
|
|
int __sm_offset = (int)(imm); \
|
|
if(__sm_offset >= 0 && __sm_offset < (1 << 12)) \
|
|
{ \
|
|
*(inst)++ = arm_prefix(0x05800000 | (mask)) | \
|
|
(((unsigned int)(basereg)) << 16) | \
|
|
(((unsigned int)(reg)) << 12) | \
|
|
((unsigned int)__sm_offset); \
|
|
} \
|
|
else if(__sm_offset > -(1 << 12) && __sm_offset < 0) \
|
|
{ \
|
|
*(inst)++ = arm_prefix(0x05000000 | (mask)) | \
|
|
(((unsigned int)(basereg)) << 16) | \
|
|
(((unsigned int)(reg)) << 12) | \
|
|
((unsigned int)(-__sm_offset)); \
|
|
} \
|
|
else \
|
|
{ \
|
|
arm_mov_reg_imm((inst), ARM_WORK, __sm_offset); \
|
|
*(inst)++ = arm_prefix(0x07800000 | (mask)) | \
|
|
(((unsigned int)(basereg)) << 16) | \
|
|
(((unsigned int)(reg)) << 12) | \
|
|
((unsigned int)ARM_WORK); \
|
|
} \
|
|
} while (0)
|
|
#define arm_store_membase(inst,reg,basereg,imm) \
|
|
do { \
|
|
arm_store_membase_either((inst), (reg), (basereg), (imm), 0); \
|
|
} while (0)
|
|
#define arm_store_membase_byte(inst,reg,basereg,imm) \
|
|
do { \
|
|
arm_store_membase_either((inst), (reg), (basereg), (imm), \
|
|
0x00400000); \
|
|
} while (0)
|
|
#define arm_store_membase_sbyte(inst,reg,basereg,imm) \
|
|
do { \
|
|
arm_store_membase_byte((inst), (reg), (basereg), (imm)); \
|
|
} while (0)
|
|
#define arm_store_membase_short(inst,reg,basereg,imm) \
|
|
do { \
|
|
arm_store_membase_either((inst), (reg), (basereg), (imm), \
|
|
0x00400000); \
|
|
arm_shift_reg_imm8((inst), ARM_SHR, (reg), (reg), 8); \
|
|
arm_store_membase_either((inst), (reg), (basereg), \
|
|
(imm) + 1, 0x00400000); \
|
|
} while (0)
|
|
#define arm_store_membase_ushort(inst,reg,basereg,imm) \
|
|
do { \
|
|
arm_store_membase_short((inst), (reg), (basereg), (imm)); \
|
|
} while (0)
|
|
|
|
/*
|
|
* Load a value from an indexed address into a register.
|
|
*/
|
|
#define arm_load_memindex_either(inst,reg,basereg,indexreg,shift,mask) \
|
|
do { \
|
|
*(inst)++ = arm_prefix(0x07900000 | (mask)) | \
|
|
(((unsigned int)(basereg)) << 16) | \
|
|
(((unsigned int)(reg)) << 12) | \
|
|
(((unsigned int)(shift)) << 7) | \
|
|
((unsigned int)(indexreg)); \
|
|
} while (0)
|
|
#define arm_load_memindex(inst,reg,basereg,indexreg) \
|
|
do { \
|
|
arm_load_memindex_either((inst), (reg), (basereg), \
|
|
(indexreg), 2, 0); \
|
|
} while (0)
|
|
#define arm_load_memindex_byte(inst,reg,basereg,indexreg) \
|
|
do { \
|
|
arm_load_memindex_either((inst), (reg), (basereg), \
|
|
(indexreg), 0, 0x00400000); \
|
|
} while (0)
|
|
#define arm_load_memindex_sbyte(inst,reg,basereg,indexreg) \
|
|
do { \
|
|
arm_load_memindex_either((inst), (reg), (basereg), \
|
|
(indexreg), 0, 0x00400000); \
|
|
arm_shift_reg_imm8((inst), ARM_SHL, (reg), (reg), 24); \
|
|
arm_shift_reg_imm8((inst), ARM_SAR, (reg), (reg), 24); \
|
|
} while (0)
|
|
#define arm_load_memindex_ushort(inst,reg,basereg,indexreg) \
|
|
do { \
|
|
arm_alu_reg_reg((inst), ARM_ADD, ARM_WORK, (basereg), \
|
|
(indexreg)); \
|
|
arm_alu_reg_reg((inst), ARM_ADD, ARM_WORK, ARM_WORK, \
|
|
(indexreg)); \
|
|
arm_load_membase_byte((inst), (reg), ARM_WORK, 0); \
|
|
arm_load_membase_byte((inst), ARM_WORK, ARM_WORK, 1); \
|
|
arm_shift_reg_imm8((inst), ARM_SHL, ARM_WORK, ARM_WORK, 8); \
|
|
arm_alu_reg_reg((inst), ARM_ORR, (reg), (reg), ARM_WORK); \
|
|
} while (0)
|
|
#define arm_load_memindex_short(inst,reg,basereg,indexreg) \
|
|
do { \
|
|
arm_alu_reg_reg((inst), ARM_ADD, ARM_WORK, (basereg), \
|
|
(indexreg)); \
|
|
arm_alu_reg_reg((inst), ARM_ADD, ARM_WORK, ARM_WORK, \
|
|
(indexreg)); \
|
|
arm_load_membase_byte((inst), (reg), ARM_WORK, 0); \
|
|
arm_load_membase_byte((inst), ARM_WORK, ARM_WORK, 1); \
|
|
arm_shift_reg_imm8((inst), ARM_SHL, ARM_WORK, ARM_WORK, 24); \
|
|
arm_shift_reg_imm8((inst), ARM_SAR, ARM_WORK, ARM_WORK, 16); \
|
|
arm_alu_reg_reg((inst), ARM_ORR, (reg), (reg), ARM_WORK); \
|
|
} while (0)
|
|
|
|
/*
|
|
* Store a value from a register into an indexed address.
|
|
*
|
|
* Note: storing a 16-bit value destroys the values in the base
|
|
* register and the source register.
|
|
*/
|
|
#define arm_store_memindex_either(inst,reg,basereg,indexreg,shift,mask) \
|
|
do { \
|
|
*(inst)++ = arm_prefix(0x07800000 | (mask)) | \
|
|
(((unsigned int)(basereg)) << 16) | \
|
|
(((unsigned int)(reg)) << 12) | \
|
|
(((unsigned int)(shift)) << 7) | \
|
|
((unsigned int)(indexreg)); \
|
|
} while (0)
|
|
#define arm_store_memindex(inst,reg,basereg,indexreg) \
|
|
do { \
|
|
arm_store_memindex_either((inst), (reg), (basereg), \
|
|
(indexreg), 2, 0); \
|
|
} while (0)
|
|
#define arm_store_memindex_byte(inst,reg,basereg,indexreg) \
|
|
do { \
|
|
arm_store_memindex_either((inst), (reg), (basereg), \
|
|
(indexreg), 0, 0x00400000); \
|
|
} while (0)
|
|
#define arm_store_memindex_sbyte(inst,reg,basereg,indexreg) \
|
|
do { \
|
|
arm_store_memindex_byte((inst), (reg), (basereg), \
|
|
(indexreg)); \
|
|
} while (0)
|
|
#define arm_store_memindex_short(inst,reg,basereg,indexreg) \
|
|
do { \
|
|
arm_store_memindex_either((inst), (reg), (basereg), \
|
|
(indexreg), 1, 0x00400000); \
|
|
arm_alu_reg_imm8((inst), ARM_ADD, (basereg), (basereg), 1); \
|
|
arm_shift_reg_imm8((inst), ARM_SHR, (reg), (reg), 8); \
|
|
arm_store_memindex_either((inst), (reg), (basereg), \
|
|
(indexreg), 1, 0x00400000); \
|
|
} while (0)
|
|
#define arm_store_memindex_ushort(inst,reg,basereg,indexreg) \
|
|
do { \
|
|
arm_store_memindex_short((inst), (reg), \
|
|
(basereg), (indexreg)); \
|
|
} while (0)
|
|
|
|
#ifdef __cplusplus
|
|
};
|
|
#endif
|
|
|
|
#endif /* _ARM_CODEGEN_H */
|
|
|