Browse Source
Includes: - Support for CAN3. - Support for UART9 and UART10. - stm32f413xg.ld and stm32f413xh.ld linker scripts. - stm32f413_af.csv alternate function mapping. - startup_stm32f413xx.s because F413 has different interrupt vector table. - Memory configuration with: 240K filesystem, 240K heap, 16K stack.pull/4727/head
Chris Mason
6 years ago
committed by
Damien George
Damien George
14 changed files with 925 additions and 15 deletions
@ -0,0 +1,580 @@ |
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/** |
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****************************************************************************** |
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* @file startup_stm32f413xx.s |
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* @author MCD Application Team |
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* @brief STM32F413xx Devices vector table for GCC based toolchains. |
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* This module performs: |
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* - Set the initial SP |
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* - Set the initial PC == Reset_Handler, |
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* - Set the vector table entries with the exceptions ISR address |
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* - Branches to main in the C library (which eventually |
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* calls main()). |
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* After Reset the Cortex-M4 processor is in Thread mode, |
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* priority is Privileged, and the Stack is set to Main. |
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****************************************************************************** |
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* @attention |
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* |
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* <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> |
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* |
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* Redistribution and use in source and binary forms, with or without modification, |
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* are permitted provided that the following conditions are met: |
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* 1. Redistributions of source code must retain the above copyright notice, |
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* this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright notice, |
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* this list of conditions and the following disclaimer in the documentation |
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* and/or other materials provided with the distribution. |
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* 3. Neither the name of STMicroelectronics nor the names of its contributors |
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* may be used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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* |
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****************************************************************************** |
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*/ |
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|
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.syntax unified |
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.cpu cortex-m4 |
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.fpu softvfp |
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.thumb |
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|
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.global g_pfnVectors |
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.global Default_Handler |
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|
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/* start address for the initialization values of the .data section. |
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defined in linker script */ |
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.word _sidata |
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/* start address for the .data section. defined in linker script */ |
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.word _sdata |
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/* end address for the .data section. defined in linker script */ |
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.word _edata |
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/* start address for the .bss section. defined in linker script */ |
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.word _sbss |
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/* end address for the .bss section. defined in linker script */ |
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.word _ebss |
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/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ |
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|
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/** |
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* @brief This is the code that gets called when the processor first |
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* starts execution following a reset event. Only the absolutely |
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* necessary set is performed, after which the application |
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* supplied main() routine is called. |
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* @param None |
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* @retval : None |
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*/ |
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|
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.section .text.Reset_Handler |
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.weak Reset_Handler |
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.type Reset_Handler, %function |
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Reset_Handler: |
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ldr sp, =_estack /* set stack pointer */ |
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|
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/* Copy the data segment initializers from flash to SRAM */ |
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movs r1, #0 |
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b LoopCopyDataInit |
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CopyDataInit: |
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ldr r3, =_sidata |
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ldr r3, [r3, r1] |
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str r3, [r0, r1] |
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adds r1, r1, #4 |
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|
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LoopCopyDataInit: |
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ldr r0, =_sdata |
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ldr r3, =_edata |
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adds r2, r0, r1 |
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cmp r2, r3 |
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bcc CopyDataInit |
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ldr r2, =_sbss |
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b LoopFillZerobss |
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/* Zero fill the bss segment. */ |
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FillZerobss: |
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movs r3, #0 |
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str r3, [r2], #4 |
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|
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LoopFillZerobss: |
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ldr r3, = _ebss |
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cmp r2, r3 |
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bcc FillZerobss |
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|
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/* Call the clock system intitialization function.*/ |
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bl SystemInit |
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/* Call static constructors */ |
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/*bl __libc_init_array*/ |
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/* Call the application's entry point.*/ |
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bl main |
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bx lr |
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.size Reset_Handler, .-Reset_Handler |
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|
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/** |
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* @brief This is the code that gets called when the processor receives an |
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* unexpected interrupt. This simply enters an infinite loop, preserving |
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* the system state for examination by a debugger. |
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* @param None |
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* @retval None |
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*/ |
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.section .text.Default_Handler,"ax",%progbits |
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Default_Handler: |
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Infinite_Loop: |
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b Infinite_Loop |
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.size Default_Handler, .-Default_Handler |
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/****************************************************************************** |
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* |
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* The minimal vector table for a Cortex M3. Note that the proper constructs |
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* must be placed on this to ensure that it ends up at physical address |
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* 0x0000.0000. |
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* |
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*******************************************************************************/ |
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.section .isr_vector,"a",%progbits |
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.type g_pfnVectors, %object |
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.size g_pfnVectors, .-g_pfnVectors |
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|
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g_pfnVectors: |
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.word _estack |
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.word Reset_Handler |
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.word NMI_Handler |
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.word HardFault_Handler |
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.word MemManage_Handler |
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.word BusFault_Handler |
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.word UsageFault_Handler |
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.word 0 |
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.word 0 |
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.word 0 |
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.word 0 |
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.word SVC_Handler |
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.word DebugMon_Handler |
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.word 0 |
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.word PendSV_Handler |
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.word SysTick_Handler |
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|
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/* External Interrupts */ |
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.word WWDG_IRQHandler /* Window WatchDog */ |
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.word PVD_IRQHandler /* PVD through EXTI Line detection */ |
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.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ |
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.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ |
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.word FLASH_IRQHandler /* FLASH */ |
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.word RCC_IRQHandler /* RCC */ |
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.word EXTI0_IRQHandler /* EXTI Line0 */ |
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.word EXTI1_IRQHandler /* EXTI Line1 */ |
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.word EXTI2_IRQHandler /* EXTI Line2 */ |
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.word EXTI3_IRQHandler /* EXTI Line3 */ |
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.word EXTI4_IRQHandler /* EXTI Line4 */ |
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.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ |
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.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ |
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.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ |
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.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ |
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.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ |
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.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ |
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.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ |
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.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ |
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.word CAN1_TX_IRQHandler /* CAN1 TX */ |
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.word CAN1_RX0_IRQHandler /* CAN1 RX0 */ |
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.word CAN1_RX1_IRQHandler /* CAN1 RX1 */ |
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.word CAN1_SCE_IRQHandler /* CAN1 SCE */ |
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.word EXTI9_5_IRQHandler /* External Line[9:5]s */ |
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.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ |
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.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ |
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.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ |
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.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ |
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.word TIM2_IRQHandler /* TIM2 */ |
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.word TIM3_IRQHandler /* TIM3 */ |
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.word TIM4_IRQHandler /* TIM4 */ |
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.word I2C1_EV_IRQHandler /* I2C1 Event */ |
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.word I2C1_ER_IRQHandler /* I2C1 Error */ |
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.word I2C2_EV_IRQHandler /* I2C2 Event */ |
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.word I2C2_ER_IRQHandler /* I2C2 Error */ |
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.word SPI1_IRQHandler /* SPI1 */ |
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.word SPI2_IRQHandler /* SPI2 */ |
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.word USART1_IRQHandler /* USART1 */ |
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.word USART2_IRQHandler /* USART2 */ |
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.word USART3_IRQHandler /* USART3 */ |
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.word EXTI15_10_IRQHandler /* External Line[15:10]s */ |
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.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ |
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.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ |
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.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ |
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.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ |
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.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ |
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.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ |
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.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ |
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.word FSMC_IRQHandler /* FSMC */ |
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.word SDIO_IRQHandler /* SDIO */ |
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.word TIM5_IRQHandler /* TIM5 */ |
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.word SPI3_IRQHandler /* SPI3 */ |
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.word UART4_IRQHandler /* UART4 */ |
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.word UART5_IRQHandler /* UART5 */ |
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.word TIM6_DAC_IRQHandler /* TIM6, DAC1 and DAC2 */ |
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.word TIM7_IRQHandler /* TIM7 */ |
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.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ |
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.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ |
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.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ |
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.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ |
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.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ |
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.word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter0 */ |
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.word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter1 */ |
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.word CAN2_TX_IRQHandler /* CAN2 TX */ |
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.word CAN2_RX0_IRQHandler /* CAN2 RX0 */ |
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.word CAN2_RX1_IRQHandler /* CAN2 RX1 */ |
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.word CAN2_SCE_IRQHandler /* CAN2 SCE */ |
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.word OTG_FS_IRQHandler /* USB OTG FS */ |
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.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ |
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.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ |
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.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ |
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.word USART6_IRQHandler /* USART6 */ |
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.word I2C3_EV_IRQHandler /* I2C3 event */ |
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.word I2C3_ER_IRQHandler /* I2C3 error */ |
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.word CAN3_TX_IRQHandler /* CAN3 TX */ |
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.word CAN3_RX0_IRQHandler /* CAN3 RX0 */ |
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.word CAN3_RX1_IRQHandler /* CAN3 RX1 */ |
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.word CAN3_SCE_IRQHandler /* CAN3 SCE */ |
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.word 0 /* Reserved */ |
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.word 0 /* Reserved */ |
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.word RNG_IRQHandler /* RNG */ |
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.word FPU_IRQHandler /* FPU */ |
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.word UART7_IRQHandler /* UART7 */ |
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.word UART8_IRQHandler /* UART8 */ |
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.word SPI4_IRQHandler /* SPI4 */ |
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.word SPI5_IRQHandler /* SPI5 */ |
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.word 0 /* Reserved */ |
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.word SAI1_IRQHandler /* SAI1 */ |
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.word UART9_IRQHandler /* UART9 */ |
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.word UART10_IRQHandler /* UART10 */ |
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.word 0 /* Reserved */ |
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.word 0 /* Reserved */ |
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.word QUADSPI_IRQHandler /* QuadSPI */ |
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.word 0 /* Reserved */ |
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.word 0 /* Reserved */ |
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.word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */ |
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.word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ |
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.word LPTIM1_IRQHandler /* LPTIM1 */ |
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.word DFSDM2_FLT0_IRQHandler /* DFSDM2 Filter0 */ |
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.word DFSDM2_FLT1_IRQHandler /* DFSDM2 Filter1 */ |
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.word DFSDM2_FLT2_IRQHandler /* DFSDM2 Filter2 */ |
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.word DFSDM2_FLT3_IRQHandler /* DFSDM2 Filter3 */ |
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|
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/******************************************************************************* |
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* |
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* Provide weak aliases for each Exception handler to the Default_Handler. |
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* As they are weak aliases, any function with the same name will override |
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* this definition. |
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* |
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*******************************************************************************/ |
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.weak NMI_Handler |
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.thumb_set NMI_Handler,Default_Handler |
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|
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.weak HardFault_Handler |
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.thumb_set HardFault_Handler,Default_Handler |
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|
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.weak MemManage_Handler |
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.thumb_set MemManage_Handler,Default_Handler |
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|
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.weak BusFault_Handler |
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.thumb_set BusFault_Handler,Default_Handler |
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|
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.weak UsageFault_Handler |
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.thumb_set UsageFault_Handler,Default_Handler |
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|
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.weak SVC_Handler |
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.thumb_set SVC_Handler,Default_Handler |
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|
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.weak DebugMon_Handler |
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.thumb_set DebugMon_Handler,Default_Handler |
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|
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.weak PendSV_Handler |
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.thumb_set PendSV_Handler,Default_Handler |
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|
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.weak SysTick_Handler |
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.thumb_set SysTick_Handler,Default_Handler |
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|
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.weak WWDG_IRQHandler |
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.thumb_set WWDG_IRQHandler,Default_Handler |
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|
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.weak PVD_IRQHandler |
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.thumb_set PVD_IRQHandler,Default_Handler |
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|
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.weak TAMP_STAMP_IRQHandler |
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.thumb_set TAMP_STAMP_IRQHandler,Default_Handler |
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|
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.weak RTC_WKUP_IRQHandler |
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.thumb_set RTC_WKUP_IRQHandler,Default_Handler |
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|
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.weak FLASH_IRQHandler |
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.thumb_set FLASH_IRQHandler,Default_Handler |
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|
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.weak RCC_IRQHandler |
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.thumb_set RCC_IRQHandler,Default_Handler |
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.weak EXTI0_IRQHandler |
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.thumb_set EXTI0_IRQHandler,Default_Handler |
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.weak EXTI1_IRQHandler |
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.thumb_set EXTI1_IRQHandler,Default_Handler |
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.weak EXTI2_IRQHandler |
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.thumb_set EXTI2_IRQHandler,Default_Handler |
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.weak EXTI3_IRQHandler |
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.thumb_set EXTI3_IRQHandler,Default_Handler |
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.weak EXTI4_IRQHandler |
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.thumb_set EXTI4_IRQHandler,Default_Handler |
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.weak DMA1_Stream0_IRQHandler |
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.thumb_set DMA1_Stream0_IRQHandler,Default_Handler |
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.weak DMA1_Stream1_IRQHandler |
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.thumb_set DMA1_Stream1_IRQHandler,Default_Handler |
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.weak DMA1_Stream2_IRQHandler |
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.thumb_set DMA1_Stream2_IRQHandler,Default_Handler |
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.weak DMA1_Stream3_IRQHandler |
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.thumb_set DMA1_Stream3_IRQHandler,Default_Handler |
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.weak DMA1_Stream4_IRQHandler |
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.thumb_set DMA1_Stream4_IRQHandler,Default_Handler |
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.weak DMA1_Stream5_IRQHandler |
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.thumb_set DMA1_Stream5_IRQHandler,Default_Handler |
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.weak DMA1_Stream6_IRQHandler |
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.thumb_set DMA1_Stream6_IRQHandler,Default_Handler |
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.weak ADC_IRQHandler |
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.thumb_set ADC_IRQHandler,Default_Handler |
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.weak CAN1_TX_IRQHandler |
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.thumb_set CAN1_TX_IRQHandler,Default_Handler |
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.weak CAN1_RX0_IRQHandler |
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.thumb_set CAN1_RX0_IRQHandler,Default_Handler |
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.weak CAN1_RX1_IRQHandler |
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.thumb_set CAN1_RX1_IRQHandler,Default_Handler |
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.weak CAN1_SCE_IRQHandler |
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.thumb_set CAN1_SCE_IRQHandler,Default_Handler |
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.weak EXTI9_5_IRQHandler |
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.thumb_set EXTI9_5_IRQHandler,Default_Handler |
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.weak TIM1_BRK_TIM9_IRQHandler |
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.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler |
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|
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.weak TIM1_UP_TIM10_IRQHandler |
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.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler |
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|
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.weak TIM1_TRG_COM_TIM11_IRQHandler |
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.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler |
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|
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.weak TIM1_CC_IRQHandler |
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.thumb_set TIM1_CC_IRQHandler,Default_Handler |
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|
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.weak TIM2_IRQHandler |
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.thumb_set TIM2_IRQHandler,Default_Handler |
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.weak TIM3_IRQHandler |
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.thumb_set TIM3_IRQHandler,Default_Handler |
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.weak TIM4_IRQHandler |
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.thumb_set TIM4_IRQHandler,Default_Handler |
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.weak I2C1_EV_IRQHandler |
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.thumb_set I2C1_EV_IRQHandler,Default_Handler |
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|
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.weak I2C1_ER_IRQHandler |
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.thumb_set I2C1_ER_IRQHandler,Default_Handler |
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|
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.weak I2C2_EV_IRQHandler |
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.thumb_set I2C2_EV_IRQHandler,Default_Handler |
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|
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.weak I2C2_ER_IRQHandler |
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.thumb_set I2C2_ER_IRQHandler,Default_Handler |
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|
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.weak SPI1_IRQHandler |
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.thumb_set SPI1_IRQHandler,Default_Handler |
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|
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.weak SPI2_IRQHandler |
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.thumb_set SPI2_IRQHandler,Default_Handler |
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|
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.weak USART1_IRQHandler |
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.thumb_set USART1_IRQHandler,Default_Handler |
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|
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.weak USART2_IRQHandler |
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.thumb_set USART2_IRQHandler,Default_Handler |
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|
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.weak USART3_IRQHandler |
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.thumb_set USART3_IRQHandler,Default_Handler |
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|
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.weak EXTI15_10_IRQHandler |
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.thumb_set EXTI15_10_IRQHandler,Default_Handler |
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|
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.weak RTC_Alarm_IRQHandler |
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.thumb_set RTC_Alarm_IRQHandler,Default_Handler |
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|
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.weak OTG_FS_WKUP_IRQHandler |
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.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler |
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|
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.weak TIM8_BRK_TIM12_IRQHandler |
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.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler |
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|
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.weak TIM8_UP_TIM13_IRQHandler |
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.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler |
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.weak TIM8_TRG_COM_TIM14_IRQHandler |
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.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler |
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.weak TIM8_CC_IRQHandler |
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.thumb_set TIM8_CC_IRQHandler,Default_Handler |
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|
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.weak DMA1_Stream7_IRQHandler |
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.thumb_set DMA1_Stream7_IRQHandler,Default_Handler |
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|
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.weak FSMC_IRQHandler |
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.thumb_set FSMC_IRQHandler,Default_Handler |
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|
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.weak SDIO_IRQHandler |
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.thumb_set SDIO_IRQHandler,Default_Handler |
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|
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.weak TIM5_IRQHandler |
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.thumb_set TIM5_IRQHandler,Default_Handler |
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|
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.weak SPI3_IRQHandler |
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.thumb_set SPI3_IRQHandler,Default_Handler |
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|
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.weak UART4_IRQHandler |
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.thumb_set UART4_IRQHandler,Default_Handler |
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|
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.weak UART5_IRQHandler |
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.thumb_set UART5_IRQHandler,Default_Handler |
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|
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.weak TIM6_DAC_IRQHandler |
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.thumb_set TIM6_DAC_IRQHandler,Default_Handler |
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.weak TIM7_IRQHandler |
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.thumb_set TIM7_IRQHandler,Default_Handler |
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.weak DMA2_Stream0_IRQHandler |
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.thumb_set DMA2_Stream0_IRQHandler,Default_Handler |
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|
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.weak DMA2_Stream1_IRQHandler |
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.thumb_set DMA2_Stream1_IRQHandler,Default_Handler |
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|
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.weak DMA2_Stream2_IRQHandler |
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.thumb_set DMA2_Stream2_IRQHandler,Default_Handler |
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.weak DMA2_Stream3_IRQHandler |
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.thumb_set DMA2_Stream3_IRQHandler,Default_Handler |
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.weak DMA2_Stream4_IRQHandler |
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.thumb_set DMA2_Stream4_IRQHandler,Default_Handler |
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.weak DFSDM1_FLT0_IRQHandler |
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.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler |
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.weak DFSDM1_FLT1_IRQHandler |
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.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler |
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|
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.weak CAN2_TX_IRQHandler |
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.thumb_set CAN2_TX_IRQHandler,Default_Handler |
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.weak CAN2_RX0_IRQHandler |
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.thumb_set CAN2_RX0_IRQHandler,Default_Handler |
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.weak CAN2_RX1_IRQHandler |
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.thumb_set CAN2_RX1_IRQHandler,Default_Handler |
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.weak CAN2_SCE_IRQHandler |
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.thumb_set CAN2_SCE_IRQHandler,Default_Handler |
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.weak OTG_FS_IRQHandler |
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.thumb_set OTG_FS_IRQHandler,Default_Handler |
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.weak DMA2_Stream5_IRQHandler |
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.thumb_set DMA2_Stream5_IRQHandler,Default_Handler |
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|
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.weak DMA2_Stream6_IRQHandler |
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.thumb_set DMA2_Stream6_IRQHandler,Default_Handler |
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|
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.weak DMA2_Stream7_IRQHandler |
|||
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler |
|||
|
|||
.weak USART6_IRQHandler |
|||
.thumb_set USART6_IRQHandler,Default_Handler |
|||
|
|||
.weak I2C3_EV_IRQHandler |
|||
.thumb_set I2C3_EV_IRQHandler,Default_Handler |
|||
|
|||
.weak I2C3_ER_IRQHandler |
|||
.thumb_set I2C3_ER_IRQHandler,Default_Handler |
|||
|
|||
.weak CAN3_TX_IRQHandler |
|||
.thumb_set CAN3_TX_IRQHandler,Default_Handler |
|||
|
|||
.weak CAN3_RX0_IRQHandler |
|||
.thumb_set CAN3_RX0_IRQHandler,Default_Handler |
|||
|
|||
.weak CAN3_RX1_IRQHandler |
|||
.thumb_set CAN3_RX1_IRQHandler,Default_Handler |
|||
|
|||
.weak CAN3_SCE_IRQHandler |
|||
.thumb_set CAN3_SCE_IRQHandler,Default_Handler |
|||
|
|||
.weak RNG_IRQHandler |
|||
.thumb_set RNG_IRQHandler,Default_Handler |
|||
|
|||
.weak FPU_IRQHandler |
|||
.thumb_set FPU_IRQHandler,Default_Handler |
|||
|
|||
.weak UART7_IRQHandler |
|||
.thumb_set UART7_IRQHandler,Default_Handler |
|||
|
|||
.weak UART8_IRQHandler |
|||
.thumb_set UART8_IRQHandler,Default_Handler |
|||
|
|||
.weak SPI4_IRQHandler |
|||
.thumb_set SPI4_IRQHandler,Default_Handler |
|||
|
|||
.weak SPI5_IRQHandler |
|||
.thumb_set SPI5_IRQHandler,Default_Handler |
|||
|
|||
.weak SAI1_IRQHandler |
|||
.thumb_set SAI1_IRQHandler,Default_Handler |
|||
|
|||
.weak UART9_IRQHandler |
|||
.thumb_set UART9_IRQHandler,Default_Handler |
|||
|
|||
.weak UART10_IRQHandler |
|||
.thumb_set UART10_IRQHandler,Default_Handler |
|||
|
|||
.weak QUADSPI_IRQHandler |
|||
.thumb_set QUADSPI_IRQHandler,Default_Handler |
|||
|
|||
.weak FMPI2C1_EV_IRQHandler |
|||
.thumb_set FMPI2C1_EV_IRQHandler,Default_Handler |
|||
|
|||
.weak FMPI2C1_ER_IRQHandler |
|||
.thumb_set FMPI2C1_ER_IRQHandler,Default_Handler |
|||
|
|||
.weak LPTIM1_IRQHandler |
|||
.thumb_set LPTIM1_IRQHandler,Default_Handler |
|||
|
|||
.weak DFSDM2_FLT0_IRQHandler |
|||
.thumb_set DFSDM2_FLT0_IRQHandler,Default_Handler |
|||
|
|||
.weak DFSDM2_FLT1_IRQHandler |
|||
.thumb_set DFSDM2_FLT1_IRQHandler,Default_Handler |
|||
|
|||
.weak DFSDM2_FLT2_IRQHandler |
|||
.thumb_set DFSDM2_FLT2_IRQHandler,Default_Handler |
|||
|
|||
.weak DFSDM2_FLT3_IRQHandler |
|||
.thumb_set DFSDM2_FLT3_IRQHandler,Default_Handler |
|||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|||
|
Can't render this file because it has a wrong number of fields in line 19.
|
@ -0,0 +1,31 @@ |
|||
/* |
|||
GNU linker script for STM32F413xg (1MB flash, 320kB RAM) |
|||
*/ |
|||
|
|||
/* Specify the memory areas */ |
|||
/* FLASH_FS2 is placed before FLASH_TEXT to support 1MB and 1.5MB FLASH with common code in flashbdev.c */ |
|||
MEMORY |
|||
{ |
|||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K /* entire flash */ |
|||
FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 16K /* sector 0 */ |
|||
FLASH_FS (rx) : ORIGIN = 0x08004000, LENGTH = 176K /* sectors 1,2,3 are 16K, 4 is 64K, 5 is 128K (64K used) for filesystem */ |
|||
FLASH_FS2 (rx) : ORIGIN = 0x08040000, LENGTH = 128K /* sector 6 is 128K (64K used) for filesystem, Total filesystem 240K */ |
|||
FLASH_TEXT (rx) : ORIGIN = 0x08060000, LENGTH = 640K /* sectors 7,8,9,10,11 are 128K*/ |
|||
SRAM2 (xrw) : ORIGIN = 0x10000000, LENGTH = 64K |
|||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 256K |
|||
} |
|||
|
|||
/* produce a link error if there is not this amount of RAM for these sections */ |
|||
_minimum_stack_size = 2K; |
|||
_minimum_heap_size = 16K; |
|||
|
|||
/* Define tho top end of the stack. The stack is full descending so begins just |
|||
above last byte of RAM. Note that EABI requires the stack to be 8-byte |
|||
aligned for a call. */ |
|||
_estack = ORIGIN(RAM) + LENGTH(RAM); |
|||
|
|||
/* RAM extents for the garbage collector */ |
|||
_ram_start = ORIGIN(RAM); |
|||
_ram_end = ORIGIN(RAM) + LENGTH(RAM); |
|||
_heap_start = _ebss; /* heap starts just after statically allocated memory */ |
|||
_heap_end = _ram_end - 16K; /* 240K, tunable */ |
|||
@ -0,0 +1,31 @@ |
|||
/* |
|||
GNU linker script for STM32F413xh (1.5MB flash, 320kB RAM) |
|||
*/ |
|||
|
|||
/* Specify the memory areas */ |
|||
/* FLASH_FS2 is placed before FLASH_TEXT to support 1MB and 1.5MB FLASH with common code in flashbdev.c */ |
|||
MEMORY |
|||
{ |
|||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1536K /* entire flash */ |
|||
FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 16K /* sector 0 */ |
|||
FLASH_FS (rx) : ORIGIN = 0x08004000, LENGTH = 176K /* sectors 1,2,3 are 16K, 4 is 64K, 5 is 128K (64K used) for filesystem */ |
|||
FLASH_FS2 (rx) : ORIGIN = 0x08040000, LENGTH = 128K /* sector 6 is 128K (64K used) for filesystem, Total filesystem 240K */ |
|||
FLASH_TEXT (rx) : ORIGIN = 0x08060000, LENGTH = 1152K /* sectors 7,8,9,10,11,12,13,14,15 are 128K*/ |
|||
SRAM2 (xrw) : ORIGIN = 0x10000000, LENGTH = 64K |
|||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 256K |
|||
} |
|||
|
|||
/* produce a link error if there is not this amount of RAM for these sections */ |
|||
_minimum_stack_size = 2K; |
|||
_minimum_heap_size = 16K; |
|||
|
|||
/* Define tho top end of the stack. The stack is full descending so begins just |
|||
above last byte of RAM. Note that EABI requires the stack to be 8-byte |
|||
aligned for a call. */ |
|||
_estack = ORIGIN(RAM) + LENGTH(RAM); |
|||
|
|||
/* RAM extents for the garbage collector */ |
|||
_ram_start = ORIGIN(RAM); |
|||
_ram_end = ORIGIN(RAM) + LENGTH(RAM); |
|||
_heap_start = _ebss; /* heap starts just after statically allocated memory */ |
|||
_heap_end = _ram_end - 16K; /* 240K, tunable */ |
|||
Loading…
Reference in new issue