drivers/memory/spiflash.c: Write 2nd byte of SR as separate command.

The existing spiflash driver writes both bytes of SR as a single command.
Some flash chips don't support multi-byte writes such as this, and have a
seperate command to write SR byte 1 and SR byte 2 (referred to in the code
as CR). This used in the spiflash initialisation to enable quad mode. The
quad enable bit is in the second SR byte. This change still issues the
multi-byte command, then issues a single byte command for just the second
SR byte. For chips that only support one of the commands, the unsupported
command should be ignored silently. For chips that support both types of
command, the SR will be written twice.

This depends on https://github.com/micropython/micropython/pull/11931 for
the stm32 port to allow single-byte spi commands.

Signed-off-by: Victor Rajewski <victor@allumeenergy.com.au>

drivers/memory/spiflash.c

@@ -40,6 +40,7 @@
 #define CMD_RDSR        (0x05)
 #define CMD_WREN        (0x06)
 #define CMD_SEC_ERASE   (0x20)
+#define CMD_WRCR        (0x31)  // sometimes referred to as SR byte 2
 #define CMD_RDCR        (0x35)
 #define CMD_RD_DEVID    (0x9f)
 #define CMD_CHIP_ERASE  (0xc7)
@@ -199,10 +200,17 @@ void mp_spiflash_init(mp_spiflash_t *self) {
         }
         uint32_t data = (sr & 0xff) | (cr & 0xff) << 8;
         if (ret == 0 && !(data & (QSPI_QE_MASK << 8))) {
+            // Write both bytes of SR
             data |= QSPI_QE_MASK << 8;
             mp_spiflash_write_cmd(self, CMD_WREN);
             mp_spiflash_write_cmd_data(self, CMD_WRSR, 2, data);
             mp_spiflash_wait_wip0(self);
+
+            // Write just byte 2 of SR for flash that only supports that mode of setting SR
+            data = (cr & 0xff) | QSPI_QE_MASK;
+            mp_spiflash_write_cmd(self, CMD_WREN);
+            mp_spiflash_write_cmd_data(self, CMD_WRCR, 1, data);
+            mp_spiflash_wait_wip0(self);
         }
     }