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OCOTP_Init() has been removed from mphalport.c. The library files are missing for the MIMXRT1015, and for just reading the OCOTP the Init is not required.pull/8401/head
robert-hh
3 years ago
committed by
Damien George
Damien George
10 changed files with 365 additions and 2 deletions
@ -0,0 +1,38 @@ |
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/* Memory configuration */ |
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#if defined MICROPY_HW_FLASH_RESERVED |
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reserved_size = MICROPY_HW_FLASH_RESERVED; |
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#endif |
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#if MICROPY_HW_FLASH_TYPE == qspi_nor |
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flash_start = 0x60000000; |
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#else |
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#error Unknown MICROPY_HW_FLASH_TYPE |
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#endif |
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flash_size = MICROPY_HW_FLASH_SIZE; |
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flash_end = DEFINED(reserved_size) ? ((flash_start) + (flash_size - reserved_size)) : ((flash_start) + (flash_size)); |
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flash_config_start = flash_start; |
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flash_config_size = 0x00001000; |
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ivt_start = flash_start + 0x00001000; |
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ivt_size = 0x00001000; |
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interrupts_start = flash_start + 0x00002000; |
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interrupts_size = 0x00000400; |
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text_start = flash_start + 0x00002400; |
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vfs_start = flash_start + 0x00100000; |
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text_size = ((vfs_start) - (text_start)); |
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vfs_size = ((flash_end) - (vfs_start)); |
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itcm_start = 0x00000000; |
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itcm_size = 0x00008000; |
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dtcm_start = 0x20000000; |
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dtcm_size = 0x00008000; |
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ocrm_start = 0x20200000; |
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ocrm_size = 0x00010000; |
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/* 24kiB stack. */ |
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__stack_size__ = 0x5000; |
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_estack = __StackTop; |
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_sstack = __StackLimit; |
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/* Use second OCRAM bank for GC heap. */ |
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/* Use all OCRAM for the GC heap. */ |
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_gc_heap_start = ORIGIN(m_ocrm); |
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_gc_heap_end = ORIGIN(m_ocrm) + LENGTH(m_ocrm); |
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@ -0,0 +1,23 @@ |
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{ |
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"deploy": [ |
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"../deploy_mimxrt.md" |
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], |
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"docs": "", |
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"features": [ |
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"MicroSD", |
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"MicroUSB", |
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"Microphone", |
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"AudioCodec", |
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"CAN", |
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"OpenSDA", |
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"JLink" |
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], |
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"images": [ |
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"MIMXRT1015-EVK-TOP.jpg" |
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], |
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"mcu": "mimxrt", |
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"product": "MIMXRT1015_EVK", |
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"thumbnail": "", |
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"url": "https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1015-evaluation-kit:MIMXRT1015-EVK", |
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"vendor": "NXP" |
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} |
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@ -0,0 +1,107 @@ |
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/*
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* Copyright 2018-2019 NXP |
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* All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#ifndef _CLOCK_CONFIG_H_ |
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#define _CLOCK_CONFIG_H_ |
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#include "fsl_common.h" |
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/*******************************************************************************
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* Definitions |
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******************************************************************************/ |
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#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ |
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#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ |
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/*******************************************************************************
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************************ BOARD_InitBootClocks function ************************ |
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******************************************************************************/ |
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#if defined(__cplusplus) |
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extern "C" { |
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#endif /* __cplusplus*/ |
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/*!
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* @brief This function executes default configuration of clocks. |
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* |
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*/ |
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void BOARD_InitBootClocks(void); |
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#if defined(__cplusplus) |
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} |
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#endif /* __cplusplus*/ |
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/*******************************************************************************
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********************** Configuration BOARD_BootClockRUN *********************** |
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******************************************************************************/ |
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/*******************************************************************************
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* Definitions for BOARD_BootClockRUN configuration |
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******************************************************************************/ |
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#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ |
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/* Clock outputs (values are in Hz): */ |
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#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL |
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#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL |
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#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL |
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#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL |
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#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL |
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#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL |
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#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL |
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#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL |
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#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 125000000UL |
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#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL |
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#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL |
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#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL |
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#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL |
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#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL |
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#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL |
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#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL |
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#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL |
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#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL |
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#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL |
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#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL |
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#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL |
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#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL |
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#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL |
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#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL |
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#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL |
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#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL |
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#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL |
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#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL |
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#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL |
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#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL |
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#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL |
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#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL |
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#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL |
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/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
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*/ |
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extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; |
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/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
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*/ |
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extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; |
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/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
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*/ |
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extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; |
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/*******************************************************************************
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* API for BOARD_BootClockRUN configuration |
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******************************************************************************/ |
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#if defined(__cplusplus) |
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extern "C" { |
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#endif /* __cplusplus*/ |
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/*!
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* @brief This function executes configuration of clocks. |
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* |
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*/ |
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void BOARD_BootClockRUN(void); |
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#if defined(__cplusplus) |
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} |
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#endif /* __cplusplus*/ |
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#endif /* _CLOCK_CONFIG_H_ */ |
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@ -0,0 +1,84 @@ |
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#define MICROPY_HW_BOARD_NAME "i.MX RT1015 EVK" |
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#define MICROPY_HW_MCU_NAME "MIMXRT1015DAF5A" |
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// i.MX RT1015 EVK has 3 board LED
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// Todo: think about replacing the define with searching in the generated pins?
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#define MICROPY_HW_LED1_PIN (pin_GPIO_SD_B1_00) |
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#define MICROPY_HW_LED2_PIN (pin_GPIO_SD_B1_01) |
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#define MICROPY_HW_LED3_PIN (pin_GPIO_SD_B1_02) |
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#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_low(pin)) |
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#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin)) |
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#define MICROPY_HW_NUM_PIN_IRQS (3 * 32) |
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// Define mapping logical UART # to hardware UART #
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// RX/TX HW-UART Logical UART
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// DEBUG USB LPUART1 -> 0
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// D3/D5 LPUART1
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// D0/D1 LPUART2 -> 1
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// D6/D9 LPUART3 -> 2
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// A0/A1 LPUART4 -> 5
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#define MICROPY_HW_UART_NUM (sizeof(uart_index_table) / sizeof(uart_index_table)[0]) |
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#define MICROPY_HW_UART_INDEX { 1, 4, 3 } |
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#define IOMUX_TABLE_UART \ |
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{ IOMUXC_GPIO_AD_B0_06_LPUART1_TX }, { IOMUXC_GPIO_AD_B0_07_LPUART1_RX }, \ |
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{ 0 }, { 0 }, \ |
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{ IOMUXC_GPIO_AD_B0_14_LPUART3_TX }, { IOMUXC_GPIO_AD_B0_15_LPUART3_RX }, \ |
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{ IOMUXC_GPIO_EMC_32_LPUART4_TX }, { IOMUXC_GPIO_EMC_33_LPUART4_RX }, \ |
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#define MICROPY_HW_SPI_INDEX { 1 } |
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#define IOMUX_TABLE_SPI \ |
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{ IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK }, { IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0 }, \ |
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{ IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO }, { IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI }, \ |
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{ 0 } |
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#define DMA_REQ_SRC_RX { 0, kDmaRequestMuxLPSPI1Rx, kDmaRequestMuxLPSPI2Rx } |
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#define DMA_REQ_SRC_TX { 0, kDmaRequestMuxLPSPI1Tx, kDmaRequestMuxLPSPI2Tx } |
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// Define mapping hardware I2C # to logical I2C #
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// SDA/SCL HW-I2C Logical I2C
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// D14/D15 LPI2C4 -> 0
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// A4/A5 LPI2C1 -> 1
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// D0/D1 LPI2C2 -> 2
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#define MICROPY_HW_I2C_INDEX { 1, 2 } |
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#define IOMUX_TABLE_I2C \ |
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{ IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL }, { IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA }, \ |
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{ IOMUXC_GPIO_EMC_19_LPI2C2_SCL }, { IOMUXC_GPIO_EMC_18_LPI2C2_SDA }, |
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#define MICROPY_PY_MACHINE_I2S (1) |
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#define MICROPY_HW_I2S_NUM (1) |
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#define I2S_CLOCK_MUX { 0, kCLOCK_Sai1Mux, kCLOCK_Sai2Mux } |
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#define I2S_CLOCK_PRE_DIV { 0, kCLOCK_Sai1PreDiv, kCLOCK_Sai2PreDiv } |
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#define I2S_CLOCK_DIV { 0, kCLOCK_Sai1Div, kCLOCK_Sai2Div } |
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#define I2S_IOMUXC_GPR_MODE { 0, kIOMUXC_GPR_SAI1MClkOutputDir, kIOMUXC_GPR_SAI2MClkOutputDir } |
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#define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx } |
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#define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx } |
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#define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \ |
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{ \ |
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.hw_id = _hwid, \ |
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.fn = _fn, \ |
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.mode = _mode, \ |
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.name = MP_QSTR_##_pin, \ |
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.iomux = {_iomux}, \ |
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} |
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#define I2S_GPIO_MAP \ |
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{ \ |
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I2S_GPIO(1, MCK, TX, GPIO_EMC_20, IOMUXC_GPIO_EMC_20_SAI1_MCLK), \ |
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I2S_GPIO(1, SCK, RX, GPIO_EMC_19, IOMUXC_GPIO_EMC_19_SAI1_RX_BCLK), \ |
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I2S_GPIO(1, WS, RX, GPIO_EMC_18, IOMUXC_GPIO_EMC_18_SAI1_RX_SYNC), \ |
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I2S_GPIO(1, SD, RX, GPIO_EMC_21, IOMUXC_GPIO_EMC_21_SAI1_RX_DATA00), \ |
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I2S_GPIO(1, SCK, TX, GPIO_EMC_26, IOMUXC_GPIO_EMC_26_SAI1_TX_BCLK), \ |
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I2S_GPIO(1, WS, TX, GPIO_EMC_27, IOMUXC_GPIO_EMC_27_SAI1_TX_SYNC), \ |
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I2S_GPIO(1, SD, TX, GPIO_EMC_25, IOMUXC_GPIO_EMC_25_SAI1_TX_DATA00), \ |
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} |
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#define MICROPY_BOARD_ROOT_POINTERS \ |
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struct _machine_i2s_obj_t *machine_i2s_obj[MICROPY_HW_I2S_NUM]; |
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@ -0,0 +1,9 @@ |
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MCU_SERIES = MIMXRT1015 |
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MCU_VARIANT = MIMXRT1015DAF5A |
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MICROPY_FLOAT_IMPL = single |
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MICROPY_PY_MACHINE_SDCARD = 0 |
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MICROPY_HW_FLASH_TYPE ?= qspi_nor |
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MICROPY_HW_FLASH_SIZE ?= 0x1000000 # 16MB |
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MICROPY_BOOT_BUFFER_SIZE = (32 * 1024) |
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