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stm32: Add support for STM32L452 MCUs.

pull/4907/head
Chris Mason 6 years ago
committed by Damien George
parent
eea61a09c4
commit
64181b5f76
7 changed files with 143 additions and 4 deletions
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  1. 4
      ports/stm32/adc.c
  2. 85
      ports/stm32/boards/stm32l452_af.csv
  3. 34
      ports/stm32/boards/stm32l452xe.ld
  4. 14
      ports/stm32/dac.c
  5. 2
      ports/stm32/dma.c
  6. 2
      ports/stm32/dma.h
  7. 6
      ports/stm32/flashbdev.c

4
ports/stm32/adc.c
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@ -145,7 +145,9 @@
#define VBAT_DIV (4)
#elif defined(STM32H743xx)
#define VBAT_DIV (4)
#elif defined(STM32L432xx) || defined(STM32L475xx) || \
#elif defined(STM32L432xx) || \
defined(STM32L451xx) || defined(STM32L452xx) || \
defined(STM32L462xx) || defined(STM32L475xx) || \
defined(STM32L476xx) || defined(STM32L496xx)
#define VBAT_DIV (3)
#else

85
ports/stm32/boards/stm32l452_af.csv
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@ -0,0 +1,85 @@
Port,,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15,,,
,,SYS_AF,TIM1/TIM2/LPTIM1,I2C4/TIM1/TIM2/TIM3,I2C4/USART2/CAN1/TIM1,I2C1/I2C2/I2C3/I2C4,SPI1/SPI2/I2C4,SPI3/DFSDM/COMP1,USART1/USART2/USART3,UART4/LPUART1/CAN1,CAN1/TSC,CAN1/USB/QUADSPI,,SDMMC1/COMP1/COMP2,SAI1,TIM2/TIM15/TIM16/LPTIM2,EVENTOUT,ADC,COMP,DAC
PortA,PA0,,TIM2_CH1,,,,,,USART2_CTS,UART4_TX,,,,COMP1_OUT,SAI1_EXTCLK,TIM2_ETR,EVENTOUT,ADC12_IN5,COMP1_INM,
PortA,PA1,,TIM2_CH2,,,I2C1_SMBA,SPI1_SCK,,USART2_RTS/USART2_DE,UART4_RX,,,,,,TIM15_CH1N,EVENTOUT,ADC12_IN6,COMP1_INP,
PortA,PA2,,TIM2_CH3,,,,,,USART2_TX,LPUART1_TX,,QUADSPI_BK1_NCS,,COMP2_OUT,,TIM15_CH1,EVENTOUT,ADC12_IN7,COMP2_INM,
PortA,PA3,,TIM2_CH4,,,,,,USART2_RX,LPUART1_RX,,QUADSPI_CLK,,,SAI1_MCLK_A,TIM15_CH2,EVENTOUT,ADC12_IN8,COMP2_INP,
PortA,PA4,,,,,,SPI1_NSS,SPI3_NSS,USART2_CK,,,,,,SAI1_FS_B,LPTIM2_OUT,EVENTOUT,ADC12_IN9,COMP1_INM/COMP2_INM,DAC1_OUT1
PortA,PA5,,TIM2_CH1,TIM2_ETR,,,SPI1_SCK,DFSDM1_CKOUT,,,,,,,,LPTIM2_ETR,EVENTOUT,ADC12_IN10,COMP1_INM/COMP2_INM,
PortA,PA6,,TIM1_BKIN,TIM3_CH1,,,SPI1_MISO,COMP1_OUT,USART3_CTS,LPUART1_CTS,,QUADSPI_BK1_IO3,,TIM1_BKIN_COMP2,,TIM16_CH1,EVENTOUT,ADC12_IN11,,
PortA,PA7,,TIM1_CH1N,TIM3_CH2,,I2C3_SCL,SPI1_MOSI,DFSDM1_DATIN0,,,,QUADSPI_BK1_IO2,,COMP2_OUT,,,EVENTOUT,ADC12_IN12,,
PortA,PA8,MCO,TIM1_CH1,,,,,DFSDM1_CKIN1,USART1_CK,,,,,,SAI1_SCK_A,LPTIM2_OUT,EVENTOUT,,,
PortA,PA9,,TIM1_CH2,,,I2C1_SCL,,DFSDM1_DATIN1,USART1_TX,,,,,,SAI1_FS_A,TIM15_BKIN,EVENTOUT,,,
PortA,PA10,,TIM1_CH3,,,I2C1_SDA,,,USART1_RX,,,USBCRS_SYNC,,,SAI1_SD_A,,EVENTOUT,,,
PortA,PA11,,TIM1_CH4,TIM1_BKIN2,,,SPI1_MISO,COMP1_OUT,USART1_CTS,,CAN1_RX,USBDM,,TIM1_BKIN2_COMP1,,,EVENTOUT,,,
PortA,PA12,,TIM1_ETR,,,,SPI1_MOSI,,USART1_RTS/USART1_DE,,CAN1_TX,USBDP,,,,,EVENTOUT,,,
PortA,PA13,JTMS/SWDIO,IR_OUT,,,,,,,,,USBNOE,,,SAI1_SD_B,,EVENTOUT,,,
PortA,PA14,JTCK/SWCLK,LPTIM1_OUT,,,I2C1_SMBA,I2C4_SMBA,,,,,,,,SAI1_FS_B,,EVENTOUT,,,
PortA,PA15,JTDI,TIM2_CH1,TIM2_ETR,USART2_RX,,SPI1_NSS,SPI3_NSS,USART3_RTS/USART3_DE,UART4_RTS/UART4_DE,TSC_G3_IO1,,,,,,EVENTOUT,,,
PortB,PB0,,TIM1_CH2N,TIM3_CH3,,,SPI1_NSS,DFSDM1_CKIN0,USART3_CK,,,QUADSPI_BK1_IO1,,COMP1_OUT,SAI1_EXTCLK,,EVENTOUT,ADC12_IN15,,
PortB,PB1,,TIM1_CH3N,TIM3_CH4,,,,DFSDM_DATIN0,USART3_RTS/USART3_DE,LPUART1_RTS/LPUART1_DE,,QUADSPI_BK1_IO0,,,,LPTIM2_IN1,EVENTOUT,ADC12_IN16,COMP1_INN,
PortB,PB2,RTC_OUT,LPTIM1_OUT,,,I2C3_SMBA,,DFSDM_CKIN0,,,,,,,,,EVENTOUT,,COMP1_INP,
PortB,PB3,JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCK,USART1_RTS/USART1_DE,,,,,,SAI1_SCK_B,,EVENTOUT,,COMP2_INM,
PortB,PB4,NJTRST,,TIM3_CH1,,I2C3_SDA,SPI1_MISO,SPI3_MISO,USART1_CTS,,TSC_G2_IO1,,,,SAI1_MCLK_B,,EVENTOUT,,COMP2_INP,
PortB,PB5,,LPTIM1_IN1,TIM3_CH2,CAN1_RX,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI,USART1_CK,,TSC_G2_IO2,,,COMP2_OUT,SAI1_SD_B,TIM16_BKIN,EVENTOUT,,,
PortB,PB6,,LPTIM1_ETR,,,I2C1_SCL,I2C4_SCL,,USART1_TX,CAN1_TX,TSC_G2_IO3,,,,SAI1_FS_B,TIM16_CH1N,EVENTOUT,,COMP2_INP,
PortB,PB7,,LPTIM1_IN2,,,I2C1_SDA,I2C4_SDA,,USART1_RX,UART4_CTS,TSC_G2_IO4,,,,,,EVENTOUT,,COMP2_INM,
PortB,PB8,,,,,I2C1_SCL,,,,,CAN1_RX,,,SDMMC1_D4,SAI1_MCLK_A,TIM16_CH1,EVENTOUT,,,
PortB,PB9,,IR_OUT,,,I2C1_SDA,SPI2_NSS,,,,CAN1_TX,,,SDMMC1_D5,SAI1_FS_A,,EVENTOUT,,,
PortB,PB10,,TIM2_CH3,,I2C4_SCL,I2C2_SCL,SPI2_SCK,,USART3_TX,LPUART1_RX,TSC_SYNC,QUADSPI_CLK,,COMP1_OUT,SAI1_SCK_A,,EVENTOUT,,,
PortB,PB11,,TIM2_CH4,,I2C4_SDA,I2C2_SDA,,,USART3_RX,LPUART1_TX,,QUADSPI_NCS,,COMP2_OUT,,,EVENTOUT,,,
PortB,PB12,,TIM1_BKIN,,TIM1_BKIN_COMP2,I2C2_SMBA,SPI2_NSS,DFSDM_DATIN1,USART3_CK,LPUART1_RTS/LPUART1_DE,TSC_G1_IO1,CAN1_RX,,,SAI1_FS_A,TIM15_BKIN,EVENTOUT,,,
PortB,PB13,,TIM1_CH1N,,,I2C2_SCL,SPI2_SCK,DFSDM_CKIN1,USART3_CTS,LPUART1_CTS,TSC_G1_IO2,CAN1_TX,,,SAI1_SCK_A,TIM15_CH1N,EVENTOUT,,,
PortB,PB14,,TIM1_CH2N,,,I2C2_SDA,SPI2_MISO,DFSDM_DATIN2,USART3_RTS_DE,,TSC_G1_IO3,,,,SAI1_MCLK_A,TIM15_CH1,EVENTOUT,,,
PortB,PB15,RTC_REFIN,TIM1_CH3N,,,,SPI2_MOSI,DFSDM_CKIN2,,,TSC_G1_IO4,,,,SAI1_SD_A,TIM15_CH2,EVENTOUT,,,
PortC,PC0,,LPTIM1_IN1,I2C4_SCL,,I2C3_SCL,,,,LPUART1_RX,,,,,,LPTIM2_IN1,EVENTOUT,ADC123_IN1,,
PortC,PC1,TRACED0,LPTIM1_OUT,I2C4_SDA,,I2C3_SDA,,,,LPUART1_TX,,,,,,,EVENTOUT,ADC123_IN2,,
PortC,PC2,,LPTIM1_IN2,,,,SPI2_MISO,DFSDM_CKOUT,,,,,,,,,EVENTOUT,ADC123_IN3,,
PortC,PC3,,LPTIM1_ETR,,,,SPI2_MOSI,,,,,,,,SAI1_SD_A,LPTIM2_ETR,EVENTOUT,ADC123_IN4,,
PortC,PC4,,,,,,,,USART3_TX,,,,,,,,EVENTOUT,ADC12_IN13,COMP1_INM,
PortC,PC5,,,,,,,,USART3_RX,,,,,,,,EVENTOUT,ADC12_IN14,COMP1_INP,
PortC,PC6,,,TIM3_CH1,,,,DFSDM_CKIN3,,,TSC_G4_IO1,,,SDMMC1_D6,,,EVENTOUT,,,
PortC,PC7,,,TIM3_CH2,,,,DFSDM_DATIN3,,,TSC_G4_IO2,,,SDMMC1_D7,,,EVENTOUT,,,
PortC,PC8,,,TIM3_CH3,,,,,,,TSC_G4_IO3,,,SDMMC1_D0,,,EVENTOUT,,,
PortC,PC9,,,TIM3_CH4,,,,,,,TSC_G4_IO4,USBNOE,,SDMMC1_D1,,,EVENTOUT,,,
PortC,PC10,TRACED1,,,,,,SPI3_SCK,USART3_TX,UART4_TX,TSC_G3_IO2,,,SDMMC1_D2,,,EVENTOUT,,,
PortC,PC11,,,,,,,SPI3_MISO,USART3_RX,UART4_RX,TSC_G3_IO3,,,SDMMC1_D3,,,EVENTOUT,,,
PortC,PC12,TRACED3,,,,,,SPI3_MOSI,USART3_CK,,TSC_G3_IO4,,,SDMMC1_CK,,,EVENTOUT,,,
PortC,PC13,,,,,,,,,,,,,,,,EVENTOUT,,,
PortC,PC14,,,,,,,,,,,,,,,,EVENTOUT,,,
PortC,PC15,,,,,,,,,,,,,,,,EVENTOUT,,,
PortD,PD0,,,,,,SPI2_NSS,,,,CAN1_RX,,,,,,EVENTOUT,,,
PortD,PD1,,,,,,SPI2_SCK,,,,CAN1_TX,,,,,,EVENTOUT,,,
PortD,PD2,TRACED2,,TIM3_ETR,,,,,USART3_RTS/USART3_DE,,TSC_SYNC,,,SDMMC1_CMD,,,EVENTOUT,,,
PortD,PD3,,,,,,SPI2_MISO,DFSDM_DATIN0,USART2_CTS,,,QUADSPI_BK2_NCS,,,,,EVENTOUT,,,
PortD,PD4,,,,,,SPI2_MOSI,DFSDM_CKIN0,USART2_RTS/USART2_DE,,,QUADSPI_BK2_IO0,,,,,EVENTOUT,,,
PortD,PD5,,,,,,,,USART2_TX,,,QUADSPI_BK2_IO1,,,,,EVENTOUT,,,
PortD,PD6,,,,,,,DFSDM_DATIN1,USART2_RX,,,QUADSPI_BK2_IO2,,,SAI1_SD_A,,EVENTOUT,,,
PortD,PD7,,,,,,,DFSDM_CKIN1,USART2_CK,,,QUADSPI_BK2_IO3,,,,,EVENTOUT,,,
PortD,PD8,,,,,,,,USART3_TX,,,,,,,,EVENTOUT,,,
PortD,PD9,,,,,,,,USART3_RX,,,,,,,,EVENTOUT,,,
PortD,PD10,,,,,,,,USART3_CK,,TSC_G6_IO1,,,,,,EVENTOUT,,,
PortD,PD11,,,,,I2C4_SMBA,,,USART3_CTS,,TSC_G6_IO2,,,,,LPTIM2_ETR,EVENTOUT,,,
PortD,PD12,,,,,I2C4_SCL,,,USART3_RTS/USART3_DE,,TSC_G6_IO3,,,,,LPTIM2_IN1,EVENTOUT,,,
PortD,PD13,,,,,I2C4_SDA,,,,,TSC_G6_IO4,,,,,LPTIM2_OUT,EVENTOUT,,,
PortD,PD14,,,,,,,,,,,,,,,,EVENTOUT,,,
PortD,PD15,,,,,,,,,,,,,,,,EVENTOUT,,,
PortE,PE0,,,,,,,,,,,,,,,TIM16_CH1,EVENTOUT,,,
PortE,PE1,,,,,,,,,,,,,,,,EVENTOUT,,,
PortE,PE2,TRACECLK,,TIM3_ETR,,,,,,,TSC_G7_IO1,,,,SAI1_MCLK_A,,EVENTOUT,,,
PortE,PE3,TRACED0,,TIM3_CH1,,,,,,,TSC_G7_IO2,,,,SAI1_SD_B,,EVENTOUT,,,
PortE,PE4,TRACED1,,TIM3_CH2,,,,DFSDM_DATIN3,,,TSC_G7_IO3,,,,SAI1_FS_A,,EVENTOUT,,,
PortE,PE5,TRACED2,,TIM3_CH3,,,,DFSDM_CKIN3,,,TSC_G7_IO4,,,,SAI1_SCK_A,,EVENTOUT,,,
PortE,PE6,TRACED3,,TIM3_CH4,,,,,,,,,,,SAI1_SD_A,,EVENTOUT,,,
PortE,PE7,,TIM1_ETR,,,,,DFSDM_DATIN2,,,,,,,SAI1_SD_B,,EVENTOUT,,,
PortE,PE8,,TIM1_CH1N,,,,,DFSDM_CKIN2,,,,,,,SAI1_SCK_B,,EVENTOUT,,,
PortE,PE9,,TIM1_CH1,,,,,DFSDM_CKOUT,,,,,,,SAI1_FS_B,,EVENTOUT,,,
PortE,PE10,,TIM1_CH2N,,,,,,,,TSC_G5_IO1,QUADSPI_CLK,,,SAI1_MCLK_B,,EVENTOUT,,,
PortE,PE11,,TIM1_CH2,,,,,,,,TSC_G5_IO2,QUADSPI_BK1_NCS,,,,,EVENTOUT,,,
PortE,PE12,,TIM1_CH3N,,,,SPI1_NSS,,,,TSC_G5_IO3,QUADSPI_BK1_IO0,,,,,EVENTOUT,,,
PortE,PE13,,TIM1_CH3,,,,SPI1_SCK,,,,TSC_G5_IO4,QUADSPI_BK1_IO1,,,,,EVENTOUT,,,
PortE,PE14,,TIM1_CH4,TIM1_BKIN2,TIM1_BKIN2_COMP2,,SPI1_MISO,,,,,QUADSPI_BK1_IO2,,,,,EVENTOUT,,,
PortE,PE15,,TIM1_BKIN,,TIM1_BKIN_COMP1,,SPI1_MOSI,,,,,QUADSPI_BK1_IO3,,,,,EVENTOUT,,,
PortH,PH0,,,,,,,,,,,,,,,,EVENTOUT,,,
PortH,PH1,,,,,,,,,,,,,,,,EVENTOUT,,,
PortH,PH3,,,,,,,,,,,,,,,,,,,
Can't render this file because it has a wrong number of fields in line 19.

34
ports/stm32/boards/stm32l452xe.ld
View File

@ -0,0 +1,34 @@
/*
GNU linker script for STM32L452XE
*/
/* Specify the memory areas */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 384K /* sectors 0-191 */
FLASH_FS (r) : ORIGIN = 0x08060000, LENGTH = 128K /* sectors 192-255 */
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 160K /* SRAM1, 128K + SRAM2, 32K */
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_heap_size = 16K;
/* Define the stack. The stack is full descending so begins just above last byte of RAM,
or bottom of FS cache.. Note that EABI requires the stack to be 8-byte aligned for a call. */
/* RAM extents for the garbage collector */
_ram_start = ORIGIN(RAM);
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
_ram_fs_cache_end = _ram_end;
_ram_fs_cache_start = _ram_fs_cache_end - 2K; /* fs cache = 2K */
_estack = _ram_fs_cache_start - _estack_reserve;
_sstack = _estack - 16K; /* stack = 16K */
_heap_start = _ebss; /* heap starts just after statically allocated memory */
_heap_end = _sstack; /* bss + heap = 142K, tunable by adjusting stack size */
_flash_fs_start = ORIGIN(FLASH_FS);
_flash_fs_end = ORIGIN(FLASH_FS) + LENGTH(FLASH_FS);

14
ports/stm32/dac.c
View File

@ -148,8 +148,10 @@ STATIC void dac_set_value(uint32_t dac_channel, uint32_t align, uint32_t value)
uint32_t base;
if (dac_channel == DAC_CHANNEL_1) {
base = (uint32_t)&DAC->DHR12R1;
#if !defined(STM32L452xx)
} else {
base = (uint32_t)&DAC->DHR12R2;
#endif
}
*(volatile uint32_t*)(base + align) = value;
}
@ -169,8 +171,10 @@ STATIC void dac_start_dma(uint32_t dac_channel, const dma_descr_t *dma_descr, ui
uint32_t base;
if (dac_channel == DAC_CHANNEL_1) {
base = (uint32_t)&DAC->DHR12R1;
#if !defined(STM32L452xx)
} else {
base = (uint32_t)&DAC->DHR12R2;
#endif
}
dma_nohal_deinit(dma_descr);
@ -185,7 +189,7 @@ STATIC void dac_start_dma(uint32_t dac_channel, const dma_descr_t *dma_descr, ui
typedef struct _pyb_dac_obj_t {
mp_obj_base_t base;
uint8_t dac_channel; // DAC_CHANNEL_1 or DAC_CHANNEL_2
uint8_t dac_channel; // DAC_CHANNEL_1 or DAC_CHANNEL_2. STM32L452 only has CHANNEL_1.
uint8_t bits; // 8 or 12
uint8_t outbuf_single;
uint8_t outbuf_waveform;
@ -200,8 +204,10 @@ STATIC void pyb_dac_reconfigure(pyb_dac_obj_t *self, uint32_t cr, uint32_t outbu
const dma_descr_t *tx_dma_descr;
if (self->dac_channel == DAC_CHANNEL_1) {
tx_dma_descr = &dma_DAC_1_TX;
#if !defined(STM32L452xx)
} else {
tx_dma_descr = &dma_DAC_2_TX;
#endif
}
dma_nohal_deinit(tx_dma_descr);
dac_config_channel(self->dac_channel, cr, outbuf);
@ -234,8 +240,10 @@ STATIC mp_obj_t pyb_dac_init_helper(pyb_dac_obj_t *self, size_t n_args, const mp
mp_hal_pin_obj_t pin;
if (self->dac_channel == DAC_CHANNEL_1) {
pin = pin_A4;
#if !defined(STM32L452xx)
} else {
pin = pin_A5;
#endif
}
mp_hal_pin_config(pin, MP_HAL_PIN_MODE_ANALOG, MP_HAL_PIN_PULL_NONE, 0);
@ -306,8 +314,10 @@ STATIC mp_obj_t pyb_dac_make_new(const mp_obj_type_t *type, size_t n_args, size_
uint32_t dac_channel;
if (dac_id == 1) {
dac_channel = DAC_CHANNEL_1;
#if !defined(STM32L452xx)
} else if (dac_id == 2) {
dac_channel = DAC_CHANNEL_2;
#endif
} else {
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "DAC(%d) doesn't exist", dac_id));
}
@ -446,8 +456,10 @@ mp_obj_t pyb_dac_write_timed(size_t n_args, const mp_obj_t *pos_args, mp_map_t *
const dma_descr_t *tx_dma_descr;
if (self->dac_channel == DAC_CHANNEL_1) {
tx_dma_descr = &dma_DAC_1_TX;
#if !defined(STM32L452xx)
} else {
tx_dma_descr = &dma_DAC_2_TX;
#endif
}
uint32_t align;

2
ports/stm32/dma.c
View File

@ -387,7 +387,9 @@ const dma_descr_t dma_I2C_1_TX = { DMA1_Channel6, DMA_REQUEST_3, dma_id_5, &dm
const dma_descr_t dma_I2C_1_RX = { DMA1_Channel7, DMA_REQUEST_3, dma_id_6, &dma_init_struct_spi_i2c };
// DMA2 streams
const dma_descr_t dma_I2C_4_RX = { DMA2_Channel1, DMA_REQUEST_0, dma_id_0, &dma_init_struct_spi_i2c };
const dma_descr_t dma_SPI_3_RX = { DMA2_Channel1, DMA_REQUEST_3, dma_id_7, &dma_init_struct_spi_i2c };
const dma_descr_t dma_I2C_4_TX = { DMA2_Channel2, DMA_REQUEST_0, dma_id_1, &dma_init_struct_spi_i2c };
const dma_descr_t dma_SPI_3_TX = { DMA2_Channel2, DMA_REQUEST_3, dma_id_8, &dma_init_struct_spi_i2c };
/* not preferred streams
const dma_descr_t dma_ADC_1_RX = { DMA2_Channel3, DMA_REQUEST_0, dma_id_9, NULL };

2
ports/stm32/dma.h
View File

@ -93,6 +93,8 @@ extern const dma_descr_t dma_I2C_1_RX;
extern const dma_descr_t dma_SPI_3_RX;
extern const dma_descr_t dma_SPI_3_TX;
extern const dma_descr_t dma_SDIO_0;
extern const dma_descr_t dma_I2C_4_TX;
extern const dma_descr_t dma_I2C_4_RX;
#endif

6
ports/stm32/flashbdev.c
View File

@ -103,9 +103,11 @@ STATIC byte flash_cache_mem[0x4000] __attribute__((aligned(4))); // 16k
#define FLASH_MEM_SEG1_START_ADDR (0x08020000) // sector 1
#define FLASH_MEM_SEG1_NUM_BLOCKS (256) // Sector 1: 128k / 512b = 256 blocks
#elif defined(STM32L432xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L496xx)
#elif defined(STM32L432xx) || \
defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L496xx)
// The STM32L475/6 doesn't have CCRAM, so we use the 32K SRAM2 for this, although
// The STM32L4xx doesn't have CCRAM, so we use SRAM2 for this, although
// actual location and size is defined by the linker script.
extern uint8_t _flash_fs_start;
extern uint8_t _flash_fs_end;

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