From a542c6d7e0340e5ff5364426131bdbd69a64e746 Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 29 Jan 2020 16:49:13 +1100 Subject: [PATCH] stm32/powerctrl: For F7, allow PLLM!=HSE when setting PLLSAI to 48MHz. PLLM is shared among all PLL blocks on F7 MCUs, and this calculation to configure PLLSAI to have 48MHz on the P output previously assumed that PLLM is equal to HSE (eg PLLM=25 for HSE=25MHz). This commit relaxes this assumption to allow other values of PLLM. --- ports/stm32/powerctrl.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/ports/stm32/powerctrl.c b/ports/stm32/powerctrl.c index dfd9e8262d..1d1792c386 100644 --- a/ports/stm32/powerctrl.c +++ b/ports/stm32/powerctrl.c @@ -94,9 +94,11 @@ int powerctrl_rcc_clock_config_pll(RCC_ClkInitTypeDef *rcc_init, uint32_t sysclk if (need_pllsai) { // Configure PLLSAI at 48MHz for those peripherals that need this freq - const uint32_t pllsain = 192; + // (calculation assumes it can get an integral value of PLLSAIN) + const uint32_t pllm = (RCC->PLLCFGR >> RCC_PLLCFGR_PLLM_Pos) & 0x3f; const uint32_t pllsaip = 4; const uint32_t pllsaiq = 2; + const uint32_t pllsain = 48 * pllsaip * pllm / (HSE_VALUE / 1000000); RCC->PLLSAICFGR = pllsaiq << RCC_PLLSAICFGR_PLLSAIQ_Pos | (pllsaip / 2 - 1) << RCC_PLLSAICFGR_PLLSAIP_Pos | pllsain << RCC_PLLSAICFGR_PLLSAIN_Pos;