|
@ -33,7 +33,7 @@ |
|
|
#include "samd_soc.h" |
|
|
#include "samd_soc.h" |
|
|
|
|
|
|
|
|
static uint32_t cpu_freq = CPU_FREQ; |
|
|
static uint32_t cpu_freq = CPU_FREQ; |
|
|
static uint32_t apb_freq = APB_FREQ; |
|
|
static uint32_t peripheral_freq = DFLL48M_FREQ; |
|
|
static uint32_t dfll48m_calibration; |
|
|
static uint32_t dfll48m_calibration; |
|
|
|
|
|
|
|
|
int sercom_gclk_id[] = { |
|
|
int sercom_gclk_id[] = { |
|
@ -49,8 +49,8 @@ uint32_t get_cpu_freq(void) { |
|
|
return cpu_freq; |
|
|
return cpu_freq; |
|
|
} |
|
|
} |
|
|
|
|
|
|
|
|
uint32_t get_apb_freq(void) { |
|
|
uint32_t get_peripheral_freq(void) { |
|
|
return apb_freq; |
|
|
return peripheral_freq; |
|
|
} |
|
|
} |
|
|
|
|
|
|
|
|
void set_cpu_freq(uint32_t cpu_freq_arg) { |
|
|
void set_cpu_freq(uint32_t cpu_freq_arg) { |
|
@ -181,7 +181,7 @@ void init_clocks(uint32_t cpu_freq) { |
|
|
while (GCLK->PCHCTRL[0].bit.CHEN == 0) { |
|
|
while (GCLK->PCHCTRL[0].bit.CHEN == 0) { |
|
|
} |
|
|
} |
|
|
// Step 2: Set the multiplication values. The offset of 16384 to the freq is for rounding.
|
|
|
// Step 2: Set the multiplication values. The offset of 16384 to the freq is for rounding.
|
|
|
OSCCTRL->DFLLMUL.reg = OSCCTRL_DFLLMUL_MUL((APB_FREQ + DPLLx_REF_FREQ / 2) / DPLLx_REF_FREQ) | |
|
|
OSCCTRL->DFLLMUL.reg = OSCCTRL_DFLLMUL_MUL((DFLL48M_FREQ + DPLLx_REF_FREQ / 2) / DPLLx_REF_FREQ) | |
|
|
OSCCTRL_DFLLMUL_FSTEP(1) | OSCCTRL_DFLLMUL_CSTEP(1); |
|
|
OSCCTRL_DFLLMUL_FSTEP(1) | OSCCTRL_DFLLMUL_CSTEP(1); |
|
|
while (OSCCTRL->DFLLSYNC.bit.DFLLMUL == 1) { |
|
|
while (OSCCTRL->DFLLSYNC.bit.DFLLMUL == 1) { |
|
|
} |
|
|
} |
|
@ -200,7 +200,7 @@ void init_clocks(uint32_t cpu_freq) { |
|
|
#else // MICROPY_HW_XOSC32K
|
|
|
#else // MICROPY_HW_XOSC32K
|
|
|
|
|
|
|
|
|
// Derive GCLK1 from DFLL48M at DPLL0_REF_FREQ as defined in mpconfigboard.h (e.g. 32768 Hz)
|
|
|
// Derive GCLK1 from DFLL48M at DPLL0_REF_FREQ as defined in mpconfigboard.h (e.g. 32768 Hz)
|
|
|
GCLK->GENCTRL[1].reg = ((APB_FREQ + DPLLx_REF_FREQ / 2) / DPLLx_REF_FREQ) << GCLK_GENCTRL_DIV_Pos |
|
|
GCLK->GENCTRL[1].reg = ((DFLL48M_FREQ + DPLLx_REF_FREQ / 2) / DPLLx_REF_FREQ) << GCLK_GENCTRL_DIV_Pos |
|
|
| GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL; |
|
|
| GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL; |
|
|
while (GCLK->SYNCBUSY.bit.GENCTRL1) { |
|
|
while (GCLK->SYNCBUSY.bit.GENCTRL1) { |
|
|
} |
|
|
} |
|
@ -236,7 +236,7 @@ void init_clocks(uint32_t cpu_freq) { |
|
|
|
|
|
|
|
|
set_cpu_freq(cpu_freq); |
|
|
set_cpu_freq(cpu_freq); |
|
|
|
|
|
|
|
|
apb_freq = APB_FREQ; // To be changed if CPU_FREQ < 48M
|
|
|
peripheral_freq = DFLL48M_FREQ; // To be changed if CPU_FREQ < 48M
|
|
|
|
|
|
|
|
|
// Setup GCLK2 for DPLL1 output (48 MHz)
|
|
|
// Setup GCLK2 for DPLL1 output (48 MHz)
|
|
|
GCLK->GENCTRL[2].reg = GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL; |
|
|
GCLK->GENCTRL[2].reg = GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL; |
|
|