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214 lines
5.7 KiB
214 lines
5.7 KiB
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2019, Michael Neuling, IBM Corporation.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "py/mpstate.h"
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#if MICROPY_NLR_POWERPC
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#undef nlr_push
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// Saving all ABI non-vol registers here
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#ifdef __LP64__
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unsigned int nlr_push(nlr_buf_t *nlr) {
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__asm__ volatile (
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"li 4, 0x4eed ; " // Store canary
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"std 4, 0x00(%0) ;"
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"std 0, 0x08(%0) ;"
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"std 1, 0x10(%0) ;"
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"std 2, 0x18(%0) ;"
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"std 14, 0x20(%0) ;"
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"std 15, 0x28(%0) ;"
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"std 16, 0x30(%0) ;"
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"std 17, 0x38(%0) ;"
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"std 18, 0x40(%0) ;"
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"std 19, 0x48(%0) ;"
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"std 20, 0x50(%0) ;"
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"std 21, 0x58(%0) ;"
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"std 22, 0x60(%0) ;"
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"std 23, 0x68(%0) ;"
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"std 24, 0x70(%0) ;"
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"std 25, 0x78(%0) ;"
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"std 26, 0x80(%0) ;"
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"std 27, 0x88(%0) ;"
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"std 28, 0x90(%0) ;"
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"std 29, 0x98(%0) ;"
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"std 30, 0xA0(%0) ;"
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"std 31, 0xA8(%0) ;"
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"mfcr 4 ; "
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"std 4, 0xB0(%0) ;"
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"mflr 4 ;"
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"std 4, 0xB8(%0) ;"
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"li 4, nlr_push_tail@l ;"
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"oris 4, 4, nlr_push_tail@h ;"
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"mtctr 4 ;"
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"mr 3, %1 ; "
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"bctr ;"
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:
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: "r" (&nlr->regs), "r" (nlr)
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:
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);
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return 0;
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}
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NORETURN void nlr_jump(void *val) {
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MP_NLR_JUMP_HEAD(val, top)
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__asm__ volatile (
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"ld 3, 0x0(%0) ;"
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"cmpdi 3, 0x4eed ; " // Check canary
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"bne . ; "
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"ld 0, 0x08(%0) ;"
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"ld 1, 0x10(%0) ;"
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"ld 2, 0x18(%0) ;"
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"ld 14, 0x20(%0) ;"
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"ld 15, 0x28(%0) ;"
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"ld 16, 0x30(%0) ;"
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"ld 17, 0x38(%0) ;"
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"ld 18, 0x40(%0) ;"
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"ld 19, 0x48(%0) ;"
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"ld 20, 0x50(%0) ;"
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"ld 21, 0x58(%0) ;"
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"ld 22, 0x60(%0) ;"
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"ld 23, 0x68(%0) ;"
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"ld 24, 0x70(%0) ;"
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"ld 25, 0x78(%0) ;"
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"ld 26, 0x80(%0) ;"
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"ld 27, 0x88(%0) ;"
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"ld 28, 0x90(%0) ;"
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"ld 29, 0x98(%0) ;"
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"ld 30, 0xA0(%0) ;"
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"ld 31, 0xA8(%0) ;"
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"ld 3, 0xB0(%0) ;"
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"mtcr 3 ;"
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"ld 3, 0xB8(%0) ;"
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"mtlr 3 ; "
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"li 3, 1;"
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"blr ;"
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:
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: "r" (&top->regs)
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: "memory"
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);
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MP_UNREACHABLE;
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}
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#else
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// Saving all ABI non-vol registers here
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unsigned int nlr_push(nlr_buf_t *nlr) {
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__asm__ volatile (
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"li 4, 0x4eed ; " // Store canary
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"stw 4, 0x00(%0) ;"
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"stw 0, 0x04(%0) ;"
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"stw 1, 0x08(%0) ;"
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"stw 2, 0x0c(%0) ;"
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"stw 14, 0x10(%0) ;"
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"stw 15, 0x14(%0) ;"
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"stw 16, 0x18(%0) ;"
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"stw 17, 0x1c(%0) ;"
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"stw 18, 0x20(%0) ;"
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"stw 19, 0x24(%0) ;"
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"stw 20, 0x28(%0) ;"
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"stw 21, 0x2c(%0) ;"
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"stw 22, 0x30(%0) ;"
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"stw 23, 0x34(%0) ;"
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"stw 24, 0x38(%0) ;"
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"stw 25, 0x3c(%0) ;"
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"stw 26, 0x40(%0) ;"
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"stw 27, 0x44(%0) ;"
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"stw 28, 0x48(%0) ;"
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"stw 29, 0x4c(%0) ;"
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"stw 30, 0x50(%0) ;"
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"stw 31, 0x54(%0) ;"
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"mfcr 4 ; "
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"stw 4, 0x58(%0) ;"
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"mflr 4 ;"
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"stw 4, 0x5c(%0) ;"
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"li 4, nlr_push_tail@l ;"
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"oris 4, 4, nlr_push_tail@h ;"
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"mtctr 4 ;"
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"mr 3, %1 ; "
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"bctr ;"
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:
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: "r" (&nlr->regs), "r" (nlr)
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:
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);
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return 0;
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}
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NORETURN void nlr_jump(void *val) {
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MP_NLR_JUMP_HEAD(val, top)
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__asm__ volatile (
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"l 3, 0x0(%0) ;"
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"cmpdi 3, 0x4eed ; " // Check canary
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"bne . ; "
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"l 0, 0x04(%0) ;"
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"l 1, 0x08(%0) ;"
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"l 2, 0x0c(%0) ;"
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"l 14, 0x10(%0) ;"
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"l 15, 0x14(%0) ;"
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"l 16, 0x18(%0) ;"
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"l 17, 0x1c(%0) ;"
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"l 18, 0x20(%0) ;"
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"l 19, 0x24(%0) ;"
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"l 20, 0x28(%0) ;"
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"l 21, 0x2c(%0) ;"
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"l 22, 0x30(%0) ;"
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"l 23, 0x34(%0) ;"
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"l 24, 0x38(%0) ;"
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"l 25, 0x3c(%0) ;"
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"l 26, 0x40(%0) ;"
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"l 27, 0x44(%0) ;"
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"l 28, 0x48(%0) ;"
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"l 29, 0x4c(%0) ;"
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"l 30, 0x50(%0) ;"
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"l 31, 0x54(%0) ;"
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"l 3, 0x58(%0) ;"
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"mtcr 3 ;"
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"l 3, 0x5c(%0) ;"
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"mtlr 3 ; "
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"li 3, 1;"
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"blr ;"
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:
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: "r" (&top->regs)
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: "memory"
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);
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MP_UNREACHABLE;
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}
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#endif // __LP64__
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#endif // MICROPY_NLR_POWERPC
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