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372 lines
11 KiB
372 lines
11 KiB
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2014 Fabian Vogt
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* Copyright (c) 2013, 2014 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdio.h>
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#include <assert.h>
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#include <string.h>
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#include "py/mpconfig.h"
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// wrapper around everything in this file
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#if MICROPY_EMIT_ARM
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#include "py/asmarm.h"
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#define SIGNED_FIT24(x) (((x) & 0xff800000) == 0) || (((x) & 0xff000000) == 0xff000000)
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// Insert word into instruction flow
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STATIC void emit(asm_arm_t *as, uint op) {
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uint8_t *c = mp_asm_base_get_cur_to_write_bytes(&as->base, 4);
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if (c != NULL) {
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*(uint32_t *)c = op;
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}
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}
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// Insert word into instruction flow, add "ALWAYS" condition code
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STATIC void emit_al(asm_arm_t *as, uint op) {
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emit(as, op | ASM_ARM_CC_AL);
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}
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// Basic instructions without condition code
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STATIC uint asm_arm_op_push(uint reglist) {
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// stmfd sp!, {reglist}
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return 0x92d0000 | (reglist & 0xFFFF);
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}
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STATIC uint asm_arm_op_pop(uint reglist) {
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// ldmfd sp!, {reglist}
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return 0x8bd0000 | (reglist & 0xFFFF);
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}
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STATIC uint asm_arm_op_mov_reg(uint rd, uint rn) {
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// mov rd, rn
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return 0x1a00000 | (rd << 12) | rn;
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}
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STATIC uint asm_arm_op_mov_imm(uint rd, uint imm) {
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// mov rd, #imm
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return 0x3a00000 | (rd << 12) | imm;
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}
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STATIC uint asm_arm_op_mvn_imm(uint rd, uint imm) {
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// mvn rd, #imm
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return 0x3e00000 | (rd << 12) | imm;
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}
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STATIC uint asm_arm_op_add_imm(uint rd, uint rn, uint imm) {
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// add rd, rn, #imm
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return 0x2800000 | (rn << 16) | (rd << 12) | (imm & 0xFF);
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}
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STATIC uint asm_arm_op_add_reg(uint rd, uint rn, uint rm) {
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// add rd, rn, rm
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return 0x0800000 | (rn << 16) | (rd << 12) | rm;
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}
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STATIC uint asm_arm_op_sub_imm(uint rd, uint rn, uint imm) {
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// sub rd, rn, #imm
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return 0x2400000 | (rn << 16) | (rd << 12) | (imm & 0xFF);
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}
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STATIC uint asm_arm_op_sub_reg(uint rd, uint rn, uint rm) {
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// sub rd, rn, rm
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return 0x0400000 | (rn << 16) | (rd << 12) | rm;
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}
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STATIC uint asm_arm_op_mul_reg(uint rd, uint rm, uint rs) {
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// mul rd, rm, rs
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assert(rd != rm);
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return 0x0000090 | (rd << 16) | (rs << 8) | rm;
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}
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STATIC uint asm_arm_op_and_reg(uint rd, uint rn, uint rm) {
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// and rd, rn, rm
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return 0x0000000 | (rn << 16) | (rd << 12) | rm;
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}
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STATIC uint asm_arm_op_eor_reg(uint rd, uint rn, uint rm) {
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// eor rd, rn, rm
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return 0x0200000 | (rn << 16) | (rd << 12) | rm;
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}
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STATIC uint asm_arm_op_orr_reg(uint rd, uint rn, uint rm) {
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// orr rd, rn, rm
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return 0x1800000 | (rn << 16) | (rd << 12) | rm;
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}
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void asm_arm_bkpt(asm_arm_t *as) {
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// bkpt #0
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emit_al(as, 0x1200070);
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}
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// locals:
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// - stored on the stack in ascending order
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// - numbered 0 through num_locals-1
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// - SP points to first local
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//
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// | SP
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// v
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// l0 l1 l2 ... l(n-1)
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// ^ ^
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// | low address | high address in RAM
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void asm_arm_entry(asm_arm_t *as, int num_locals) {
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assert(num_locals >= 0);
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as->stack_adjust = 0;
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as->push_reglist = 1 << ASM_ARM_REG_R1
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| 1 << ASM_ARM_REG_R2
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| 1 << ASM_ARM_REG_R3
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| 1 << ASM_ARM_REG_R4
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| 1 << ASM_ARM_REG_R5
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| 1 << ASM_ARM_REG_R6
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| 1 << ASM_ARM_REG_R7
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| 1 << ASM_ARM_REG_R8;
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// Only adjust the stack if there are more locals than usable registers
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if (num_locals > 3) {
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as->stack_adjust = num_locals * 4;
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// Align stack to 8 bytes
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if (num_locals & 1) {
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as->stack_adjust += 4;
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}
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}
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emit_al(as, asm_arm_op_push(as->push_reglist | 1 << ASM_ARM_REG_LR));
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if (as->stack_adjust > 0) {
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emit_al(as, asm_arm_op_sub_imm(ASM_ARM_REG_SP, ASM_ARM_REG_SP, as->stack_adjust));
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}
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}
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void asm_arm_exit(asm_arm_t *as) {
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if (as->stack_adjust > 0) {
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emit_al(as, asm_arm_op_add_imm(ASM_ARM_REG_SP, ASM_ARM_REG_SP, as->stack_adjust));
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}
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emit_al(as, asm_arm_op_pop(as->push_reglist | (1 << ASM_ARM_REG_PC)));
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}
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void asm_arm_push(asm_arm_t *as, uint reglist) {
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emit_al(as, asm_arm_op_push(reglist));
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}
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void asm_arm_pop(asm_arm_t *as, uint reglist) {
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emit_al(as, asm_arm_op_pop(reglist));
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}
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void asm_arm_mov_reg_reg(asm_arm_t *as, uint reg_dest, uint reg_src) {
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emit_al(as, asm_arm_op_mov_reg(reg_dest, reg_src));
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}
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size_t asm_arm_mov_reg_i32(asm_arm_t *as, uint rd, int imm) {
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// Insert immediate into code and jump over it
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emit_al(as, 0x59f0000 | (rd << 12)); // ldr rd, [pc]
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emit_al(as, 0xa000000); // b pc
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size_t loc = mp_asm_base_get_code_pos(&as->base);
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emit(as, imm);
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return loc;
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}
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void asm_arm_mov_reg_i32_optimised(asm_arm_t *as, uint rd, int imm) {
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// TODO: There are more variants of immediate values
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if ((imm & 0xFF) == imm) {
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emit_al(as, asm_arm_op_mov_imm(rd, imm));
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} else if (imm < 0 && imm >= -256) {
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// mvn is "move not", not "move negative"
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emit_al(as, asm_arm_op_mvn_imm(rd, ~imm));
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} else {
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asm_arm_mov_reg_i32(as, rd, imm);
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}
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}
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void asm_arm_mov_local_reg(asm_arm_t *as, int local_num, uint rd) {
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// str rd, [sp, #local_num*4]
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emit_al(as, 0x58d0000 | (rd << 12) | (local_num << 2));
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}
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void asm_arm_mov_reg_local(asm_arm_t *as, uint rd, int local_num) {
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// ldr rd, [sp, #local_num*4]
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emit_al(as, 0x59d0000 | (rd << 12) | (local_num << 2));
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}
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void asm_arm_cmp_reg_i8(asm_arm_t *as, uint rd, int imm) {
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// cmp rd, #imm
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emit_al(as, 0x3500000 | (rd << 16) | (imm & 0xFF));
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}
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void asm_arm_cmp_reg_reg(asm_arm_t *as, uint rd, uint rn) {
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// cmp rd, rn
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emit_al(as, 0x1500000 | (rd << 16) | rn);
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}
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void asm_arm_setcc_reg(asm_arm_t *as, uint rd, uint cond) {
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emit(as, asm_arm_op_mov_imm(rd, 1) | cond); // movCOND rd, #1
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emit(as, asm_arm_op_mov_imm(rd, 0) | (cond ^ (1 << 28))); // mov!COND rd, #0
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}
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void asm_arm_add_reg_reg_reg(asm_arm_t *as, uint rd, uint rn, uint rm) {
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// add rd, rn, rm
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emit_al(as, asm_arm_op_add_reg(rd, rn, rm));
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}
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void asm_arm_sub_reg_reg_reg(asm_arm_t *as, uint rd, uint rn, uint rm) {
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// sub rd, rn, rm
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emit_al(as, asm_arm_op_sub_reg(rd, rn, rm));
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}
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void asm_arm_mul_reg_reg_reg(asm_arm_t *as, uint rd, uint rs, uint rm) {
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// rs and rm are swapped because of restriction rd!=rm
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// mul rd, rm, rs
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emit_al(as, asm_arm_op_mul_reg(rd, rm, rs));
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}
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void asm_arm_and_reg_reg_reg(asm_arm_t *as, uint rd, uint rn, uint rm) {
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// and rd, rn, rm
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emit_al(as, asm_arm_op_and_reg(rd, rn, rm));
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}
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void asm_arm_eor_reg_reg_reg(asm_arm_t *as, uint rd, uint rn, uint rm) {
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// eor rd, rn, rm
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emit_al(as, asm_arm_op_eor_reg(rd, rn, rm));
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}
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void asm_arm_orr_reg_reg_reg(asm_arm_t *as, uint rd, uint rn, uint rm) {
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// orr rd, rn, rm
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emit_al(as, asm_arm_op_orr_reg(rd, rn, rm));
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}
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void asm_arm_mov_reg_local_addr(asm_arm_t *as, uint rd, int local_num) {
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// add rd, sp, #local_num*4
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emit_al(as, asm_arm_op_add_imm(rd, ASM_ARM_REG_SP, local_num << 2));
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}
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void asm_arm_mov_reg_pcrel(asm_arm_t *as, uint reg_dest, uint label) {
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assert(label < as->base.max_num_labels);
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mp_uint_t dest = as->base.label_offsets[label];
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mp_int_t rel = dest - as->base.code_offset;
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rel -= 12 + 8; // adjust for load of rel, and then PC+8 prefetch of add_reg_reg_reg
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// To load rel int reg_dest, insert immediate into code and jump over it
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emit_al(as, 0x59f0000 | (reg_dest << 12)); // ldr rd, [pc]
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emit_al(as, 0xa000000); // b pc
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emit(as, rel);
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// Do reg_dest += PC
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asm_arm_add_reg_reg_reg(as, reg_dest, reg_dest, ASM_ARM_REG_PC);
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}
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void asm_arm_lsl_reg_reg(asm_arm_t *as, uint rd, uint rs) {
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// mov rd, rd, lsl rs
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emit_al(as, 0x1a00010 | (rd << 12) | (rs << 8) | rd);
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}
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void asm_arm_lsr_reg_reg(asm_arm_t *as, uint rd, uint rs) {
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// mov rd, rd, lsr rs
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emit_al(as, 0x1a00030 | (rd << 12) | (rs << 8) | rd);
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}
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void asm_arm_asr_reg_reg(asm_arm_t *as, uint rd, uint rs) {
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// mov rd, rd, asr rs
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emit_al(as, 0x1a00050 | (rd << 12) | (rs << 8) | rd);
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}
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void asm_arm_ldr_reg_reg(asm_arm_t *as, uint rd, uint rn, uint byte_offset) {
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// ldr rd, [rn, #off]
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emit_al(as, 0x5900000 | (rn << 16) | (rd << 12) | byte_offset);
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}
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void asm_arm_ldrh_reg_reg(asm_arm_t *as, uint rd, uint rn) {
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// ldrh rd, [rn]
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emit_al(as, 0x1d000b0 | (rn << 16) | (rd << 12));
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}
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void asm_arm_ldrb_reg_reg(asm_arm_t *as, uint rd, uint rn) {
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// ldrb rd, [rn]
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emit_al(as, 0x5d00000 | (rn << 16) | (rd << 12));
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}
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void asm_arm_str_reg_reg(asm_arm_t *as, uint rd, uint rm, uint byte_offset) {
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// str rd, [rm, #off]
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emit_al(as, 0x5800000 | (rm << 16) | (rd << 12) | byte_offset);
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}
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void asm_arm_strh_reg_reg(asm_arm_t *as, uint rd, uint rm) {
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// strh rd, [rm]
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emit_al(as, 0x1c000b0 | (rm << 16) | (rd << 12));
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}
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void asm_arm_strb_reg_reg(asm_arm_t *as, uint rd, uint rm) {
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// strb rd, [rm]
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emit_al(as, 0x5c00000 | (rm << 16) | (rd << 12));
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}
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void asm_arm_str_reg_reg_reg(asm_arm_t *as, uint rd, uint rm, uint rn) {
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// str rd, [rm, rn, lsl #2]
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emit_al(as, 0x7800100 | (rm << 16) | (rd << 12) | rn);
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}
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void asm_arm_strh_reg_reg_reg(asm_arm_t *as, uint rd, uint rm, uint rn) {
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// strh doesn't support scaled register index
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emit_al(as, 0x1a00080 | (ASM_ARM_REG_R8 << 12) | rn); // mov r8, rn, lsl #1
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emit_al(as, 0x18000b0 | (rm << 16) | (rd << 12) | ASM_ARM_REG_R8); // strh rd, [rm, r8]
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}
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void asm_arm_strb_reg_reg_reg(asm_arm_t *as, uint rd, uint rm, uint rn) {
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// strb rd, [rm, rn]
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emit_al(as, 0x7c00000 | (rm << 16) | (rd << 12) | rn);
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}
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void asm_arm_bcc_label(asm_arm_t *as, int cond, uint label) {
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assert(label < as->base.max_num_labels);
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mp_uint_t dest = as->base.label_offsets[label];
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mp_int_t rel = dest - as->base.code_offset;
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rel -= 8; // account for instruction prefetch, PC is 8 bytes ahead of this instruction
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rel >>= 2; // in ARM mode the branch target is 32-bit aligned, so the 2 LSB are omitted
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if (SIGNED_FIT24(rel)) {
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emit(as, cond | 0xa000000 | (rel & 0xffffff));
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} else {
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printf("asm_arm_bcc: branch does not fit in 24 bits\n");
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}
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}
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void asm_arm_b_label(asm_arm_t *as, uint label) {
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asm_arm_bcc_label(as, ASM_ARM_CC_AL, label);
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}
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void asm_arm_bl_ind(asm_arm_t *as, uint fun_id, uint reg_temp) {
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// The table offset should fit into the ldr instruction
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assert(fun_id < (0x1000 / 4));
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emit_al(as, asm_arm_op_mov_reg(ASM_ARM_REG_LR, ASM_ARM_REG_PC)); // mov lr, pc
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emit_al(as, 0x597f000 | (fun_id << 2)); // ldr pc, [r7, #fun_id*4]
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}
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void asm_arm_bx_reg(asm_arm_t *as, uint reg_src) {
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emit_al(as, 0x012fff10 | reg_src);
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}
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#endif // MICROPY_EMIT_ARM
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