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357 lines
16 KiB
357 lines
16 KiB
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2020-2021 Damien P. George
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* Copyright (c) 2021 Robert Hammelrath
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "py/runtime.h"
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#include "py/mphal.h"
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#include "py/mperrno.h"
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#include "extmod/machine_spi.h"
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#include "modmachine.h"
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#include "dma_manager.h"
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#include "fsl_cache.h"
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#include "fsl_dmamux.h"
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#include "fsl_iomuxc.h"
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#include "fsl_lpspi.h"
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#include "fsl_lpspi_edma.h"
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#define DEFAULT_SPI_BAUDRATE (1000000)
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#define DEFAULT_SPI_POLARITY (0)
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#define DEFAULT_SPI_PHASE (0)
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#define DEFAULT_SPI_BITS (8)
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#define DEFAULT_SPI_FIRSTBIT (kLPSPI_MsbFirst)
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#define DEFAULT_SPI_DRIVE (6)
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#define CLOCK_DIVIDER (1)
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#define MICROPY_HW_SPI_NUM MP_ARRAY_SIZE(spi_index_table)
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#define SCK (iomux_table[index])
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#define CS0 (iomux_table[index + 1])
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#define SDO (iomux_table[index + 2])
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#define SDI (iomux_table[index + 3])
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#define CS1 (iomux_table[index + 4])
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typedef struct _machine_spi_obj_t {
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mp_obj_base_t base;
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uint8_t spi_id;
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uint8_t mode;
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uint8_t spi_hw_id;
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bool transfer_busy;
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LPSPI_Type *spi_inst;
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lpspi_master_config_t *master_config;
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} machine_spi_obj_t;
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typedef struct _iomux_table_t {
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uint32_t muxRegister;
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uint32_t muxMode;
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uint32_t inputRegister;
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uint32_t inputDaisy;
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uint32_t configRegister;
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} iomux_table_t;
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STATIC const uint8_t spi_index_table[] = MICROPY_HW_SPI_INDEX;
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STATIC LPSPI_Type *spi_base_ptr_table[] = LPSPI_BASE_PTRS;
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static const iomux_table_t iomux_table[] = {
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IOMUX_TABLE_SPI
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};
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static uint16_t dma_req_src_rx[] = DMA_REQ_SRC_RX;
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static uint16_t dma_req_src_tx[] = DMA_REQ_SRC_TX;
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bool lpspi_set_iomux(int8_t spi, uint8_t drive, uint8_t cs) {
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int index = (spi - 1) * 5;
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if (SCK.muxRegister != 0) {
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IOMUXC_SetPinMux(SCK.muxRegister, SCK.muxMode, SCK.inputRegister, SCK.inputDaisy, SCK.configRegister, 0U);
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IOMUXC_SetPinConfig(SCK.muxRegister, SCK.muxMode, SCK.inputRegister, SCK.inputDaisy, SCK.configRegister,
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pin_generate_config(PIN_PULL_UP_100K, PIN_MODE_OUT, drive, SCK.configRegister));
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if (cs == 0 && CS0.muxRegister != 0) {
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IOMUXC_SetPinMux(CS0.muxRegister, CS0.muxMode, CS0.inputRegister, CS0.inputDaisy, CS0.configRegister, 0U);
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IOMUXC_SetPinConfig(CS0.muxRegister, CS0.muxMode, CS0.inputRegister, CS0.inputDaisy, CS0.configRegister,
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pin_generate_config(PIN_PULL_UP_100K, PIN_MODE_OUT, drive, CS0.configRegister));
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} else if (cs == 1 && CS1.muxRegister != 0) {
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IOMUXC_SetPinMux(CS1.muxRegister, CS1.muxMode, CS1.inputRegister, CS1.inputDaisy, CS1.configRegister, 0U);
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IOMUXC_SetPinConfig(CS1.muxRegister, CS1.muxMode, CS1.inputRegister, CS1.inputDaisy, CS1.configRegister,
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pin_generate_config(PIN_PULL_UP_100K, PIN_MODE_OUT, drive, CS1.configRegister));
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} else {
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mp_raise_ValueError(MP_ERROR_TEXT("The chosen CS is not available"));
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}
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IOMUXC_SetPinMux(SDO.muxRegister, SDO.muxMode, SDO.inputRegister, SDO.inputDaisy, SDO.configRegister, 0U);
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IOMUXC_SetPinConfig(SDO.muxRegister, SDO.muxMode, SDO.inputRegister, SDO.inputDaisy, SDO.configRegister,
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pin_generate_config(PIN_PULL_UP_100K, PIN_MODE_OUT, drive, SDO.configRegister));
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IOMUXC_SetPinMux(SDI.muxRegister, SDI.muxMode, SDI.inputRegister, SDI.inputDaisy, SDI.configRegister, 0U);
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IOMUXC_SetPinConfig(SDI.muxRegister, SDI.muxMode, SDI.inputRegister, SDI.inputDaisy, SDI.configRegister,
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pin_generate_config(PIN_PULL_UP_100K, PIN_MODE_IN, drive, SDI.configRegister));
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return true;
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} else {
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return false;
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}
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}
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STATIC void machine_spi_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
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static const char *firstbit_str[] = {"MSB", "LSB"};
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machine_spi_obj_t *self = MP_OBJ_TO_PTR(self_in);
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mp_printf(print, "SPI(%u, baudrate=%u, polarity=%u, phase=%u, bits=%u, firstbit=%s, gap_ns=%d)",
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self->spi_id, self->master_config->baudRate, self->master_config->cpol,
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self->master_config->cpha, self->master_config->bitsPerFrame,
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firstbit_str[self->master_config->direction], self->master_config->betweenTransferDelayInNanoSec);
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}
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mp_obj_t machine_spi_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
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enum { ARG_id, ARG_baudrate, ARG_polarity, ARG_phase, ARG_bits, ARG_firstbit, ARG_gap_ns, ARG_drive, ARG_cs };
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static const mp_arg_t allowed_args[] = {
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{ MP_QSTR_id, MP_ARG_REQUIRED | MP_ARG_OBJ },
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{ MP_QSTR_baudrate, MP_ARG_INT, {.u_int = DEFAULT_SPI_BAUDRATE} },
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{ MP_QSTR_polarity, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = DEFAULT_SPI_POLARITY} },
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{ MP_QSTR_phase, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = DEFAULT_SPI_PHASE} },
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{ MP_QSTR_bits, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = DEFAULT_SPI_BITS} },
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{ MP_QSTR_firstbit, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = DEFAULT_SPI_FIRSTBIT} },
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{ MP_QSTR_gap_ns, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} },
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{ MP_QSTR_drive, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = DEFAULT_SPI_DRIVE} },
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{ MP_QSTR_cs, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} },
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};
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static bool clk_init = true;
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// Parse the arguments.
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mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
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mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
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// Get the SPI bus id.
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int spi_id = mp_obj_get_int(args[ARG_id].u_obj);
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if (spi_id < 0 || spi_id >= MP_ARRAY_SIZE(spi_index_table) || spi_index_table[spi_id] == 0) {
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mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("SPI(%d) doesn't exist"), spi_id);
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}
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// Get peripheral object.
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uint8_t spi_hw_id = spi_index_table[spi_id]; // the hw spi number 1..n
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machine_spi_obj_t *self = m_new_obj(machine_spi_obj_t);
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self->base.type = &machine_spi_type;
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self->spi_id = spi_id;
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self->spi_inst = spi_base_ptr_table[spi_hw_id];
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self->spi_hw_id = spi_hw_id;
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uint8_t drive = args[ARG_drive].u_int;
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if (drive < 1 || drive > 7) {
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drive = DEFAULT_SPI_DRIVE;
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}
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if (clk_init) {
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clk_init = false;
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/*Set clock source for LPSPI*/
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CLOCK_SetMux(kCLOCK_LpspiMux, 1); // Clock source is kCLOCK_Usb1PllPfd1Clk
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CLOCK_SetDiv(kCLOCK_LpspiDiv, CLOCK_DIVIDER);
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}
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LPSPI_Reset(self->spi_inst);
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LPSPI_Enable(self->spi_inst, false); // Disable first before new settings are applies
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self->master_config = m_new_obj(lpspi_master_config_t);
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LPSPI_MasterGetDefaultConfig(self->master_config);
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// Initialise the SPI peripheral.
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self->master_config->baudRate = args[ARG_baudrate].u_int;
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self->master_config->betweenTransferDelayInNanoSec = 1000000000 / self->master_config->baudRate * 2;
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self->master_config->cpol = args[ARG_polarity].u_int;
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self->master_config->cpha = args[ARG_phase].u_int;
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self->master_config->bitsPerFrame = args[ARG_bits].u_int;
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self->master_config->direction = args[ARG_firstbit].u_int;
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if (args[ARG_gap_ns].u_int != -1) {
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self->master_config->betweenTransferDelayInNanoSec = args[ARG_gap_ns].u_int;
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}
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uint8_t cs = args[ARG_cs].u_int;
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if (cs <= 1) {
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self->master_config->whichPcs = cs;
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}
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LPSPI_MasterInit(self->spi_inst, self->master_config, CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk) / (CLOCK_DIVIDER + 1));
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lpspi_set_iomux(spi_index_table[spi_id], drive, cs);
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return MP_OBJ_FROM_PTR(self);
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}
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STATIC void machine_spi_init(mp_obj_base_t *self_in, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
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enum { ARG_baudrate, ARG_polarity, ARG_phase, ARG_bits, ARG_firstbit, ARG_gap_ns };
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static const mp_arg_t allowed_args[] = {
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{ MP_QSTR_baudrate, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} },
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{ MP_QSTR_polarity, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} },
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{ MP_QSTR_phase, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} },
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{ MP_QSTR_bits, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} },
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{ MP_QSTR_firstbit, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} },
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{ MP_QSTR_gap_ns, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} },
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};
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// Parse the arguments.
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machine_spi_obj_t *self = (machine_spi_obj_t *)self_in;
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mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
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mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
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// Reconfigure the baudrate if requested.
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if (args[ARG_baudrate].u_int != -1) {
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self->master_config->baudRate = args[ARG_baudrate].u_int;
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self->master_config->betweenTransferDelayInNanoSec = 1000000000 / self->master_config->baudRate * 2;
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}
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// Reconfigure the format if requested.
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if (args[ARG_polarity].u_int != -1) {
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self->master_config->cpol = args[ARG_polarity].u_int;
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}
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if (args[ARG_phase].u_int != -1) {
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self->master_config->cpha = args[ARG_phase].u_int;
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}
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if (args[ARG_bits].u_int != -1) {
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self->master_config->bitsPerFrame = args[ARG_bits].u_int;
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}
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if (args[ARG_firstbit].u_int != -1) {
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self->master_config->direction = args[ARG_firstbit].u_int;
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}
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if (args[ARG_gap_ns].u_int != -1) {
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self->master_config->betweenTransferDelayInNanoSec = args[ARG_gap_ns].u_int;
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}
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LPSPI_Enable(self->spi_inst, false); // Disable first before new settings are applies
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LPSPI_MasterInit(self->spi_inst, self->master_config, CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk) / (CLOCK_DIVIDER + 1));
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}
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void LPSPI_EDMAMasterCallback(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, status_t status, void *self_in) {
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machine_spi_obj_t *self = (machine_spi_obj_t *)self_in;
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self->transfer_busy = false;
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}
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STATIC void machine_spi_transfer(mp_obj_base_t *self_in, size_t len, const uint8_t *src, uint8_t *dest) {
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machine_spi_obj_t *self = (machine_spi_obj_t *)self_in;
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// Use DMA for large transfers if channels are available
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const size_t dma_min_size_threshold = FSL_FEATURE_LPSPI_FIFO_SIZEn(0); // The Macro argument is ignored
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int chan_tx = -1;
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int chan_rx = -1;
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if (len >= dma_min_size_threshold) {
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// Use two DMA channels to service the two FIFOs
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chan_rx = allocate_dma_channel();
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chan_tx = allocate_dma_channel();
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}
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bool use_dma = chan_rx >= 0 && chan_tx >= 0;
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if (use_dma) {
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/* DMA MUX init*/
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DMAMUX_Init(DMAMUX);
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DMAMUX_SetSource(DMAMUX, chan_rx, dma_req_src_rx[self->spi_hw_id]); // ## SPIn source
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DMAMUX_EnableChannel(DMAMUX, chan_rx);
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DMAMUX_SetSource(DMAMUX, chan_tx, dma_req_src_tx[self->spi_hw_id]);
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DMAMUX_EnableChannel(DMAMUX, chan_tx);
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dma_init();
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lpspi_master_edma_handle_t g_master_edma_handle;
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edma_handle_t lpspiEdmaMasterRxRegToRxDataHandle;
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edma_handle_t lpspiEdmaMasterTxDataToTxRegHandle;
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// Set up lpspi EDMA master
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EDMA_CreateHandle(&(lpspiEdmaMasterRxRegToRxDataHandle), DMA0, chan_rx);
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EDMA_CreateHandle(&(lpspiEdmaMasterTxDataToTxRegHandle), DMA0, chan_tx);
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LPSPI_MasterTransferCreateHandleEDMA(self->spi_inst, &g_master_edma_handle, LPSPI_EDMAMasterCallback, self,
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&lpspiEdmaMasterRxRegToRxDataHandle,
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&lpspiEdmaMasterTxDataToTxRegHandle);
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// Wait a short while for a previous transfer to finish, but not forever
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for (volatile int j = 0; (j < 5000) && ((LPSPI_GetStatusFlags(self->spi_inst) & kLPSPI_ModuleBusyFlag) != 0); j++) {}
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// Start master transfer
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lpspi_transfer_t masterXfer;
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masterXfer.txData = (uint8_t *)src;
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masterXfer.rxData = (uint8_t *)dest;
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masterXfer.dataSize = len;
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masterXfer.configFlags = (self->master_config->whichPcs << LPSPI_MASTER_PCS_SHIFT) | kLPSPI_MasterPcsContinuous | kLPSPI_MasterByteSwap;
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// Reconfigure the TCR, required after switch between DMA vs. non-DMA
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LPSPI_Enable(self->spi_inst, false); // Disable first before new settings are applied
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self->spi_inst->TCR = LPSPI_TCR_CPOL(self->master_config->cpol) | LPSPI_TCR_CPHA(self->master_config->cpha) |
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LPSPI_TCR_LSBF(self->master_config->direction) | LPSPI_TCR_FRAMESZ(self->master_config->bitsPerFrame - 1) |
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(self->spi_inst->TCR & LPSPI_TCR_PRESCALE_MASK) | LPSPI_TCR_PCS(self->master_config->whichPcs);
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LPSPI_Enable(self->spi_inst, true);
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self->transfer_busy = true;
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if (dest) {
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L1CACHE_DisableDCache();
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} else if (src) {
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DCACHE_CleanByRange((uint32_t)src, len);
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}
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if (LPSPI_MasterTransferEDMA(self->spi_inst, &g_master_edma_handle, &masterXfer) != kStatus_Success) {
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L1CACHE_EnableDCache();
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mp_raise_OSError(EIO);
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} else {
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while (self->transfer_busy) {
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MICROPY_EVENT_POLL_HOOK
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}
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L1CACHE_EnableDCache();
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}
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}
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// Release DMA channels, even if never allocated.
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if (chan_rx >= 0) {
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free_dma_channel(chan_rx);
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}
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if (chan_tx >= 0) {
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free_dma_channel(chan_tx);
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}
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if (!use_dma) {
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// Wait a short while for a previous transfer to finish, but not forever
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for (volatile int j = 0; (j < 5000) && ((LPSPI_GetStatusFlags(self->spi_inst) & kLPSPI_ModuleBusyFlag) != 0); j++) {}
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// Reconfigure the TCR, required after switch between DMA vs. non-DMA
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LPSPI_Enable(self->spi_inst, false); // Disable first before new settings are applied
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self->spi_inst->TCR = LPSPI_TCR_CPOL(self->master_config->cpol) | LPSPI_TCR_CPHA(self->master_config->cpha) |
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LPSPI_TCR_LSBF(self->master_config->direction) | LPSPI_TCR_FRAMESZ(self->master_config->bitsPerFrame - 1) |
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(self->spi_inst->TCR & LPSPI_TCR_PRESCALE_MASK) | LPSPI_TCR_PCS(self->master_config->whichPcs);
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LPSPI_Enable(self->spi_inst, true);
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lpspi_transfer_t masterXfer;
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masterXfer.txData = (uint8_t *)src;
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masterXfer.rxData = (uint8_t *)dest;
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masterXfer.dataSize = len;
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masterXfer.configFlags = (self->master_config->whichPcs << LPSPI_MASTER_PCS_SHIFT) | kLPSPI_MasterPcsContinuous | kLPSPI_MasterByteSwap;
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if (LPSPI_MasterTransferBlocking(self->spi_inst, &masterXfer) != kStatus_Success) {
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mp_raise_OSError(EIO);
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}
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}
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}
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STATIC const mp_machine_spi_p_t machine_spi_p = {
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.init = machine_spi_init,
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.transfer = machine_spi_transfer,
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};
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const mp_obj_type_t machine_spi_type = {
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{ &mp_type_type },
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.name = MP_QSTR_SPI,
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.print = machine_spi_print,
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.make_new = machine_spi_make_new,
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.protocol = &machine_spi_p,
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.locals_dict = (mp_obj_dict_t *)&mp_machine_spi_locals_dict,
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};
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