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337 lines
12 KiB
337 lines
12 KiB
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2014-2018 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "py/runtime.h"
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#include "py/mperrno.h"
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#include "py/mphal.h"
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#include "can.h"
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#include "irq.h"
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#if MICROPY_HW_ENABLE_CAN && MICROPY_HW_ENABLE_FDCAN
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#define FDCAN_ELEMENT_MASK_STDID (0x1ffc0000) // Standard Identifier
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#define FDCAN_ELEMENT_MASK_EXTID (0x1fffffff) // Extended Identifier
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#define FDCAN_ELEMENT_MASK_RTR (0x20000000) // Remote Transmission Request
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#define FDCAN_ELEMENT_MASK_XTD (0x40000000) // Extended Identifier
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#define FDCAN_ELEMENT_MASK_ESI (0x80000000) // Error State Indicator
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#define FDCAN_ELEMENT_MASK_TS (0x0000ffff) // Timestamp
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#define FDCAN_ELEMENT_MASK_DLC (0x000f0000) // Data Length Code
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#define FDCAN_ELEMENT_MASK_BRS (0x00100000) // Bit Rate Switch
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#define FDCAN_ELEMENT_MASK_FDF (0x00200000) // FD Format
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#define FDCAN_ELEMENT_MASK_FIDX (0x7f000000) // Filter Index
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#define FDCAN_ELEMENT_MASK_ANMF (0x80000000) // Accepted Non-matching Frame
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bool can_init(pyb_can_obj_t *can_obj, uint32_t mode, uint32_t prescaler, uint32_t sjw, uint32_t bs1, uint32_t bs2, bool auto_restart) {
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(void)auto_restart;
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FDCAN_InitTypeDef *init = &can_obj->can.Init;
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init->FrameFormat = FDCAN_FRAME_CLASSIC;
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init->Mode = mode;
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init->NominalPrescaler = prescaler; // tq = NominalPrescaler x (1/fdcan_ker_ck)
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init->NominalSyncJumpWidth = sjw;
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init->NominalTimeSeg1 = bs1; // NominalTimeSeg1 = Propagation_segment + Phase_segment_1
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init->NominalTimeSeg2 = bs2;
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init->AutoRetransmission = ENABLE;
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init->TransmitPause = DISABLE;
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init->ProtocolException = ENABLE;
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// The Message RAM is shared between CAN1 and CAN2. Setting the offset to half
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// the Message RAM for the second CAN and using half the resources for each CAN.
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if (can_obj->can_id == PYB_CAN_1) {
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init->MessageRAMOffset = 0;
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} else {
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init->MessageRAMOffset = 2560 / 2;
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}
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init->StdFiltersNbr = 64; // 128 / 2
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init->ExtFiltersNbr = 0; // Not used
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init->TxEventsNbr = 16; // 32 / 2
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init->RxBuffersNbr = 32; // 64 / 2
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init->TxBuffersNbr = 16; // 32 / 2
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init->RxFifo0ElmtsNbr = 64; // 128 / 2
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init->RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
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init->RxFifo1ElmtsNbr = 64; // 128 / 2
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init->RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
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init->TxFifoQueueElmtsNbr = 16; // Tx fifo elements
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init->TxElmtSize = FDCAN_DATA_BYTES_8;
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init->TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
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FDCAN_GlobalTypeDef *CANx = NULL;
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const pin_obj_t *pins[2];
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switch (can_obj->can_id) {
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#if defined(MICROPY_HW_CAN1_TX)
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case PYB_CAN_1:
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CANx = FDCAN1;
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pins[0] = MICROPY_HW_CAN1_TX;
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pins[1] = MICROPY_HW_CAN1_RX;
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break;
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#endif
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#if defined(MICROPY_HW_CAN2_TX)
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case PYB_CAN_2:
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CANx = FDCAN2;
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pins[0] = MICROPY_HW_CAN2_TX;
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pins[1] = MICROPY_HW_CAN2_RX;
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break;
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#endif
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default:
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return false;
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}
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// Enable FDCAN clock
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__HAL_RCC_FDCAN_CLK_ENABLE();
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// init GPIO
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uint32_t pin_mode = MP_HAL_PIN_MODE_ALT;
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uint32_t pin_pull = MP_HAL_PIN_PULL_UP;
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for (int i = 0; i < 2; ++i) {
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if (!mp_hal_pin_config_alt(pins[i], pin_mode, pin_pull, AF_FN_CAN, can_obj->can_id)) {
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return false;
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}
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}
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// init CANx
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can_obj->can.Instance = CANx;
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HAL_FDCAN_Init(&can_obj->can);
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// Disable acceptance of non-matching frames (enabled by default)
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HAL_FDCAN_ConfigGlobalFilter(&can_obj->can, FDCAN_REJECT, FDCAN_REJECT, DISABLE, DISABLE);
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// The configuration registers are locked after CAN is started.
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HAL_FDCAN_Start(&can_obj->can);
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// Reset all filters
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for (int f = 0; f < 64; ++f) {
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can_clearfilter(can_obj, f, 0);
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}
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can_obj->is_enabled = true;
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can_obj->num_error_warning = 0;
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can_obj->num_error_passive = 0;
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can_obj->num_bus_off = 0;
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switch (can_obj->can_id) {
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case PYB_CAN_1:
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NVIC_SetPriority(FDCAN1_IT0_IRQn, IRQ_PRI_CAN);
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HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn);
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NVIC_SetPriority(FDCAN1_IT1_IRQn, IRQ_PRI_CAN);
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HAL_NVIC_EnableIRQ(FDCAN1_IT1_IRQn);
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break;
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case PYB_CAN_2:
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NVIC_SetPriority(FDCAN2_IT0_IRQn, IRQ_PRI_CAN);
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HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn);
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NVIC_SetPriority(FDCAN2_IT1_IRQn, IRQ_PRI_CAN);
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HAL_NVIC_EnableIRQ(FDCAN2_IT1_IRQn);
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break;
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default:
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return false;
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}
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__HAL_FDCAN_ENABLE_IT(&can_obj->can, FDCAN_IT_BUS_OFF | FDCAN_IT_ERROR_WARNING | FDCAN_IT_ERROR_PASSIVE);
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__HAL_FDCAN_ENABLE_IT(&can_obj->can, FDCAN_IT_RX_FIFO0_NEW_MESSAGE | FDCAN_IT_RX_FIFO1_NEW_MESSAGE);
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__HAL_FDCAN_ENABLE_IT(&can_obj->can, FDCAN_IT_RX_FIFO0_MESSAGE_LOST | FDCAN_IT_RX_FIFO1_MESSAGE_LOST);
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__HAL_FDCAN_ENABLE_IT(&can_obj->can, FDCAN_IT_RX_FIFO0_FULL | FDCAN_IT_RX_FIFO1_FULL);
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return true;
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}
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void can_deinit(pyb_can_obj_t *self) {
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self->is_enabled = false;
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HAL_FDCAN_DeInit(&self->can);
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if (self->can.Instance == FDCAN1) {
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HAL_NVIC_DisableIRQ(FDCAN1_IT0_IRQn);
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HAL_NVIC_DisableIRQ(FDCAN1_IT1_IRQn);
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// TODO check if FDCAN2 is used.
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__HAL_RCC_FDCAN_FORCE_RESET();
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__HAL_RCC_FDCAN_RELEASE_RESET();
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__HAL_RCC_FDCAN_CLK_DISABLE();
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#if defined(MICROPY_HW_CAN2_TX)
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} else if (self->can.Instance == FDCAN2) {
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HAL_NVIC_DisableIRQ(FDCAN2_IT0_IRQn);
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HAL_NVIC_DisableIRQ(FDCAN2_IT1_IRQn);
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// TODO check if FDCAN2 is used.
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__HAL_RCC_FDCAN_FORCE_RESET();
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__HAL_RCC_FDCAN_RELEASE_RESET();
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__HAL_RCC_FDCAN_CLK_DISABLE();
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#endif
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}
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}
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void can_clearfilter(pyb_can_obj_t *self, uint32_t f, uint8_t bank) {
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if (self && self->can.Instance) {
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FDCAN_FilterTypeDef filter = {0};
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filter.IdType = FDCAN_STANDARD_ID;
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filter.FilterIndex = f;
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filter.FilterConfig = FDCAN_FILTER_DISABLE;
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HAL_FDCAN_ConfigFilter(&self->can, &filter);
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}
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}
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int can_receive(FDCAN_HandleTypeDef *can, int fifo, FDCAN_RxHeaderTypeDef *hdr, uint8_t *data, uint32_t timeout_ms) {
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volatile uint32_t *rxf, *rxa;
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uint32_t fl;
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if (fifo == FDCAN_RX_FIFO0) {
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rxf = &can->Instance->RXF0S;
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rxa = &can->Instance->RXF0A;
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fl = FDCAN_RXF0S_F0FL;
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} else {
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rxf = &can->Instance->RXF1S;
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rxa = &can->Instance->RXF1A;
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fl = FDCAN_RXF1S_F1FL;
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}
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// Wait for a message to become available, with timeout
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uint32_t start = HAL_GetTick();
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while ((*rxf & fl) == 0) {
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if (timeout_ms != HAL_MAX_DELAY) {
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if (HAL_GetTick() - start >= timeout_ms) {
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return -MP_ETIMEDOUT;
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}
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}
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MICROPY_EVENT_POLL_HOOK
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}
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// Get pointer to incoming message
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uint32_t index, *address;
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if (fifo == FDCAN_RX_FIFO0) {
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index = (*rxf & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos;
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address = (uint32_t *)(can->msgRam.RxFIFO0SA + (index * can->Init.RxFifo0ElmtSize * 4));
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} else {
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index = (*rxf & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos;
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address = (uint32_t *)(can->msgRam.RxFIFO1SA + (index * can->Init.RxFifo1ElmtSize * 4));
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}
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// Parse header of message
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hdr->IdType = *address & FDCAN_ELEMENT_MASK_XTD;
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if (hdr->IdType == FDCAN_STANDARD_ID) {
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hdr->Identifier = (*address & FDCAN_ELEMENT_MASK_STDID) >> 18;
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} else {
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hdr->Identifier = *address & FDCAN_ELEMENT_MASK_EXTID;
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}
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hdr->RxFrameType = *address & FDCAN_ELEMENT_MASK_RTR;
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hdr->ErrorStateIndicator = *address++ & FDCAN_ELEMENT_MASK_ESI;
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hdr->RxTimestamp = *address & FDCAN_ELEMENT_MASK_TS;
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hdr->DataLength = (*address & FDCAN_ELEMENT_MASK_DLC) >> 16;
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hdr->BitRateSwitch = *address & FDCAN_ELEMENT_MASK_BRS;
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hdr->FDFormat = *address & FDCAN_ELEMENT_MASK_FDF;
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hdr->FilterIndex = (*address & FDCAN_ELEMENT_MASK_FIDX) >> 24;
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hdr->IsFilterMatchingFrame = (*address++ & FDCAN_ELEMENT_MASK_ANMF) >> 31;
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// Copy data
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uint8_t *pdata = (uint8_t *)address;
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for (uint32_t i = 0; i < 8; ++i) { // TODO use DLCtoBytes[hdr->DataLength] for length > 8
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*data++ = *pdata++;
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}
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// Release (free) message from FIFO
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*rxa = index;
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return 0; // success
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}
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STATIC void can_rx_irq_handler(uint can_id, uint fifo_id) {
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mp_obj_t callback;
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pyb_can_obj_t *self;
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mp_obj_t irq_reason = MP_OBJ_NEW_SMALL_INT(0);
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byte *state;
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self = MP_STATE_PORT(pyb_can_obj_all)[can_id - 1];
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if (fifo_id == FDCAN_RX_FIFO0) {
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callback = self->rxcallback0;
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state = &self->rx_state0;
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} else {
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callback = self->rxcallback1;
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state = &self->rx_state1;
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}
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switch (*state) {
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case RX_STATE_FIFO_EMPTY:
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__HAL_FDCAN_DISABLE_IT(&self->can, (fifo_id == FDCAN_RX_FIFO0) ?
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FDCAN_IT_RX_FIFO0_NEW_MESSAGE : FDCAN_IT_RX_FIFO1_NEW_MESSAGE);
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irq_reason = MP_OBJ_NEW_SMALL_INT(0);
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*state = RX_STATE_MESSAGE_PENDING;
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break;
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case RX_STATE_MESSAGE_PENDING:
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__HAL_FDCAN_DISABLE_IT(&self->can, (fifo_id == FDCAN_RX_FIFO0) ? FDCAN_IT_RX_FIFO0_FULL : FDCAN_IT_RX_FIFO1_FULL);
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__HAL_FDCAN_CLEAR_FLAG(&self->can, (fifo_id == FDCAN_RX_FIFO0) ? FDCAN_FLAG_RX_FIFO0_FULL : FDCAN_FLAG_RX_FIFO1_FULL);
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irq_reason = MP_OBJ_NEW_SMALL_INT(1);
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*state = RX_STATE_FIFO_FULL;
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break;
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case RX_STATE_FIFO_FULL:
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__HAL_FDCAN_DISABLE_IT(&self->can, (fifo_id == FDCAN_RX_FIFO0) ?
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FDCAN_IT_RX_FIFO0_MESSAGE_LOST : FDCAN_IT_RX_FIFO1_MESSAGE_LOST);
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__HAL_FDCAN_CLEAR_FLAG(&self->can, (fifo_id == FDCAN_RX_FIFO0) ?
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FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST : FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST);
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irq_reason = MP_OBJ_NEW_SMALL_INT(2);
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*state = RX_STATE_FIFO_OVERFLOW;
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break;
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case RX_STATE_FIFO_OVERFLOW:
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// This should never happen
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break;
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}
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pyb_can_handle_callback(self, fifo_id, callback, irq_reason);
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}
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#if defined(MICROPY_HW_CAN1_TX)
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void FDCAN1_IT0_IRQHandler(void) {
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IRQ_ENTER(FDCAN1_IT0_IRQn);
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can_rx_irq_handler(PYB_CAN_1, FDCAN_RX_FIFO0);
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IRQ_EXIT(FDCAN1_IT0_IRQn);
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}
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void FDCAN1_IT1_IRQHandler(void) {
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IRQ_ENTER(FDCAN1_IT1_IRQn);
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can_rx_irq_handler(PYB_CAN_1, FDCAN_RX_FIFO1);
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IRQ_EXIT(FDCAN1_IT1_IRQn);
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}
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#endif
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#if defined(MICROPY_HW_CAN2_TX)
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void FDCAN2_IT0_IRQHandler(void) {
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IRQ_ENTER(FDCAN2_IT0_IRQn);
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can_rx_irq_handler(PYB_CAN_2, FDCAN_RX_FIFO0);
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IRQ_EXIT(FDCAN2_IT0_IRQn);
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}
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void FDCAN2_IT1_IRQHandler(void) {
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IRQ_ENTER(FDCAN2_IT1_IRQn);
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can_rx_irq_handler(PYB_CAN_2, FDCAN_RX_FIFO1);
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IRQ_EXIT(FDCAN2_IT1_IRQn);
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}
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#endif
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#endif // MICROPY_HW_ENABLE_CAN && MICROPY_HW_ENABLE_FDCAN
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