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67 lines
2.5 KiB
67 lines
2.5 KiB
3 years ago
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/*******************************************************************************
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Copyright (c) 2016-2021 NVIDIA Corporation
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to
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deal in the Software without restriction, including without limitation the
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rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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sell copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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DEALINGS IN THE SOFTWARE.
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*******************************************************************************/
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#include "uvm_linux.h"
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#include "uvm_global.h"
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#include "uvm_gpu.h"
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#include "uvm_hal.h"
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static void clear_access_counter_notifications_interrupt(uvm_parent_gpu_t *parent_gpu)
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{
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volatile NvU32 *reg;
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NvU32 mask;
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reg = parent_gpu->access_counter_buffer_info.rm_info.pHubIntr;
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mask = parent_gpu->access_counter_buffer_info.rm_info.accessCounterMask;
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UVM_GPU_WRITE_ONCE(*reg, mask);
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}
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void uvm_hal_turing_disable_access_counter_notifications(uvm_parent_gpu_t *parent_gpu)
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{
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volatile NvU32 *reg;
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NvU32 mask;
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reg = parent_gpu->access_counter_buffer_info.rm_info.pHubIntrEnClear;
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mask = parent_gpu->access_counter_buffer_info.rm_info.accessCounterMask;
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UVM_GPU_WRITE_ONCE(*reg, mask);
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wmb();
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// See the comment in uvm_hal_turing_disable_replayable_faults
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clear_access_counter_notifications_interrupt(parent_gpu);
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}
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void uvm_hal_turing_clear_access_counter_notifications(uvm_parent_gpu_t *parent_gpu, NvU32 get)
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{
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clear_access_counter_notifications_interrupt(parent_gpu);
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wmb();
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// Write GET to force the re-evaluation of the interrupt condition after the
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// interrupt bit has been cleared.
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UVM_GPU_WRITE_ONCE(*parent_gpu->access_counter_buffer_info.rm_info.pAccessCntrBufferGet, get);
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}
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