560.35.03

README.md

@@ -1,7 +1,7 @@
 # NVIDIA Linux Open GPU Kernel Module Source
 
 This is the source release of the NVIDIA Linux open GPU kernel modules,
-version 560.31.02.
+version 560.35.03.
 
 
 ## How to Build
@@ -17,7 +17,7 @@ as root:
 
 Note that the kernel modules built here must be used with GSP
 firmware and user-space NVIDIA GPU driver components from a corresponding
-560.31.02 driver release.  This can be achieved by installing
+560.35.03 driver release.  This can be achieved by installing
 the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
 option.  E.g.,
 
@@ -185,7 +185,7 @@ table below).
 For details on feature support and limitations, see the NVIDIA GPU driver
 end user README here:
 
-https://us.download.nvidia.com/XFree86/Linux-x86_64/560.31.02/README/kernel_open.html
+https://us.download.nvidia.com/XFree86/Linux-x86_64/560.35.03/README/kernel_open.html
 
 For vGPU support, please refer to the README.vgpu packaged in the vGPU Host
 Package for more details.

kernel-open/Kbuild

@@ -72,7 +72,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc
 EXTRA_CFLAGS += -I$(src)
 EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-format-extra-args
 EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM
-EXTRA_CFLAGS += -DNV_VERSION_STRING=\"560.31.02\"
+EXTRA_CFLAGS += -DNV_VERSION_STRING=\"560.35.03\"
 
 ifneq ($(SYSSRCHOST1X),)
  EXTRA_CFLAGS += -I$(SYSSRCHOST1X)

kernel-open/common/inc/nvkms-kapi.h

@@ -1425,7 +1425,7 @@ struct NvKmsKapiFunctionsTable {
     );
 
     /*!
-     * Immediately reset the specified display semaphore to the pending state.
+     * Immediately initialize the specified display semaphore to the pending state.
      *
      * Must be called prior to applying a mode set that utilizes the specified
      * display semaphore for synchronization.
@@ -1438,7 +1438,7 @@ struct NvKmsKapiFunctionsTable {
      *                            for the specified device.
      */
     NvBool
-    (*resetDisplaySemaphore)
+    (*tryInitDisplaySemaphore)
     (
         struct NvKmsKapiDevice *device,
         NvU32 semaphoreIndex
@@ -1447,7 +1447,7 @@ struct NvKmsKapiFunctionsTable {
     /*!
      * Immediately set the specified display semaphore to the displayable state.
      *
-     * Must be called after \ref resetDisplaySemaphore to indicate a mode
+     * Must be called after \ref tryInitDisplaySemaphore to indicate a mode
      * configuration change that utilizes the specified display semaphore for
      * synchronization may proceed.
      *
@@ -1471,7 +1471,7 @@ struct NvKmsKapiFunctionsTable {
      *
      * This can be used by clients to restore a semaphore to a consistent state
      * when they have prepared it for use by previously calling
-     * \ref resetDisplaySemaphore() on it, but are then prevented from
+     * \ref tryInitDisplaySemaphore() on it, but are then prevented from
      * submitting the associated hardware operations to consume it due to the
      * subsequent failure of some software or hardware operation.
      *

kernel-open/nvidia-drm/nvidia-drm-modeset.c

@@ -192,6 +192,7 @@ static int __nv_drm_convert_in_fences(
         &to_nv_crtc_state(crtc_state)->req_config;
     struct nv_drm_plane_fence_cb_data *fence_data;
     uint32_t semaphore_index;
+    uint32_t idx_count;
     int ret, i;
 
     if (!crtc_state->active) {
@@ -244,9 +245,14 @@ static int __nv_drm_convert_in_fences(
             return -EINVAL;
         }
 
+        for (idx_count = 0; idx_count < nv_dev->display_semaphores.count; idx_count++) {
             semaphore_index = nv_drm_next_display_semaphore(nv_dev);
+            if (nvKms->tryInitDisplaySemaphore(nv_dev->pDevice, semaphore_index)) {
+                break;
+            }
+        }
 
-        if (!nvKms->resetDisplaySemaphore(nv_dev->pDevice, semaphore_index)) {
+        if (idx_count == nv_dev->display_semaphores.count) {
             NV_DRM_DEV_LOG_ERR(
                 nv_dev,
                 "Failed to initialize semaphore for plane fence");

kernel-open/nvidia-uvm/uvm_common.h

@@ -1,5 +1,5 @@
 /*******************************************************************************
-    Copyright (c) 2013-2023 NVIDIA Corporation
+    Copyright (c) 2013-2024 NVIDIA Corporation
 
     Permission is hereby granted, free of charge, to any person obtaining a copy
     of this software and associated documentation files (the "Software"), to
@@ -423,7 +423,9 @@ static void uvm_get_unaddressable_range(NvU32 num_va_bits, NvU64 *first, NvU64 *
     UVM_ASSERT(first);
     UVM_ASSERT(outer);
 
-    if (uvm_platform_uses_canonical_form_address()) {
+    // Maxwell GPUs (num_va_bits == 40b) do not support canonical form address
+    // even when plugged into platforms using it.
+    if (uvm_platform_uses_canonical_form_address() && num_va_bits > 40) {
         *first = 1ULL << (num_va_bits - 1);
         *outer = (NvU64)((NvS64)(1ULL << 63) >> (64 - num_va_bits));
     }

kernel-open/nvidia-uvm/uvm_populate_pageable.c

@@ -137,6 +137,15 @@ NV_STATUS uvm_populate_pageable_vma(struct vm_area_struct *vma,
     if (status != NV_OK)
         goto out;
 
+    // Kernel v6.6 introduced a bug in set_pte_range() around the handling of AF
+    // bit. Instead of setting the AF bit, the bit is incorrectly being cleared
+    // in set_pte_range() during first-touch fault handling. Calling
+    // handle_mm_fault() again takes a different code path which correctly sets
+    // the AF bit.
+    status = handle_fault(vma, start, vma_num_pages, !!(gup_flags & FOLL_WRITE));
+    if (status != NV_OK)
+        goto out;
+
     if (touch)
         ret = NV_PIN_USER_PAGES_REMOTE(mm, start, vma_num_pages, gup_flags, pages, NULL);
     else

src/common/inc/nvBldVer.h

@@ -36,25 +36,25 @@
 // and then checked back in. You cannot make changes to these sections without
 // corresponding changes to the buildmeister script
 #ifndef NV_BUILD_BRANCH
-    #define NV_BUILD_BRANCH             r560_78
+    #define NV_BUILD_BRANCH             r560_88
 #endif
 #ifndef NV_PUBLIC_BRANCH
-    #define NV_PUBLIC_BRANCH             r560_78
+    #define NV_PUBLIC_BRANCH             r560_88
 #endif
 
 #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
-#define NV_BUILD_BRANCH_VERSION         "rel/gpu_drv/r560/r560_78-120"
+#define NV_BUILD_BRANCH_VERSION         "rel/gpu_drv/r560/r560_88-137"
-#define NV_BUILD_CHANGELIST_NUM         (34643855)
+#define NV_BUILD_CHANGELIST_NUM         (34725486)
 #define NV_BUILD_TYPE                   "Official"
-#define NV_BUILD_NAME                   "rel/gpu_drv/r560/r560_78-120"
+#define NV_BUILD_NAME                   "rel/gpu_drv/r560/r560_88-137"
-#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34643855)
+#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34725486)
 
 #else     /* Windows builds */
-#define NV_BUILD_BRANCH_VERSION         "r560_78-2"
+#define NV_BUILD_BRANCH_VERSION         "r560_88-4"
-#define NV_BUILD_CHANGELIST_NUM         (34643068)
+#define NV_BUILD_CHANGELIST_NUM         (34711266)
 #define NV_BUILD_TYPE                   "Official"
-#define NV_BUILD_NAME                   "560.81"
+#define NV_BUILD_NAME                   "560.94"
-#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34643068)
+#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34711266)
 #define NV_BUILD_BRANCH_BASE_VERSION    R560
 #endif
 // End buildmeister python edited section

src/common/inc/nvUnixVersion.h

@@ -4,7 +4,7 @@
 #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
     (defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
 
-#define NV_VERSION_STRING               "560.31.02"
+#define NV_VERSION_STRING               "560.35.03"
 
 #else
 

src/common/sdk/nvidia/inc/nvfixedtypes.h

@@ -84,9 +84,11 @@ typedef NvUFXP32                                                    NvUFXP25_7;
 typedef NvUFXP32                                                    NvUFXP26_6;
 typedef NvUFXP32                                                    NvUFXP28_4;
 
+typedef NvUFXP64                                                   NvUFXP37_27;
 typedef NvUFXP64                                                   NvUFXP40_24;
 typedef NvUFXP64                                                   NvUFXP48_16;
 typedef NvUFXP64                                                   NvUFXP52_12;
+typedef NvUFXP64                                                   NvUFXP54_10;
 typedef NvUFXP64                                                    NvUFXP60_4;
 
 /*!

src/nvidia-modeset/kapi/include/nvkms-kapi-notifiers.h

@@ -84,7 +84,7 @@ NvBool nvKmsKapiIsNotifierFinish(const struct NvKmsKapiDevice *device,
 void nvKmsKapiNotifierSetNotBegun(struct NvKmsKapiDevice *device,
                                   NvU32 head, NvU32 layer, NvU32 index);
 
-NvBool nvKmsKapiResetDisplaySemaphore(struct NvKmsKapiDevice *device,
+NvBool nvKmsKapiTryInitDisplaySemaphore(struct NvKmsKapiDevice *device,
                                         NvU32 index);
 
 void nvKmsKapiSignalDisplaySemaphore(struct NvKmsKapiDevice *device,

src/nvidia-modeset/kapi/interface/nvkms-kapi.h

@@ -1425,7 +1425,7 @@ struct NvKmsKapiFunctionsTable {
     );
 
     /*!
-     * Immediately reset the specified display semaphore to the pending state.
+     * Immediately initialize the specified display semaphore to the pending state.
      *
      * Must be called prior to applying a mode set that utilizes the specified
      * display semaphore for synchronization.
@@ -1438,7 +1438,7 @@ struct NvKmsKapiFunctionsTable {
      *                            for the specified device.
      */
     NvBool
-    (*resetDisplaySemaphore)
+    (*tryInitDisplaySemaphore)
     (
         struct NvKmsKapiDevice *device,
         NvU32 semaphoreIndex
@@ -1447,7 +1447,7 @@ struct NvKmsKapiFunctionsTable {
     /*!
      * Immediately set the specified display semaphore to the displayable state.
      *
-     * Must be called after \ref resetDisplaySemaphore to indicate a mode
+     * Must be called after \ref tryInitDisplaySemaphore to indicate a mode
      * configuration change that utilizes the specified display semaphore for
      * synchronization may proceed.
      *
@@ -1471,7 +1471,7 @@ struct NvKmsKapiFunctionsTable {
      *
      * This can be used by clients to restore a semaphore to a consistent state
      * when they have prepared it for use by previously calling
-     * \ref resetDisplaySemaphore() on it, but are then prevented from
+     * \ref tryInitDisplaySemaphore() on it, but are then prevented from
      * submitting the associated hardware operations to consume it due to the
      * subsequent failure of some software or hardware operation.
      *

src/nvidia-modeset/kapi/src/nvkms-kapi-notifiers.c

@@ -286,7 +286,7 @@ NvBool nvKmsKapiAllocateSemaphores(struct NvKmsKapiDevice *device,
     return NV_TRUE;
 }
 
-NvBool nvKmsKapiResetDisplaySemaphore(struct NvKmsKapiDevice *device,
+NvBool nvKmsKapiTryInitDisplaySemaphore(struct NvKmsKapiDevice *device,
                                         NvU32 index)
 {
     struct nvKmsParsedSemaphore semParsed;
@@ -297,12 +297,6 @@ NvBool nvKmsKapiResetDisplaySemaphore(struct NvKmsKapiDevice *device,
                         &semParsed);
 
     if (semParsed.payload != NVKMS_KAPI_SEMAPHORE_VALUE_DONE) {
-        nvKmsKapiLogDeviceDebug(
-            device,
-            "Attempt to reuse semaphore at index %u with pending status 0x%08x",
-            index,
-            semParsed.payload);
-
         return NV_FALSE;
     }
 

src/nvidia-modeset/kapi/src/nvkms-kapi.c

@@ -3607,7 +3607,7 @@ NvBool nvKmsKapiGetFunctionsTableInternal
         nvKmsKapiSetSemaphoreSurfaceValue;
     funcsTable->setSuspendResumeCallback = nvKmsKapiSetSuspendResumeCallback;
 
-    funcsTable->resetDisplaySemaphore = nvKmsKapiResetDisplaySemaphore;
+    funcsTable->tryInitDisplaySemaphore = nvKmsKapiTryInitDisplaySemaphore;
     funcsTable->signalDisplaySemaphore = nvKmsKapiSignalDisplaySemaphore;
     funcsTable->cancelDisplaySemaphore = nvKmsKapiCancelDisplaySemaphore;
     funcsTable->signalVrrSemaphore = SignalVrrSemaphore;

src/nvidia-modeset/src/nvkms-evo.c

@@ -6716,7 +6716,8 @@ static NvBool GetDfpHdmiProtocol(const NVDpyEvoRec *pDpyEvo,
         nvDpyGetOutputColorFormatInfo(pDpyEvo);
     const NvBool forceHdmiFrlIsSupported = FALSE;
 
-    nvAssert(rmProtocol == NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_A ||
+    nvAssert(rmProtocol == NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DUAL_TMDS ||
+             rmProtocol == NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_A ||
              rmProtocol == NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_B);
 
     /* Override protocol if this mode requires HDMI FRL. */
@@ -6743,10 +6744,25 @@ static NvBool GetDfpHdmiProtocol(const NVDpyEvoRec *pDpyEvo,
         if (nvHdmiGetEffectivePixelClockKHz(pDpyEvo, pTimings, pDpyColor) <=
                pDpyEvo->maxSingleLinkPixelClockKHz) {
 
-            *pTimingsProtocol = (rmProtocol ==
+            switch (rmProtocol) {
-                NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_A) ?
+                case NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DUAL_TMDS:
-                NVKMS_PROTOCOL_SOR_SINGLE_TMDS_A :
+                    /*
-                NVKMS_PROTOCOL_SOR_SINGLE_TMDS_B;
+                     * Force single link TMDS protocol. HDMI does not support
+                     * physically support dual link TMDS.
+                     *
+                     * TMDS_A: "use A side of the link"
+                     */
+                    *pTimingsProtocol = NVKMS_PROTOCOL_SOR_SINGLE_TMDS_A;
+                    break;
+                case NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_A:
+                    *pTimingsProtocol = NVKMS_PROTOCOL_SOR_SINGLE_TMDS_A;
+                    break;
+                case NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_B:
+                    *pTimingsProtocol = NVKMS_PROTOCOL_SOR_SINGLE_TMDS_B;
+                    break;
+                default:
+                    return FALSE;
+            }
             return TRUE;
         }
     } while (nvDowngradeColorSpaceAndBpc(&colorFormatsInfo,

src/nvidia-modeset/src/nvkms-headsurface-ioctl.c

@@ -110,7 +110,7 @@ NvBool nvHsIoctlMoveCursor(
 {
     NVHsChannelEvoRec *pHsChannel;
 
-    if (apiHead > ARRAY_LEN(pDispEvo->pHsChannel)) {
+    if (apiHead >= ARRAY_LEN(pDispEvo->pHsChannel)) {
         return FALSE;
     }
 
@@ -206,7 +206,7 @@ NvBool nvHsIoctlSetCursorImage(
     NVHsChannelEvoRec *pHsChannel;
     NVSurfaceEvoRec *pSurfaceEvo = NULL;
 
-    if (apiHead > ARRAY_LEN(pDispEvo->pHsChannel)) {
+    if (apiHead >= ARRAY_LEN(pDispEvo->pHsChannel)) {
         return FALSE;
     }
 

src/nvidia/arch/nvalloc/common/inc/gsp/gsp_proxy_reg.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -40,4 +40,8 @@
 #define NVGSP_PROXY_REG_CONF_COMPUTE_MULTI_GPU_MODE_NONE            0x00000000
 #define NVGSP_PROXY_REG_CONF_COMPUTE_MULTI_GPU_MODE_PROTECTED_PCIE  0x00000001
 
+#define NVGSP_PROXY_REG_NVLINK_ENCRYPTION                           5:5
+#define NVGSP_PROXY_REG_NVLINK_ENCRYPTION_DISABLE                   0x00000000
+#define NVGSP_PROXY_REG_NVLINK_ENCRYPTION_ENABLE                    0x00000001
+
 #endif // NVGSP_PROXY_REG_H

src/nvidia/generated/g_gpu_mgr_nvoc.h

@@ -137,6 +137,7 @@ typedef struct CONF_COMPUTE_CAPS
     NvBool bAcceptClientRequest;
     NvBool bMultiGpuProtectedPcieModeEnabled;
     NvBool bFatalFailure;
+    NvBool bNvlEncryptionEnabled;
 } CONF_COMPUTE_CAPS;
 
 //

src/nvidia/generated/g_kernel_nvlink_nvoc.h

@@ -311,6 +311,7 @@ struct KernelNvlink {
     NvBool PDB_PROP_KNVLINK_ENCRYPTION_ENABLED;
 
     // Data members
+    NvU32 gspProxyRegkeys;
     struct KernelIoctrl *PRIVATE_FIELD(pKernelIoctrl)[3];
     NvU32 PRIVATE_FIELD(ioctrlMask);
     NvU32 PRIVATE_FIELD(ipVerNvlink);
@@ -444,6 +445,7 @@ struct KernelNvlink_PRIVATE {
     NvBool PDB_PROP_KNVLINK_ENCRYPTION_ENABLED;
 
     // Data members
+    NvU32 gspProxyRegkeys;
     struct KernelIoctrl *pKernelIoctrl[3];
     NvU32 ioctrlMask;
     NvU32 ipVerNvlink;

src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c

@@ -41,6 +41,8 @@
 #include "published/hopper/gh100/dev_riscv_pri.h"
 #include "published/hopper/gh100/dev_vm.h"
 
+#include "gpu/nvlink/kernel_nvlink.h"
+
 #define RISCV_BR_ADDR_ALIGNMENT                 (8)
 
 const char*
@@ -409,6 +411,12 @@ kgspSetupGspFmcArgs_GH100
         pGspFmcBootParams->initParams.regkeys = pCC->gspProxyRegkeys;
     }
 
+    KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu);
+    if (pKernelNvlink != NULL)
+    {
+        pGspFmcBootParams->initParams.regkeys |= pKernelNvlink->gspProxyRegkeys;
+    }
+
     pGspFmcBootParams->bootGspRmParams.gspRmDescOffset = memdescGetPhysAddr(pKernelGsp->pWprMetaDescriptor, AT_GPU, 0);
     pGspFmcBootParams->bootGspRmParams.gspRmDescSize = sizeof(*pKernelGsp->pWprMeta);
     pGspFmcBootParams->bootGspRmParams.target = _kgspMemdescToDmaTarget(pKernelGsp->pWprMetaDescriptor);

src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkoverrides.c

@@ -28,6 +28,9 @@
 #include "nvrm_registry.h"
 #include "os/os.h"
 
+#include "gpu/conf_compute/conf_compute.h"
+#include "gsp/gsp_proxy_reg.h"
+
 /*!
  * @brief Apply NVLink overrides from Registry
  *
@@ -278,11 +281,33 @@ knvlinkApplyRegkeyOverrides_IMPL
     if (NV_OK == osReadRegistryDword(pGpu,
                  NV_REG_STR_RM_NVLINK_ENCRYPTION, &regdata))
     {
+        //
+        // Nvlink Encryption PDB PROP is set when Nvlink Encryption regkey has been enabled AND
+        // either we are running in MODS or CC is enabled
+        //
         if (FLD_TEST_DRF(_REG_STR_RM, _NVLINK_ENCRYPTION, _MODE, _ENABLE, regdata))
         {
-            pKernelNvlink->setProperty(pGpu, PDB_PROP_KNVLINK_ENCRYPTION_ENABLED, NV_TRUE);
+            if (RMCFG_FEATURE_MODS_FEATURES)
+            {
+                pKernelNvlink->setProperty(pKernelNvlink, PDB_PROP_KNVLINK_ENCRYPTION_ENABLED, NV_TRUE);
+                pKernelNvlink->gspProxyRegkeys = DRF_DEF(GSP, _PROXY_REG, _NVLINK_ENCRYPTION, _ENABLE);
                 NV_PRINTF(LEVEL_INFO,
-                      "Nvlink Encryption is enabled\n");
+                          "Nvlink Encryption is enabled via regkey\n");
+                return NV_OK;
+            }
+            else
+            {
+                ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu);
+                NvBool bCCFeatureEnabled = (pCC != NULL) && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_ENABLED);
+                if (bCCFeatureEnabled)
+                {
+                    pKernelNvlink->setProperty(pKernelNvlink, PDB_PROP_KNVLINK_ENCRYPTION_ENABLED, NV_TRUE);
+                    pKernelNvlink->gspProxyRegkeys = DRF_DEF(GSP, _PROXY_REG, _NVLINK_ENCRYPTION, _ENABLE);
+                    NV_PRINTF(LEVEL_INFO,
+                              "Nvlink Encryption is enabled via regkey\n");
+                    return NV_OK;
+                }
+            }
         }
     }
 

src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c

@@ -189,6 +189,36 @@ _gpumgrDetermineConfComputeCapabilities
     return NV_OK;
 }
 
+static NV_STATUS
+_gpumgrDetermineNvlinkEncryptionCapabilities
+(
+    OBJGPUMGR *pGpuMgr,
+    OBJGPU    *pGpu
+)
+{
+    NvBool bNvlEncryptionEnabled = NV_FALSE;
+    KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu);
+    bNvlEncryptionEnabled = (pKernelNvlink != NULL) &&
+                             pKernelNvlink->getProperty(pKernelNvlink, PDB_PROP_KNVLINK_ENCRYPTION_ENABLED);
+
+    // First GPU
+    if (ONEBITSET(pGpuMgr->gpuAttachMask))
+    {
+        pGpuMgr->ccCaps.bNvlEncryptionEnabled = bNvlEncryptionEnabled;
+    }
+    else
+    {
+        //
+        // If one of the GPUs is not NVLE capable, the system as a whole
+        // is not NVLE capable
+        //
+        NV_ASSERT_OR_RETURN(pGpuMgr->ccCaps.bNvlEncryptionEnabled ==
+            bNvlEncryptionEnabled, NV_ERR_INVALID_STATE);
+    }
+
+    return NV_OK;
+}
+
 static void
 _gpumgrCacheClearMIGGpuIdInfo(NvU32 gpuId)
 {
@@ -1417,6 +1447,9 @@ gpumgrAttachGpu(NvU32 gpuInstance, GPUATTACHARG *pAttachArg)
     // Determine conf compute params
     NV_ASSERT_OK_OR_RETURN(_gpumgrDetermineConfComputeCapabilities(pGpuMgr, pGpu));
 
+    // Determine nvlink encryption params
+    NV_ASSERT_OK_OR_RETURN(_gpumgrDetermineNvlinkEncryptionCapabilities(pGpuMgr, pGpu));
+
     if (!IS_GSP_CLIENT(pGpu))
         pGpuMgr->gpuMonolithicRmMask |= NVBIT(gpuInstance);
 

src/nvidia/src/kernel/platform/cpu.c

@@ -178,6 +178,7 @@ void RmInitCpuInfo(void)
         case AARCH64_VENDOR_PART(FUJITSU, A64FX):
         case AARCH64_VENDOR_PART(PHYTIUM, FT2000):
         case AARCH64_VENDOR_PART(PHYTIUM, S2500):
+        case AARCH64_VENDOR_PART(PHYTIUM, S5000):
         case AARCH64_VENDOR_PART(AMPERE, ALTRA):
         case AARCH64_VENDOR_PART(MARVELL, OCTEON_CN96XX):
         case AARCH64_VENDOR_PART(MARVELL, OCTEON_CN98XX):

src/nvidia/src/kernel/platform/cpu_arm_def.h

@@ -88,6 +88,7 @@ extern void CP_WRITE_CSSELR_REGISTER(NvU32 val);
 #define CP_MIDR_PRIMARY_PART_NUM_A64FX         0x001
 #define CP_MIDR_PRIMARY_PART_NUM_FT2000        0x662
 #define CP_MIDR_PRIMARY_PART_NUM_S2500         0x663
+#define CP_MIDR_PRIMARY_PART_NUM_S5000         0x862
 #define CP_MIDR_PRIMARY_PART_NUM_ALTRA         0x000
 #define CP_MIDR_PRIMARY_PART_NUM_OCTEON_CN96XX 0x0b2
 #define CP_MIDR_PRIMARY_PART_NUM_OCTEON_CN98XX 0x0b1

src/nvidia/src/kernel/rmapi/client_resource.c

@@ -2541,6 +2541,7 @@ _controllerParseStaticTable_v22
 
     switch (header.version)
     {
+        case NVPCF_CONTROLLER_STATIC_TABLE_VERSION_24:
         case NVPCF_CONTROLLER_STATIC_TABLE_VERSION_23:
         case NVPCF_CONTROLLER_STATIC_TABLE_VERSION_22:
         {

version.mk

@@ -1,4 +1,4 @@
-NVIDIA_VERSION = 560.31.02
+NVIDIA_VERSION = 560.35.03
 
 # This file.
 VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))