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110 lines
4.2 KiB
110 lines
4.2 KiB
/*******************************************************************************
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Copyright (c) 2016-2019 NVIDIA Corporation
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to
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deal in the Software without restriction, including without limitation the
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rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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sell copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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DEALINGS IN THE SOFTWARE.
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*******************************************************************************/
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#ifndef __UVM_TLB_BATCH_H__
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#define __UVM_TLB_BATCH_H__
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#include "uvm_forward_decl.h"
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#include "uvm_hal_types.h"
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// Max number of separate VA ranges to track before falling back to invalidate all.
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// TLB batches take space on the stack so this number should be big enough to
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// cover our common cases, but not bigger.
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//
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// TODO: Bug 1767241: Once we have all the paths using TLB invalidates
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// implemented, verify whether it makes sense.
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#define UVM_TLB_BATCH_MAX_ENTRIES 4
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typedef struct
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{
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NvU64 start;
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NvU64 size;
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// Min and max page size ored together
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NvU32 page_sizes;
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} uvm_tlb_batch_range_t;
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struct uvm_tlb_batch_struct
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{
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uvm_page_tree_t *tree;
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union
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{
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// Total number of pages covered by the queued up ranges so far
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NvU32 total_pages;
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// Total number of ranges that have been invalidated so far
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// Each range can be invalidated using a single Host method on supported GPUs
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NvU32 total_ranges;
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};
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// Queued up ranges to invalidate
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uvm_tlb_batch_range_t ranges[UVM_TLB_BATCH_MAX_ENTRIES];
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NvU32 count;
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// Biggest page size across all queued up invalidates
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NvU32 biggest_page_size;
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// Max membar across all queued up invalidates
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uvm_membar_t membar;
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};
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// Begin a TLB invalidate batch
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void uvm_tlb_batch_begin(uvm_page_tree_t *tree, uvm_tlb_batch_t *batch);
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// Queue up an invalidate of the [start, start + size) range that will invalidate
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// all TLB cache entries for all page sizes included in the page sizes mask.
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// The smallest page size in the mask affects the density of the per VA TLB
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// invalidate (if one ends up being used) and the largest page size affects the
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// depth of the issued TLB invalidates.
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//
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// If the membar parameter is not UVM_MEMBAR_NONE, the specified membar will
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// be performed logically after the TLB invalidate such that all physical memory
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// accesses using the old translations are ordered to the scope of the membar.
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void uvm_tlb_batch_invalidate(uvm_tlb_batch_t *batch, NvU64 start, NvU64 size, NvU32 page_sizes, uvm_membar_t tlb_membar);
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// End a TLB invalidate batch
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//
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// This will push the required TLB invalidate to invalidate all the queued up
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// ranges.
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//
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// The tlb_membar argument has the same behavior as in uvm_tlb_batch_invalidate.
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// This allows callers which use the same membar for all calls to
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// uvm_tlb_batch_invalidate to pass a single membar once at the end of the
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// batch.
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void uvm_tlb_batch_end(uvm_tlb_batch_t *batch, uvm_push_t *push, uvm_membar_t tlb_membar);
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// Helper for invalidating a single range immediately.
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//
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// Internally begins and ends a TLB batch.
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static void uvm_tlb_batch_single_invalidate(uvm_page_tree_t *tree, uvm_push_t *push,
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NvU64 start, NvU64 size, NvU32 page_sizes, uvm_membar_t tlb_membar)
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{
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uvm_tlb_batch_t batch;
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uvm_tlb_batch_begin(tree, &batch);
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uvm_tlb_batch_invalidate(&batch, start, size, page_sizes, UVM_MEMBAR_NONE);
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uvm_tlb_batch_end(&batch, push, tlb_membar);
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}
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#endif // __UVM_TLB_BATCH_H__
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