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tinygo/targets/riscv.ld

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all: add HiFive1 rev B board with RISC-V architecture This page has been a big help in adding support for this new chip: https://wiki.osdev.org/HiFive-1_Bare_Bones
6 years ago
SECTIONS
{
.text :
{
riscv: add bare-bones interrupt support This commit adds support for timer interrupts, replacing the busy loop that was used before. It is perhaps the most simple interrupt to implement and should serve as the basis for further interrupt support in RISC-V.
5 years ago
. = ALIGN(4);
all: add HiFive1 rev B board with RISC-V architecture This page has been a big help in adding support for this new chip: https://wiki.osdev.org/HiFive-1_Bare_Bones
6 years ago
KEEP(*(.init))
riscv: add bare-bones interrupt support This commit adds support for timer interrupts, replacing the busy loop that was used before. It is perhaps the most simple interrupt to implement and should serve as the basis for further interrupt support in RISC-V.
5 years ago
. = ALIGN(4);
*(.text.handleInterruptASM)
all: add HiFive1 rev B board with RISC-V architecture This page has been a big help in adding support for this new chip: https://wiki.osdev.org/HiFive-1_Bare_Bones
6 years ago
*(.text)
*(.text.*)
*(.rodata)
*(.rodata.*)
. = ALIGN(4);
} >FLASH_TEXT
/* Put the stack at the bottom of RAM, so that the application will
* crash on stack overflow instead of silently corrupting memory.
* See: http://blog.japaric.io/stack-overflow-protection/ */
targets: explicitly mark the stack as NOLOAD This prevents it from being of type PROGBITS in lld 9, it should always be NOBITS. It should fix the following error in lld 9: ROM segments are non-contiguous
5 years ago
.stack (NOLOAD) :
all: add HiFive1 rev B board with RISC-V architecture This page has been a big help in adding support for this new chip: https://wiki.osdev.org/HiFive-1_Bare_Bones
6 years ago
{
riscv: align stack and data sections to 8 bytes Alignment on 4 bytes can cause load/store address misalignment exceptions when loading/storing 64bit values on the stack.
4 years ago
. = ALIGN(8);
all: add HiFive1 rev B board with RISC-V architecture This page has been a big help in adding support for this new chip: https://wiki.osdev.org/HiFive-1_Bare_Bones
6 years ago
. += _stack_size;
_stack_top = .;
} >RAM
/* Start address (in flash) of .data, used by startup code. */
_sidata = LOADADDR(.data);
/* Globals with initial value */
.data :
{
riscv: align stack and data sections to 8 bytes Alignment on 4 bytes can cause load/store address misalignment exceptions when loading/storing 64bit values on the stack.
4 years ago
. = ALIGN(8);
all: add HiFive1 rev B board with RISC-V architecture This page has been a big help in adding support for this new chip: https://wiki.osdev.org/HiFive-1_Bare_Bones
6 years ago
/* see https://gnu-mcu-eclipse.github.io/arch/riscv/programmer/#the-gp-global-pointer-register */
PROVIDE( __global_pointer$ = . + (4K / 2) );
_sdata = .; /* used by startup code */
riscv: fix heap corruption The .sdata and .sbss sections are created by the compiler, but were not present in the linker script. That means that the linker put them after all other data/bss section, which happens to be where the heap also resides. This commit adds the .sdata and .sbss sections to the linker script, which gets the blinky examples to work again on RISC-V.
5 years ago
*(.sdata)
*(.data .data.*)
riscv: align stack and data sections to 8 bytes Alignment on 4 bytes can cause load/store address misalignment exceptions when loading/storing 64bit values on the stack.
4 years ago
. = ALIGN(8);
all: add HiFive1 rev B board with RISC-V architecture This page has been a big help in adding support for this new chip: https://wiki.osdev.org/HiFive-1_Bare_Bones
6 years ago
_edata = .; /* used by startup code */
} >RAM AT>FLASH_TEXT
/* Zero-initialized globals */
.bss :
{
riscv: align stack and data sections to 8 bytes Alignment on 4 bytes can cause load/store address misalignment exceptions when loading/storing 64bit values on the stack.
4 years ago
. = ALIGN(8);
all: add HiFive1 rev B board with RISC-V architecture This page has been a big help in adding support for this new chip: https://wiki.osdev.org/HiFive-1_Bare_Bones
6 years ago
_sbss = .; /* used by startup code */
riscv: fix heap corruption The .sdata and .sbss sections are created by the compiler, but were not present in the linker script. That means that the linker put them after all other data/bss section, which happens to be where the heap also resides. This commit adds the .sdata and .sbss sections to the linker script, which gets the blinky examples to work again on RISC-V.
5 years ago
*(.sbss)
*(.bss .bss.*)
all: add HiFive1 rev B board with RISC-V architecture This page has been a big help in adding support for this new chip: https://wiki.osdev.org/HiFive-1_Bare_Bones
6 years ago
*(COMMON)
riscv: align stack and data sections to 8 bytes Alignment on 4 bytes can cause load/store address misalignment exceptions when loading/storing 64bit values on the stack.
4 years ago
. = ALIGN(8);
all: add HiFive1 rev B board with RISC-V architecture This page has been a big help in adding support for this new chip: https://wiki.osdev.org/HiFive-1_Bare_Bones
6 years ago
_ebss = .; /* used by startup code */
} >RAM
riscv: use LLVM tools instead of GNU toolchain Now that we use LLVM 9, RISC-V support in LLVM has far fewer bugs and we can avoid the GNU toolchain. * replace GNU linker with lld * replace GCC with clang Additionally, RISC-V was promoted to stable so it can be enabled by default in CI.
5 years ago
/DISCARD/ :
{
*(.eh_frame) /* causes 'no memory region specified' error in lld */
}
all: add HiFive1 rev B board with RISC-V architecture This page has been a big help in adding support for this new chip: https://wiki.osdev.org/HiFive-1_Bare_Bones
6 years ago
}
/* For the memory allocator. */
_heap_start = _ebss;
_heap_end = ORIGIN(RAM) + LENGTH(RAM);
_globals_start = _sdata;
_globals_end = _ebss;