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tinygo/targets/riscv.json

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all: add HiFive1 rev B board with RISC-V architecture This page has been a big help in adding support for this new chip: https://wiki.osdev.org/HiFive-1_Bare_Bones
6 years ago
{
"llvm-target": "riscv32--none",
"goos": "linux",
"goarch": "arm",
all: use baremetal build tag This simplifies adding more baremetal targets, like a GameBoy Advance, or baremetal x86 for unikernels.
5 years ago
"build-tags": ["tinygo.riscv", "baremetal", "linux", "arm"],
all: add HiFive1 rev B board with RISC-V architecture This page has been a big help in adding support for this new chip: https://wiki.osdev.org/HiFive-1_Bare_Bones
6 years ago
"gc": "conservative",
riscv: use LLVM tools instead of GNU toolchain Now that we use LLVM 9, RISC-V support in LLVM has far fewer bugs and we can avoid the GNU toolchain. * replace GNU linker with lld * replace GCC with clang Additionally, RISC-V was promoted to stable so it can be enabled by default in CI.
5 years ago
"compiler": "clang",
"linker": "ld.lld",
riscv: add support for compiler-rt This gets all the tests to compile and many of them to pass. There are some issues left, but those are probably unrelated to compiler-rt.
5 years ago
"rtlib": "compiler-rt",
all: add HiFive1 rev B board with RISC-V architecture This page has been a big help in adding support for this new chip: https://wiki.osdev.org/HiFive-1_Bare_Bones
6 years ago
"cflags": [
riscv: use LLVM tools instead of GNU toolchain Now that we use LLVM 9, RISC-V support in LLVM has far fewer bugs and we can avoid the GNU toolchain. * replace GNU linker with lld * replace GCC with clang Additionally, RISC-V was promoted to stable so it can be enabled by default in CI.
5 years ago
"--target=riscv32--none",
all: add HiFive1 rev B board with RISC-V architecture This page has been a big help in adding support for this new chip: https://wiki.osdev.org/HiFive-1_Bare_Bones
6 years ago
"-march=rv32imac",
"-mabi=ilp32",
"-Os",
"-Werror",
"-nostdinc",
"-fno-exceptions", "-fno-unwind-tables",
"-ffunction-sections", "-fdata-sections"
],
"ldflags": [
"-melf32lriscv",
"--gc-sections"
],
"extra-files": [
"src/device/riscv/start.S"
targets: add hifive1-qemu for testing RISC-V bare metal in QEMU Most tests don't pass yet, so can't add this test to the standard tests, yet.
5 years ago
],
"gdb": "riscv64-unknown-elf-gdb"
all: add HiFive1 rev B board with RISC-V architecture This page has been a big help in adding support for this new chip: https://wiki.osdev.org/HiFive-1_Bare_Bones
6 years ago
}