mirror of https://github.com/tinygo-org/tinygo.git
Browse Source
This is only very minimal support. More support (such as tinygo flash, or peripheral access) should be added in later commits, to keep this one focused. Importantly, this commit changes the LLVM repo from llvm/llvm-project to tinygo-org/llvm-project. This provides a little bit of versioning in case something changes in the Espressif fork. If we want to upgrade to LLVM 11 it's easy to switch back to llvm/llvm-project until Espressif has updated their fork.pull/1324/head
Ayke van Laethem
4 years ago
committed by
Ron Evans
Ron Evans
15 changed files with 520 additions and 39 deletions
@ -1 +1 @@ |
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Subproject commit a155cfd832c9e6ddf193244d8d90489f4d089cc7 |
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Subproject commit 2fc335802cf97309ec4035caf276746b53efbd5b |
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@ -0,0 +1,52 @@ |
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|
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// The following definitions were copied from: |
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// esp-idf/components/xtensa/include/xtensa/corebits.h |
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#define PS_WOE_MASK 0x00040000 |
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#define PS_OWB_MASK 0x00000F00 |
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#define PS_CALLINC_MASK 0x00030000 |
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#define PS_WOE PS_WOE_MASK |
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|
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// Only calling it call_start_cpu0 for consistency with ESP-IDF. |
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.section .text.call_start_cpu0 |
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1: |
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.long _stack_top |
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.global call_start_cpu0 |
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call_start_cpu0: |
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// We need to set the stack pointer to a different value. This is somewhat |
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// complicated in the Xtensa architecture. The code below is a modified |
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// version of the following code: |
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// https://github.com/espressif/esp-idf/blob/c77c4ccf/components/xtensa/include/xt_instr_macros.h#L47 |
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|
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// Disable WOE. |
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rsr.ps a2 |
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movi a3, ~(PS_WOE_MASK) |
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and a2, a2, a3 |
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wsr.ps a2 |
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rsync |
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|
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// Set WINDOWBASE to 1 << WINDOWSTART. |
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rsr.windowbase a2 |
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ssl a2 |
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movi a2, 1 |
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sll a2, a2 |
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wsr.windowstart a2 |
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rsync |
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|
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// Load new stack pointer. |
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l32r sp, 1b |
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|
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// Re-enable WOE. |
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rsr.ps a2 |
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movi a3, PS_WOE |
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or a2, a2, a3 |
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wsr.ps a2 |
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rsync |
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|
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// Jump to the runtime start function written in Go. |
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j main |
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|
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.section .text.tinygo_scanCurrentStack |
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.global tinygo_scanCurrentStack |
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tinygo_scanCurrentStack: |
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// TODO: save callee saved registers on the stack |
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j tinygo_scanstack |
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@ -0,0 +1,44 @@ |
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// +build esp32
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|
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package machine |
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import "device/esp" |
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|
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const peripheralClock = 80000000 // 80MHz
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|
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type PinMode uint8 |
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const ( |
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PinOutput PinMode = iota |
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PinInput |
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) |
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|
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func (p Pin) Set(value bool) |
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|
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var ( |
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UART0 = UART{Bus: esp.UART0, Buffer: NewRingBuffer()} |
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UART1 = UART{Bus: esp.UART1, Buffer: NewRingBuffer()} |
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UART2 = UART{Bus: esp.UART2, Buffer: NewRingBuffer()} |
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) |
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|
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type UART struct { |
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Bus *esp.UART_Type |
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Buffer *RingBuffer |
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} |
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|
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func (uart UART) Configure(config UARTConfig) { |
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if config.BaudRate == 0 { |
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config.BaudRate = 115200 |
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} |
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uart.Bus.CLKDIV.Set(peripheralClock / config.BaudRate) |
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} |
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|
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func (uart UART) WriteByte(b byte) error { |
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for (uart.Bus.STATUS.Get()>>16)&0xff >= 128 { |
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// Read UART_TXFIFO_CNT from the status register, which indicates how
|
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// many bytes there are in the transmit buffer. Wait until there are
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// less than 128 bytes in this buffer (the default buffer size).
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} |
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uart.Bus.TX_FIFO.Set(b) |
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return nil |
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} |
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@ -0,0 +1,15 @@ |
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// +build xtensa
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|
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package runtime |
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const GOARCH = "arm" // xtensa pretends to be arm
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|
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// The bitness of the CPU (e.g. 8, 32, 64).
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const TargetBits = 32 |
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|
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// Align on a word boundary.
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func align(ptr uintptr) uintptr { |
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return (ptr + 3) &^ 3 |
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} |
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|
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func getCurrentStackPointer() uintptr |
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@ -0,0 +1,31 @@ |
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// +build xtensa
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package interrupt |
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import "device" |
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// State represents the previous global interrupt state.
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type State uintptr |
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// Disable disables all interrupts and returns the previous interrupt state. It
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// can be used in a critical section like this:
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//
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// state := interrupt.Disable()
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// // critical section
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// interrupt.Restore(state)
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//
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// Critical sections can be nested. Make sure to call Restore in the same order
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// as you called Disable (this happens naturally with the pattern above).
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func Disable() (state State) { |
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return State(device.AsmFull("rsil {}, 15", nil)) |
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} |
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|
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// Restore restores interrupts to what they were before. Give the previous state
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// returned by Disable as a parameter. If interrupts were disabled before
|
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// calling Disable, this will not re-enable interrupts, allowing for nested
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// cricital sections.
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func Restore(state State) { |
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device.AsmFull("wsr {state}, PS", map[string]interface{}{ |
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"state": state, |
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}) |
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} |
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@ -0,0 +1,126 @@ |
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// +build esp32
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|
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package runtime |
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import ( |
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"device" |
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"device/esp" |
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"machine" |
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"unsafe" |
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) |
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|
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type timeUnit int64 |
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|
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var currentTime timeUnit |
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|
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func putchar(c byte) { |
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machine.UART0.WriteByte(c) |
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} |
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|
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func postinit() {} |
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|
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// This is the function called on startup right after the stack pointer has been
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// set.
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//export main
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func main() { |
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// Disable both watchdog timers that are enabled by default on startup.
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// Note that these watchdogs can be protected, but the ROM bootloader
|
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// doesn't seem to protect them.
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esp.RTCCNTL.WDTCONFIG0.Set(0) |
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esp.TIMG0.WDTCONFIG0.Set(0) |
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|
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// Switch SoC clock source to PLL (instead of the default which is XTAL).
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// This switches the CPU (and APB) clock from 40MHz to 80MHz.
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// Options:
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// RTCCNTL_CLK_CONF_SOC_CLK_SEL: PLL (default XTAL)
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// RTCCNTL_CLK_CONF_CK8M_DIV_SEL: 2 (default)
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// RTCCNTL_CLK_CONF_DIG_CLK8M_D256_EN: Enable (default)
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// RTCCNTL_CLK_CONF_CK8M_DIV: DIV256 (default)
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// The only real change made here is modifying RTCCNTL_CLK_CONF_SOC_CLK_SEL,
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// but setting a fixed value produces smaller code.
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esp.RTCCNTL.CLK_CONF.Set((esp.RTCCNTL_CLK_CONF_SOC_CLK_SEL_PLL << esp.RTCCNTL_CLK_CONF_SOC_CLK_SEL_Pos) | |
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(2 << esp.RTCCNTL_CLK_CONF_CK8M_DIV_SEL_Pos) | |
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(esp.RTCCNTL_CLK_CONF_DIG_CLK8M_D256_EN_Enable << esp.RTCCNTL_CLK_CONF_DIG_CLK8M_D256_EN_Pos) | |
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(esp.RTCCNTL_CLK_CONF_CK8M_DIV_DIV256 << esp.RTCCNTL_CLK_CONF_CK8M_DIV_Pos)) |
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|
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// Switch CPU from 80MHz to 160MHz. This doesn't affect the APB clock,
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// which is still running at 80MHz.
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esp.DPORT.CPU_PER_CONF.Set(esp.DPORT_CPU_PER_CONF_CPUPERIOD_SEL_SEL_160) |
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// Clear .bss section. .data has already been loaded by the ROM bootloader.
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// Do this after increasing the CPU clock to possibly make startup slightly
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// faster.
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preinit() |
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// Initialize UART.
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machine.UART0.Configure(machine.UARTConfig{}) |
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// Configure timer 0 in timer group 0, for timekeeping.
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// EN: Enable the timer.
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// INCREASE: Count up every tick (as opposed to counting down).
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// DIVIDER: 16-bit prescaler, set to 2 for dividing the APB clock by two
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// (40MHz).
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esp.TIMG0.T0CONFIG.Set(esp.TIMG_T0CONFIG_T0_EN | esp.TIMG_T0CONFIG_T0_INCREASE | 2<<esp.TIMG_T0CONFIG_T0_DIVIDER_Pos) |
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|
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// Set the timer counter value to 0.
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esp.TIMG0.T0LOADLO.Set(0) |
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esp.TIMG0.T0LOADHI.Set(0) |
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esp.TIMG0.T0LOAD.Set(0) // value doesn't matter.
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run() |
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// Fallback: if main ever returns, hang the CPU.
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abort() |
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} |
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|
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//go:extern _sbss
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var _sbss [0]byte |
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|
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//go:extern _ebss
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var _ebss [0]byte |
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func preinit() { |
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// Initialize .bss: zero-initialized global variables.
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// The .data section has already been loaded by the ROM bootloader.
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ptr := unsafe.Pointer(&_sbss) |
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for ptr != unsafe.Pointer(&_ebss) { |
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*(*uint32)(ptr) = 0 |
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ptr = unsafe.Pointer(uintptr(ptr) + 4) |
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} |
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} |
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|
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func ticks() timeUnit { |
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// First, update the LO and HI register pair by writing any value to the
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// register. This allows reading the pair atomically.
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esp.TIMG0.T0UPDATE.Set(0) |
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// Then read the two 32-bit parts of the timer.
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return timeUnit(uint64(esp.TIMG0.T0LO.Get()) | uint64(esp.TIMG0.T0HI.Get())<<32) |
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} |
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|
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const asyncScheduler = false |
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func nanosecondsToTicks(ns int64) timeUnit { |
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// Calculate the number of ticks from the number of nanoseconds. At a 80MHz
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// APB clock, that's 25 nanoseconds per tick with a timer prescaler of 2:
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// 25 = 1e9 / (80MHz / 2)
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return timeUnit(ns / 25) |
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} |
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|
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func ticksToNanoseconds(ticks timeUnit) int64 { |
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// See nanosecondsToTicks.
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return int64(ticks) * 25 |
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} |
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|
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// sleepTicks busy-waits until the given number of ticks have passed.
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func sleepTicks(d timeUnit) { |
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sleepUntil := ticks() + d |
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for ticks() < sleepUntil { |
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// TODO: suspend the CPU to not burn power here unnecessarily.
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} |
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} |
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|
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func abort() { |
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for { |
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device.Asm("waiti 0") |
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} |
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} |
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@ -0,0 +1,13 @@ |
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{ |
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"inherits": ["xtensa"], |
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"cpu": "esp32", |
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"build-tags": ["esp32", "esp"], |
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"linker": "xtensa-esp32-elf-ld", |
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"cflags": [ |
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"-mcpu=esp32" |
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], |
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"linkerscript": "targets/esp32.ld", |
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"extra-files": [ |
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"src/device/esp/esp32.S" |
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] |
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} |
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@ -0,0 +1,104 @@ |
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/* Linker script for the ESP32 */ |
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MEMORY |
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{ |
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/* Data RAM. Allows byte access. |
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* There are various data RAM regions: |
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* SRAM2: 0x3FFA_E000..0x3FFD_FFFF (72 + 128 = 200K) |
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* SRAM1: 0x3FFE_0000..0x3FFF_FFFF (128K) |
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* This gives us 328K of contiguous RAM, which is the largest span possible. |
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* SRAM1 has other addresses as well but the datasheet seems to indicate |
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* these are aliases. |
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*/ |
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DRAM (rw) : ORIGIN = 0x3FFAE000, LENGTH = 200K + 128K /* Internal SRAM 1 + 2 */ |
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/* Instruction RAM. */ |
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IRAM (x) : ORIGIN = 0x40080000, LENGTH = 128K /* Internal SRAM 0 */ |
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} |
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|
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/* The entry point. It is set in the image flashed to the chip, so must be |
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* defined. |
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*/ |
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ENTRY(call_start_cpu0) |
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|
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SECTIONS |
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{ |
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/* Constant literals and code. Loaded into IRAM for now. Eventually, most |
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* code should be executed directly from flash. |
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* Note that literals must be before code for the l32r instruction to work. |
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*/ |
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.text : ALIGN(4) |
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{ |
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*(.literal.text.call_start_cpu0) |
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*(.text.call_start_cpu0) |
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*(.literal .text) |
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*(.literal.* .text.*) |
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} >IRAM |
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|
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/* Put the stack at the bottom of DRAM, so that the application will |
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* crash on stack overflow instead of silently corrupting memory. |
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* See: http://blog.japaric.io/stack-overflow-protection/ */ |
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.stack (NOLOAD) : |
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{ |
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. = ALIGN(16); |
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. += _stack_size; |
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_stack_top = .; |
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} >DRAM |
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|
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/* Constant global variables. |
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* They are loaded in DRAM for ease of use. Eventually they should be stored |
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* in flash and loaded directly from there but they're kept in RAM to make |
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* sure they can always be accessed (even in interrupts). |
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*/ |
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.rodata : ALIGN(4) |
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{ |
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*(.rodata) |
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*(.rodata.*) |
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} >DRAM |
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|
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/* Mutable global variables. |
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*/ |
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.data : ALIGN(4) |
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{ |
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_sdata = ABSOLUTE(.); |
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*(.data) |
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*(.data.*) |
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_edata = ABSOLUTE(.); |
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} >DRAM |
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|
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/* Check that the boot ROM stack (for the APP CPU) does not overlap with the |
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* data that is loaded by the boot ROM. There may be ways to avoid this |
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* issue if it occurs in practice. |
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* The magic value here is _stack_sentry in the boot ROM ELF file. |
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*/ |
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ASSERT(_edata < 0x3ffe1320, "the .data section overlaps with the stack used by the boot ROM, possibly causing corruption at startup") |
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|
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/* Global variables that are mutable and zero-initialized. |
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* These must be zeroed at startup (unlike data, which is loaded by the |
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* bootloader). |
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*/ |
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.bss (NOLOAD) : ALIGN(4) |
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{ |
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. = ALIGN (4); |
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_sbss = ABSOLUTE(.); |
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*(.bss) |
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*(.bss.*) |
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. = ALIGN (4); |
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_ebss = ABSOLUTE(.); |
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} >DRAM |
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} |
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|
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/* For the garbage collector. |
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*/ |
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_globals_start = _sdata; |
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_globals_end = _ebss; |
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_heap_start = _ebss; |
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_heap_end = ORIGIN(DRAM) + LENGTH(DRAM); |
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|
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_stack_size = 4K; |
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|
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/* From ESP-IDF, included here as long as picolibc doesn't compile. |
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*/ |
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memcpy = 0x4000c2c8; |
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memset = 0x4000c44c; |
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__udivdi3 = 0x4000cff8; |
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@ -0,0 +1,22 @@ |
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{ |
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"llvm-target": "xtensa", |
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"goos": "linux", |
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"goarch": "arm", |
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"build-tags": ["xtensa", "baremetal", "linux", "arm"], |
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"gc": "conservative", |
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"scheduler": "none", |
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"compiler": "clang", |
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"cflags": [ |
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"--target=xtensa", |
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"-Oz", |
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"-Werror", |
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"-fshort-enums", |
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"-Wno-macro-redefined", |
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"-Qunused-arguments", |
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"-fno-exceptions", "-fno-unwind-tables", |
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"-ffunction-sections", "-fdata-sections" |
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], |
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"ldflags": [ |
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"--gc-sections" |
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] |
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} |
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Reference in new issue