From 3f89fa0bee72a282e1221c353c0a932e9f805970 Mon Sep 17 00:00:00 2001
From: Ayke van Laethem <aykevanlaethem@gmail.com>
Date: Wed, 20 Oct 2021 02:14:49 +0200
Subject: [PATCH] fe310: increase CPU frequency from 16MHz to 320MHz

This chip can run so much faster! Let's update the default frequency.

Also, change the UART implementation to be more fexible regarding the
clock frequency.
---
 src/machine/machine_fe310.go | 16 ++++++++++++----
 src/runtime/runtime_fe310.go | 12 ++++++------
 2 files changed, 18 insertions(+), 10 deletions(-)

diff --git a/src/machine/machine_fe310.go b/src/machine/machine_fe310.go
index ebd85971..ffad20de 100644
--- a/src/machine/machine_fe310.go
+++ b/src/machine/machine_fe310.go
@@ -9,7 +9,7 @@ import (
 )
 
 func CPUFrequency() uint32 {
-	return 16000000
+	return 320000000 // 320MHz
 }
 
 const (
@@ -61,9 +61,17 @@ var (
 )
 
 func (uart *UART) Configure(config UARTConfig) {
-	// Assuming a 16Mhz Crystal (which is Y1 on the HiFive1), the divisor for a
-	// 115200 baud rate is 138.
-	sifive.UART0.DIV.Set(138)
+	if config.BaudRate == 0 {
+		config.BaudRate = 115200
+	}
+	// The divisor is:
+	//   fbaud = fin / (div + 1)
+	// Restating to get the divisor:
+	//   div = fin / fbaud - 1
+	// But we're using integers, so we should take care of rounding:
+	//   div = (fin + fbaud/2) / fbaud - 1
+	divisor := (CPUFrequency()+config.BaudRate/2)/config.BaudRate - 1
+	sifive.UART0.DIV.Set(divisor)
 	sifive.UART0.TXCTRL.Set(sifive.UART_TXCTRL_ENABLE)
 	sifive.UART0.RXCTRL.Set(sifive.UART_RXCTRL_ENABLE)
 	sifive.UART0.IE.Set(sifive.UART_IE_RXWM) // enable the receive interrupt (only)
diff --git a/src/runtime/runtime_fe310.go b/src/runtime/runtime_fe310.go
index 2163fb0f..5cfa7a69 100644
--- a/src/runtime/runtime_fe310.go
+++ b/src/runtime/runtime_fe310.go
@@ -79,12 +79,12 @@ func handleInterrupt() {
 
 // initPeripherals configures periperhals the way the runtime expects them.
 func initPeripherals() {
-	// Make sure the HFROSC is on
-	sifive.PRCI.HFROSCCFG.SetBits(sifive.PRCI_HFROSCCFG_ENABLE)
-
-	// Run off 16 MHz Crystal for accuracy.
-	sifive.PRCI.PLLCFG.SetBits(sifive.PRCI_PLLCFG_REFSEL | sifive.PRCI_PLLCFG_BYPASS)
-	sifive.PRCI.PLLCFG.SetBits(sifive.PRCI_PLLCFG_SEL)
+	// Configure PLL to output 320MHz.
+	//   R=2:  divide 16MHz to 8MHz
+	//   F=80: multiply 8MHz by 80 to get 640MHz (80/2-1=39)
+	//   Q=2:  divide 640MHz by 2 to get 320MHz
+	// This makes the main CPU run at 320MHz.
+	sifive.PRCI.PLLCFG.Set(sifive.PRCI_PLLCFG_PLLR_R2<<sifive.PRCI_PLLCFG_PLLR_Pos | 39<<sifive.PRCI_PLLCFG_PLLF_Pos | sifive.PRCI_PLLCFG_PLLQ_Q2<<sifive.PRCI_PLLCFG_PLLQ_Pos | sifive.PRCI_PLLCFG_SEL | sifive.PRCI_PLLCFG_REFSEL)
 
 	// Turn off HFROSC to save power
 	sifive.PRCI.HFROSCCFG.ClearBits(sifive.PRCI_HFROSCCFG_ENABLE)