Nucleo f722ze (#1526)

machine/nucleo-f722ze: Add support for ST Micro NUCLEO-F722ZE

Makefile

@@ -319,6 +319,8 @@ smoketest:
 	@$(MD5SUM) test.hex
 	$(TINYGO) build -size short -o test.hex -target=teensy36            examples/blinky1
 	@$(MD5SUM) test.hex
+	$(TINYGO) build -size short -o test.hex -target=nucleo-f722ze       examples/blinky1
+	@$(MD5SUM) test.hex
 	# test pwm
 	$(TINYGO) build -size short -o test.hex -target=itsybitsy-m0        examples/pwm
 	@$(MD5SUM) test.hex

src/machine/board_nucleof722ze.go

@@ -0,0 +1,58 @@
+// +build nucleof722ze
+
+package machine
+
+import (
+	"device/stm32"
+	"runtime/interrupt"
+)
+
+const (
+	LED         = LED_BUILTIN
+	LED_BUILTIN = LED_GREEN
+	LED_GREEN   = PB0
+	LED_BLUE    = PB7
+	LED_RED     = PB14
+)
+
+const (
+	BUTTON      = BUTTON_USER
+	BUTTON_USER = PC13
+)
+
+// UART pins
+const (
+	// PD8 and PD9 are connected to the ST-Link Virtual Com Port (VCP)
+	UART_TX_PIN = PD8
+	UART_RX_PIN = PD9
+	UART_ALT_FN = 7 // GPIO_AF7_UART3
+)
+
+var (
+	// USART3 is the hardware serial port connected to the onboard ST-LINK
+	// debugger to be exposed as virtual COM port over USB on Nucleo boards.
+	// Both UART0 and UART1 refer to USART2.
+	UART0 = UART{
+		Buffer:          NewRingBuffer(),
+		Bus:             stm32.USART3,
+		AltFuncSelector: UART_ALT_FN,
+	}
+	UART1 = &UART0
+)
+
+func init() {
+	UART0.Interrupt = interrupt.New(stm32.IRQ_USART3, UART0.handleInterrupt)
+}
+
+// SPI pins
+const (
+	SPI0_SCK_PIN = PA5
+	SPI0_SDI_PIN = PA6
+	SPI0_SDO_PIN = PA7
+)
+
+// I2C pins
+const (
+	SCL_PIN = PB6
+	SDA_PIN = PB7
+)

src/machine/i2c.go

@@ -1,4 +1,4 @@
-// +build avr nrf sam stm32,!stm32f407 fe310 k210
+// +build avr nrf sam stm32,!stm32f407,!stm32f7x2 fe310 k210
 
 package machine
 

src/machine/machine_stm32_f7_uart.go

@@ -0,0 +1,62 @@
+// +build stm32f7
+
+package machine
+
+// Peripheral abstraction layer for UARTs on the stm32 family.
+
+import (
+	"device/stm32"
+	"runtime/interrupt"
+	"unsafe"
+)
+
+// Configure the UART.
+func (uart UART) Configure(config UARTConfig) {
+	// Default baud rate to 115200.
+	if config.BaudRate == 0 {
+		config.BaudRate = 115200
+	}
+
+	// Set the GPIO pins to defaults if they're not set
+	if config.TX == 0 && config.RX == 0 {
+		config.TX = UART_TX_PIN
+		config.RX = UART_RX_PIN
+	}
+
+	// Enable USART clock
+	enableAltFuncClock(unsafe.Pointer(uart.Bus))
+
+	uart.configurePins(config)
+
+	// Set baud rate
+	uart.SetBaudRate(config.BaudRate)
+
+	// Enable USART port, tx, rx and rx interrupts
+	uart.Bus.CR1.Set(stm32.USART_CR1_TE | stm32.USART_CR1_RE | stm32.USART_CR1_RXNEIE | stm32.USART_CR1_UE)
+
+	// Enable RX IRQ
+	uart.Interrupt.SetPriority(0xc0)
+	uart.Interrupt.Enable()
+}
+
+// handleInterrupt should be called from the appropriate interrupt handler for
+// this UART instance.
+func (uart *UART) handleInterrupt(interrupt.Interrupt) {
+	uart.Receive(byte((uart.Bus.RDR.Get() & 0xFF)))
+}
+
+// SetBaudRate sets the communication speed for the UART. Defer to chip-specific
+// routines for calculation
+func (uart UART) SetBaudRate(br uint32) {
+	divider := uart.getBaudRateDivisor(br)
+	uart.Bus.BRR.Set(divider)
+}
+
+// WriteByte writes a byte of data to the UART.
+func (uart UART) WriteByte(c byte) error {
+	uart.Bus.TDR.Set(uint32(c))
+
+	for !uart.Bus.ISR.HasBits(stm32.USART_ISR_TXE) {
+	}
+	return nil
+}

src/machine/machine_stm32_i2c.go

@@ -1,4 +1,4 @@
-// +build stm32,!stm32f103xx,!stm32f407
+// +build stm32,!stm32f103xx,!stm32f407,!stm32f7x2
 
 package machine
 

src/machine/machine_stm32_spi.go

@@ -1,4 +1,4 @@
-// +build stm32
+// +build stm32,!stm32f7x2
 
 package machine
 

src/machine/machine_stm32_uart.go

@@ -1,4 +1,4 @@
-// +build stm32
+// +build stm32,!stm32f7
 
 package machine
 

src/machine/machine_stm32f7.go

@@ -0,0 +1,259 @@
+// +build stm32f7
+
+package machine
+
+// Peripheral abstraction layer for the stm32f4
+
+import (
+	"device/stm32"
+	"unsafe"
+)
+
+const (
+	PA0  = portA + 0
+	PA1  = portA + 1
+	PA2  = portA + 2
+	PA3  = portA + 3
+	PA4  = portA + 4
+	PA5  = portA + 5
+	PA6  = portA + 6
+	PA7  = portA + 7
+	PA8  = portA + 8
+	PA9  = portA + 9
+	PA10 = portA + 10
+	PA11 = portA + 11
+	PA12 = portA + 12
+	PA13 = portA + 13
+	PA14 = portA + 14
+	PA15 = portA + 15
+
+	PB0  = portB + 0
+	PB1  = portB + 1
+	PB2  = portB + 2
+	PB3  = portB + 3
+	PB4  = portB + 4
+	PB5  = portB + 5
+	PB6  = portB + 6
+	PB7  = portB + 7
+	PB8  = portB + 8
+	PB9  = portB + 9
+	PB10 = portB + 10
+	PB11 = portB + 11
+	PB12 = portB + 12
+	PB13 = portB + 13
+	PB14 = portB + 14
+	PB15 = portB + 15
+
+	PC0  = portC + 0
+	PC1  = portC + 1
+	PC2  = portC + 2
+	PC3  = portC + 3
+	PC4  = portC + 4
+	PC5  = portC + 5
+	PC6  = portC + 6
+	PC7  = portC + 7
+	PC8  = portC + 8
+	PC9  = portC + 9
+	PC10 = portC + 10
+	PC11 = portC + 11
+	PC12 = portC + 12
+	PC13 = portC + 13
+	PC14 = portC + 14
+	PC15 = portC + 15
+
+	PD0  = portD + 0
+	PD1  = portD + 1
+	PD2  = portD + 2
+	PD3  = portD + 3
+	PD4  = portD + 4
+	PD5  = portD + 5
+	PD6  = portD + 6
+	PD7  = portD + 7
+	PD8  = portD + 8
+	PD9  = portD + 9
+	PD10 = portD + 10
+	PD11 = portD + 11
+	PD12 = portD + 12
+	PD13 = portD + 13
+	PD14 = portD + 14
+	PD15 = portD + 15
+
+	PE0  = portE + 0
+	PE1  = portE + 1
+	PE2  = portE + 2
+	PE3  = portE + 3
+	PE4  = portE + 4
+	PE5  = portE + 5
+	PE6  = portE + 6
+	PE7  = portE + 7
+	PE8  = portE + 8
+	PE9  = portE + 9
+	PE10 = portE + 10
+	PE11 = portE + 11
+	PE12 = portE + 12
+	PE13 = portE + 13
+	PE14 = portE + 14
+	PE15 = portE + 15
+
+	PF0  = portF + 0
+	PF1  = portF + 1
+	PF2  = portF + 2
+	PF3  = portF + 3
+	PF4  = portF + 4
+	PF5  = portF + 5
+	PF6  = portF + 6
+	PF7  = portF + 7
+	PF8  = portF + 8
+	PF9  = portF + 9
+	PF10 = portF + 10
+	PF11 = portF + 11
+	PF12 = portF + 12
+	PF13 = portF + 13
+	PF14 = portF + 14
+	PF15 = portF + 15
+
+	PG0  = portG + 0
+	PG1  = portG + 1
+	PG2  = portG + 2
+	PG3  = portG + 3
+	PG4  = portG + 4
+	PG5  = portG + 5
+	PG6  = portG + 6
+	PG7  = portG + 7
+	PG8  = portG + 8
+	PG9  = portG + 9
+	PG10 = portG + 10
+	PG11 = portG + 11
+	PG12 = portG + 12
+	PG13 = portG + 13
+	PG14 = portG + 14
+	PG15 = portG + 15
+
+	PH0 = portH + 0
+	PH1 = portH + 1
+)
+
+func (p Pin) getPort() *stm32.GPIO_Type {
+	switch p / 16 {
+	case 0:
+		return stm32.GPIOA
+	case 1:
+		return stm32.GPIOB
+	case 2:
+		return stm32.GPIOC
+	case 3:
+		return stm32.GPIOD
+	case 4:
+		return stm32.GPIOE
+	case 5:
+		return stm32.GPIOF
+	case 6:
+		return stm32.GPIOG
+	case 7:
+		return stm32.GPIOH
+	case 8:
+		return stm32.GPIOI
+	default:
+		panic("machine: unknown port")
+	}
+}
+
+// enableClock enables the clock for this desired GPIO port.
+func (p Pin) enableClock() {
+	switch p / 16 {
+	case 0:
+		stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOAEN)
+	case 1:
+		stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOBEN)
+	case 2:
+		stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOCEN)
+	case 3:
+		stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIODEN)
+	case 4:
+		stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOEEN)
+	case 5:
+		stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOFEN)
+	case 6:
+		stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOGEN)
+	case 7:
+		stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOHEN)
+	case 8:
+		stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOIEN)
+	default:
+		panic("machine: unknown port")
+	}
+}
+
+// Enable peripheral clock
+func enableAltFuncClock(bus unsafe.Pointer) {
+	switch bus {
+	case unsafe.Pointer(stm32.DAC): // DAC interface clock enable
+		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_DACEN)
+	case unsafe.Pointer(stm32.PWR): // Power interface clock enable
+		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_PWREN)
+	case unsafe.Pointer(stm32.CAN1): // CAN 1 clock enable
+		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_CAN1EN)
+	case unsafe.Pointer(stm32.I2C3): // I2C3 clock enable
+		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C3EN)
+	case unsafe.Pointer(stm32.I2C2): // I2C2 clock enable
+		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C2EN)
+	case unsafe.Pointer(stm32.I2C1): // I2C1 clock enable
+		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C1EN)
+	case unsafe.Pointer(stm32.UART5): // UART5 clock enable
+		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_UART5EN)
+	case unsafe.Pointer(stm32.UART4): // UART4 clock enable
+		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_UART4EN)
+	case unsafe.Pointer(stm32.USART3): // USART3 clock enable
+		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART3EN)
+	case unsafe.Pointer(stm32.USART2): // USART2 clock enable
+		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART2EN)
+	case unsafe.Pointer(stm32.SPI3): // SPI3 clock enable
+		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_SPI3EN)
+	case unsafe.Pointer(stm32.SPI2): // SPI2 clock enable
+		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_SPI2EN)
+	case unsafe.Pointer(stm32.WWDG): // Window watchdog clock enable
+		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_WWDGEN)
+	case unsafe.Pointer(stm32.TIM14): // TIM14 clock enable
+		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM14EN)
+	case unsafe.Pointer(stm32.TIM13): // TIM13 clock enable
+		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM13EN)
+	case unsafe.Pointer(stm32.TIM12): // TIM12 clock enable
+		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM12EN)
+	case unsafe.Pointer(stm32.TIM7): // TIM7 clock enable
+		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM7EN)
+	case unsafe.Pointer(stm32.TIM6): // TIM6 clock enable
+		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM6EN)
+	case unsafe.Pointer(stm32.TIM5): // TIM5 clock enable
+		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM5EN)
+	case unsafe.Pointer(stm32.TIM4): // TIM4 clock enable
+		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM4EN)
+	case unsafe.Pointer(stm32.TIM3): // TIM3 clock enable
+		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM3EN)
+	case unsafe.Pointer(stm32.TIM2): // TIM2 clock enable
+		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM2EN)
+	case unsafe.Pointer(stm32.TIM11): // TIM11 clock enable
+		stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM11EN)
+	case unsafe.Pointer(stm32.TIM10): // TIM10 clock enable
+		stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM10EN)
+	case unsafe.Pointer(stm32.TIM9): // TIM9 clock enable
+		stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM9EN)
+	case unsafe.Pointer(stm32.SYSCFG): // System configuration controller clock enable
+		stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SYSCFGEN)
+	case unsafe.Pointer(stm32.SPI1): // SPI1 clock enable
+		stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SPI1EN)
+	case unsafe.Pointer(stm32.ADC3): // ADC3 clock enable
+		stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_ADC3EN)
+	case unsafe.Pointer(stm32.ADC2): // ADC2 clock enable
+		stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_ADC2EN)
+	case unsafe.Pointer(stm32.ADC1): // ADC1 clock enable
+		stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_ADC1EN)
+	case unsafe.Pointer(stm32.USART6): // USART6 clock enable
+		stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART6EN)
+	case unsafe.Pointer(stm32.USART1): // USART1 clock enable
+		stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART1EN)
+	case unsafe.Pointer(stm32.TIM8): // TIM8 clock enable
+		stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM8EN)
+	case unsafe.Pointer(stm32.TIM1): // TIM1 clock enable
+		stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM1EN)
+	}
+}

src/machine/machine_stm32f7x2.go

@@ -0,0 +1,44 @@
+// +build stm32f7x2
+
+package machine
+
+// Peripheral abstraction layer for the stm32f407
+
+import (
+	"device/stm32"
+	"runtime/interrupt"
+)
+
+func CPUFrequency() uint32 {
+	return 216000000
+}
+
+//---------- UART related types and code
+
+// UART representation
+type UART struct {
+	Buffer          *RingBuffer
+	Bus             *stm32.USART_Type
+	Interrupt       interrupt.Interrupt
+	AltFuncSelector stm32.AltFunc
+}
+
+// Configure the UART.
+func (uart UART) configurePins(config UARTConfig) {
+	// enable the alternate functions on the TX and RX pins
+	config.TX.ConfigureAltFunc(PinConfig{Mode: PinModeUARTTX}, uart.AltFuncSelector)
+	config.RX.ConfigureAltFunc(PinConfig{Mode: PinModeUARTRX}, uart.AltFuncSelector)
+}
+
+// UART baudrate calc based on the bus and clockspeed
+// NOTE: keep this in sync with the runtime/runtime_stm32f7x2.go clock init code
+func (uart UART) getBaudRateDivisor(baudRate uint32) uint32 {
+	var clock uint32
+	switch uart.Bus {
+	case stm32.USART1, stm32.USART6:
+		clock = CPUFrequency() / 2 // APB2 Frequency
+	case stm32.USART2, stm32.USART3, stm32.UART4, stm32.UART5:
+		clock = CPUFrequency() / 8 // APB1 Frequency
+	}
+	return clock / baudRate
+}

src/machine/spi.go

@@ -1,4 +1,4 @@
-// +build !baremetal sam stm32 fe310 k210
+// +build !baremetal sam stm32,!stm32f7x2 fe310 k210
 
 package machine
 

src/runtime/runtime_stm32f7x2.go

@@ -0,0 +1,208 @@
+// +build stm32,stm32f7x2
+
+package runtime
+
+import (
+	"device/arm"
+	"device/stm32"
+	"machine"
+	"runtime/interrupt"
+	"runtime/volatile"
+)
+
+func init() {
+	initCLK()
+	initTIM3()
+	machine.UART0.Configure(machine.UARTConfig{})
+	initTIM7()
+}
+
+func putchar(c byte) {
+	machine.UART0.WriteByte(c)
+}
+
+const (
+	HSE_STARTUP_TIMEOUT = 0x0500
+	PLL_M               = 4
+	PLL_N               = 216
+	PLL_P               = 2
+	PLL_Q               = 2
+)
+
+/*
+   clock settings
+   +-------------+--------+
+   | HSE         | 8mhz   |
+   | SYSCLK      | 216mhz |
+   | HCLK        | 216mhz |
+   | APB1(PCLK1) | 27mhz  |
+   | APB2(PCLK2) | 108mhz |
+   +-------------+--------+
+*/
+func initCLK() {
+	// PWR_CLK_ENABLE
+	stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_PWREN)
+	_ = stm32.RCC.APB1ENR.Get()
+
+	// PWR_VOLTAGESCALING_CONFIG
+	stm32.PWR.CR1.ReplaceBits(0x3<<stm32.PWR_CR1_VOS_Pos, stm32.PWR_CR1_VOS_Msk, 0)
+	_ = stm32.PWR.CR1.Get()
+
+	// Initialize the High-Speed External Oscillator
+	initOsc()
+
+	// Set flash wait states (min 7 latency units) based on clock
+	if (stm32.FLASH.ACR.Get() & stm32.FLASH_ACR_LATENCY_Msk) < 7 {
+		stm32.FLASH.ACR.ReplaceBits(7, stm32.FLASH_ACR_LATENCY_Msk, 0)
+	}
+
+	// HCLK (0x1C00 = DIV_16, 0x0 = RCC_SYSCLK_DIV1) - ensure timers remain
+	// within spec as the SYSCLK source changes.
+	stm32.RCC.CFGR.ReplaceBits(0x00001C00, stm32.RCC_CFGR_PPRE1_Msk, 0)
+	stm32.RCC.CFGR.ReplaceBits(0x00001C00<<3, stm32.RCC_CFGR_PPRE2_Msk, 0)
+	stm32.RCC.CFGR.ReplaceBits(0, stm32.RCC_CFGR_HPRE_Msk, 0)
+
+	// Set SYSCLK source and wait
+	// (2 = PLLCLK, 3 = RCC_CFGR_SW mask, 3 << 3 = RCC_CFGR_SWS mask)
+	stm32.RCC.CFGR.ReplaceBits(2, 3, 0)
+	for stm32.RCC.CFGR.Get()&(3<<2) != (2 << 2) {
+	}
+
+	// Set flash wait states (max 7 latency units) based on clock
+	if (stm32.FLASH.ACR.Get() & stm32.FLASH_ACR_LATENCY_Msk) > 7 {
+		stm32.FLASH.ACR.ReplaceBits(7, stm32.FLASH_ACR_LATENCY_Msk, 0)
+	}
+
+	// Set APB1 and APB2 clocks (0x1800 = DIV8, 0x1000 = DIV2)
+	stm32.RCC.CFGR.ReplaceBits(0x1800, stm32.RCC_CFGR_PPRE1_Msk, 0)
+	stm32.RCC.CFGR.ReplaceBits(0x1000<<3, stm32.RCC_CFGR_PPRE2_Msk, 0)
+}
+
+func initOsc() {
+	// Enable HSE, wait until ready
+	stm32.RCC.CR.SetBits(stm32.RCC_CR_HSEON)
+	for !stm32.RCC.CR.HasBits(stm32.RCC_CR_HSERDY) {
+	}
+
+	// Disable the PLL, wait until disabled
+	stm32.RCC.CR.ClearBits(stm32.RCC_CR_PLLON)
+	for stm32.RCC.CR.HasBits(stm32.RCC_CR_PLLRDY) {
+	}
+
+	// Configure the PLL
+	stm32.RCC.PLLCFGR.Set(0x20000000 |
+		(1 << stm32.RCC_PLLCFGR_PLLSRC_Pos) | // 1 = HSE
+		PLL_M |
+		(PLL_N << stm32.RCC_PLLCFGR_PLLN0_Pos) |
+		(((PLL_P >> 1) - 1) << stm32.RCC_PLLCFGR_PLLP0_Pos) |
+		(PLL_Q << stm32.RCC_PLLCFGR_PLLQ0_Pos))
+
+	// Enable the PLL, wait until ready
+	stm32.RCC.CR.SetBits(stm32.RCC_CR_PLLON)
+	for !stm32.RCC.CR.HasBits(stm32.RCC_CR_PLLRDY) {
+	}
+}
+
+var (
+	// tick in milliseconds
+	tickCount timeUnit
+)
+
+var timerWakeup volatile.Register8
+
+func ticksToNanoseconds(ticks timeUnit) int64 {
+	return int64(ticks) * 1000
+}
+
+func nanosecondsToTicks(ns int64) timeUnit {
+	return timeUnit(ns / 1000)
+}
+
+// Enable the TIM3 clock.(sleep count)
+func initTIM3() {
+	stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM3EN)
+
+	intr := interrupt.New(stm32.IRQ_TIM3, handleTIM3)
+	intr.SetPriority(0xc3)
+	intr.Enable()
+}
+
+// Enable the TIM7 clock.(tick count)
+func initTIM7() {
+	stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM7EN)
+
+	// CK_INT = APB1 x2 = 54mhz
+	stm32.TIM7.PSC.Set(54000000/10000 - 1) // 54mhz to 10khz(0.1ms)
+	stm32.TIM7.ARR.Set(10 - 1)             // interrupt per 1ms
+
+	// Enable the hardware interrupt.
+	stm32.TIM7.DIER.SetBits(stm32.TIM_DIER_UIE)
+
+	// Enable the timer.
+	stm32.TIM7.CR1.SetBits(stm32.TIM_CR1_CEN)
+
+	intr := interrupt.New(stm32.IRQ_TIM7, handleTIM7)
+	intr.SetPriority(0xc1)
+	intr.Enable()
+}
+
+const asyncScheduler = false
+
+// sleepTicks should sleep for specific number of microseconds.
+func sleepTicks(d timeUnit) {
+	timerSleep(uint32(d))
+}
+
+// number of ticks (microseconds) since start.
+func ticks() timeUnit {
+	// milliseconds to microseconds
+	return tickCount * 1000
+}
+
+// ticks are in microseconds
+func timerSleep(ticks uint32) {
+	timerWakeup.Set(0)
+
+	// CK_INT = APB1 x2 = 54mhz
+	// prescale counter down from 54mhz to 10khz aka 0.1 ms frequency.
+	stm32.TIM3.PSC.Set(54000000/10000 - 1)
+
+	// set duty aka duration
+	arr := (ticks / 100) - 1 // convert from microseconds to 0.1 ms
+	if arr == 0 {
+		arr = 1 // avoid blocking
+	}
+	stm32.TIM3.ARR.Set(arr)
+
+	// Enable the hardware interrupt.
+	stm32.TIM3.DIER.SetBits(stm32.TIM_DIER_UIE)
+
+	// Enable the timer.
+	stm32.TIM3.CR1.SetBits(stm32.TIM_CR1_CEN)
+
+	// wait till timer wakes up
+	for timerWakeup.Get() == 0 {
+		arm.Asm("wfi")
+	}
+}
+
+func handleTIM3(interrupt.Interrupt) {
+	if stm32.TIM3.SR.HasBits(stm32.TIM_SR_UIF) {
+		// Disable the timer.
+		stm32.TIM3.CR1.ClearBits(stm32.TIM_CR1_CEN)
+
+		// clear the update flag
+		stm32.TIM3.SR.ClearBits(stm32.TIM_SR_UIF)
+
+		// timer was triggered
+		timerWakeup.Set(1)
+	}
+}
+
+func handleTIM7(interrupt.Interrupt) {
+	if stm32.TIM7.SR.HasBits(stm32.TIM_SR_UIF) {
+		// clear the update flag
+		stm32.TIM7.SR.ClearBits(stm32.TIM_SR_UIF)
+		tickCount++
+	}
+}

targets/cortex-m7.json

@@ -0,0 +1,9 @@
+{
+	"inherits": ["cortex-m"],
+	"llvm-target": "armv7em-none-eabi",
+	"cflags": [
+		"--target=armv7em-none-eabi",
+		"-Qunused-arguments"
+	],
+	"gdb": "arm-none-eabi-gdb"
+}

targets/nucleo-f722ze.json

@@ -0,0 +1,11 @@
+{
+  "inherits": ["cortex-m7"],
+  "build-tags": ["nucleof722ze", "stm32f7x2", "stm32f7", "stm32"],
+  "linkerscript": "targets/stm32f7x2zetx.ld",
+  "extra-files": [
+    "src/device/stm32/stm32f7x2.s"
+  ],
+  "flash-method": "openocd",
+  "openocd-interface": "stlink-v2-1",
+  "openocd-target": "stm32f7x"
+}

targets/stm32f7x2zetx.ld

@@ -0,0 +1,10 @@
+
+MEMORY
+{
+    FLASH_TEXT (rw) : ORIGIN = 0x08000000, LENGTH = 512K
+    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+_stack_size = 4K;
+
+INCLUDE "targets/arm.ld"