mirror of https://github.com/tinygo-org/tinygo.git
Ethan Reesor
5 years ago
committed by
Ron Evans
Ron Evans
11 changed files with 449 additions and 84 deletions
@ -0,0 +1,251 @@ |
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// +build nxp,mk66f18
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package machine |
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import ( |
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"device/arm" |
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"device/nxp" |
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"errors" |
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"runtime/volatile" |
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_ "unsafe" // for go:linkname
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) |
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const ( |
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uartC2Enable = nxp.UART_C2_TE | nxp.UART_C2_RE | nxp.UART_C2_RIE | nxp.UART_C2_ILIE |
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uartC2TXActive = uartC2Enable | nxp.UART_C2_TIE |
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uartC2TXCompleting = uartC2Enable | nxp.UART_C2_TCIE |
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uartC2TXInactive = uartC2Enable |
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uartIRQPriority = 64 |
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) |
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var ( |
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ErrNotImplemented = errors.New("device has not been implemented") |
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ErrNotConfigured = errors.New("device has not been configured") |
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) |
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type UARTConfig struct { |
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BaudRate uint32 |
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} |
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type UART struct { |
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*nxp.UART_Type |
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RXPCR *volatile.Register32 |
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TXPCR *volatile.Register32 |
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SCGC *volatile.Register32 |
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SCGCMask uint32 |
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IRQNumber uint32 |
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// state
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RXBuffer RingBuffer |
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TXBuffer RingBuffer |
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Transmitting volatile.Register8 |
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} |
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// 'UART0' in the K66 manual corresponds to 'UART1' on the Teensy's pinout
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var UART1 = UART{UART_Type: nxp.UART0, RXPCR: pins[0].PCR, TXPCR: pins[1].PCR, SCGC: &nxp.SIM.SCGC4, SCGCMask: nxp.SIM_SCGC4_UART0, IRQNumber: nxp.IRQ_UART0_RX_TX} |
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var UART2 = UART{UART_Type: nxp.UART1, RXPCR: pins[9].PCR, TXPCR: pins[10].PCR, SCGC: &nxp.SIM.SCGC4, SCGCMask: nxp.SIM_SCGC4_UART1, IRQNumber: nxp.IRQ_UART1_RX_TX} |
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var UART3 = UART{UART_Type: nxp.UART2, RXPCR: pins[7].PCR, TXPCR: pins[8].PCR, SCGC: &nxp.SIM.SCGC4, SCGCMask: nxp.SIM_SCGC4_UART2, IRQNumber: nxp.IRQ_UART2_RX_TX} |
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var UART4 = UART{UART_Type: nxp.UART3, RXPCR: pins[31].PCR, TXPCR: pins[32].PCR, SCGC: &nxp.SIM.SCGC4, SCGCMask: nxp.SIM_SCGC4_UART3, IRQNumber: nxp.IRQ_UART3_RX_TX} |
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var UART5 = UART{UART_Type: nxp.UART4, RXPCR: pins[34].PCR, TXPCR: pins[33].PCR, SCGC: &nxp.SIM.SCGC1, SCGCMask: nxp.SIM_SCGC1_UART4, IRQNumber: nxp.IRQ_UART4_RX_TX} |
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//go:export UART0_RX_TX_IRQHandler
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func uart0StatusISR() { UART1.handleStatusInterrupt() } |
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//go:export UART1_RX_TX_IRQHandler
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func uart1StatusISR() { UART2.handleStatusInterrupt() } |
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//go:export UART2_RX_TX_IRQHandler
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func uart2StatusISR() { UART3.handleStatusInterrupt() } |
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//go:export UART3_RX_TX_IRQHandler
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func uart3StatusISR() { UART4.handleStatusInterrupt() } |
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//go:export UART4_RX_TX_IRQHandler
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func uart4StatusISR() { UART5.handleStatusInterrupt() } |
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// Configure the UART.
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func (u *UART) Configure(config UARTConfig) { |
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en := u.SCGC.HasBits(u.SCGCMask) |
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// adapted from Teensy core's serial_begin
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if !en { |
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u.Transmitting.Set(0) |
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// turn on the clock
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u.SCGC.Set(u.SCGCMask) |
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// configure pins
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u.RXPCR.Set(nxp.PORT_PCR0_PE | nxp.PORT_PCR0_PS | nxp.PORT_PCR0_PFE | nxp.PORT_PCR0_MUX(3)) |
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u.TXPCR.Set(nxp.PORT_PCR0_DSE | nxp.PORT_PCR0_SRE | nxp.PORT_PCR0_MUX(3)) |
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u.C1.Set(nxp.UART_C1_ILT) |
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} |
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// default to 115200 baud
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if config.BaudRate == 0 { |
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config.BaudRate = 115200 |
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} |
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// copied from teensy core's BAUD2DIV macro
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divisor := ((CPUFrequency() * 2) + ((config.BaudRate) >> 1)) / config.BaudRate |
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if divisor < 32 { |
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divisor = 32 |
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} |
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if en { |
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// don't change baud rate mid transmit
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u.Flush() |
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} |
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// set the divisor
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u.BDH.Set(uint8((divisor >> 13) & 0x1F)) |
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u.BDL.Set(uint8((divisor >> 5) & 0xFF)) |
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u.C4.Set(uint8(divisor & 0x1F)) |
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if !en { |
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u.C1.Set(nxp.UART_C1_ILT) |
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// configure TX and RX watermark
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u.TWFIFO.Set(2) // causes bit TDRE of S1 to set
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u.RWFIFO.Set(4) // causes bit RDRF of S1 to set
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u.PFIFO.Set(nxp.UART_PFIFO_TXFE | nxp.UART_PFIFO_RXFE) |
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u.C2.Set(uartC2TXInactive) |
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arm.SetPriority(u.IRQNumber, uartIRQPriority) |
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arm.EnableIRQ(u.IRQNumber) |
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} |
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} |
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func (u *UART) Disable() { |
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// adapted from Teensy core's serial_end
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// check if the device has been enabled already
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if !u.SCGC.HasBits(u.SCGCMask) { |
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return |
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} |
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u.Flush() |
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arm.DisableIRQ(u.IRQNumber) |
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u.C2.Set(0) |
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// reconfigure pin
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u.RXPCR.Set(nxp.PORT_PCR0_PE | nxp.PORT_PCR0_PS | nxp.PORT_PCR0_MUX(1)) |
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u.TXPCR.Set(nxp.PORT_PCR0_PE | nxp.PORT_PCR0_PS | nxp.PORT_PCR0_MUX(1)) |
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// clear flags
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u.S1.Get() |
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u.D.Get() |
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u.RXBuffer.Clear() |
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} |
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func (u *UART) Flush() { |
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for u.Transmitting.Get() != 0 { |
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// gosched()
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} |
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} |
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// adapted from Teensy core's uart0_status_isr
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func (u *UART) handleStatusInterrupt() { |
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if u.S1.HasBits(nxp.UART_S1_RDRF | nxp.UART_S1_IDLE) { |
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intrs := arm.DisableInterrupts() |
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avail := u.RCFIFO.Get() |
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if avail == 0 { |
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// The only way to clear the IDLE interrupt flag is
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// to read the data register. But reading with no
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// data causes a FIFO underrun, which causes the
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// FIFO to return corrupted data. If anyone from
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// Freescale reads this, what a poor design! There
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// write should be a write-1-to-clear for IDLE.
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u.D.Get() |
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// flushing the fifo recovers from the underrun,
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// but there's a possible race condition where a
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// new character could be received between reading
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// RCFIFO == 0 and flushing the FIFO. To minimize
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// the chance, interrupts are disabled so a higher
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// priority interrupt (hopefully) doesn't delay.
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// TODO: change this to disabling the IDLE interrupt
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// which won't be simple, since we already manage
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// which transmit interrupts are enabled.
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u.CFIFO.Set(nxp.UART_CFIFO_RXFLUSH) |
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arm.EnableInterrupts(intrs) |
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} else { |
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arm.EnableInterrupts(intrs) |
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for { |
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u.RXBuffer.Put(u.D.Get()) |
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avail-- |
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if avail <= 0 { |
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break |
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} |
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} |
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} |
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} |
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c := u.C2.Get() |
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if c&nxp.UART_C2_TIE != 0 && u.S1.HasBits(nxp.UART_S1_TDRE) { |
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for { |
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n, ok := u.TXBuffer.Get() |
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if !ok { |
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break |
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} |
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u.S1.Get() |
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u.D.Set(n) |
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if u.TCFIFO.Get() >= 8 { |
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break |
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} |
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} |
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if u.S1.HasBits(nxp.UART_S1_TDRE) { |
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u.Transmitting.Set(0) |
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u.C2.Set(uartC2TXCompleting) |
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} |
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} |
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if c&nxp.UART_C2_TCIE != 0 && u.S1.HasBits(nxp.UART_S1_TC) { |
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u.C2.Set(uartC2TXInactive) |
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} |
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} |
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//go:linkname gosched runtime.Gosched
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func gosched() |
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// WriteByte writes a byte of data to the UART.
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func (u *UART) WriteByte(c byte) error { |
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if !u.SCGC.HasBits(u.SCGCMask) { |
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return ErrNotConfigured |
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} |
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for !u.S1.HasBits(nxp.UART_S1_TDRE) { |
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gosched() |
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} |
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u.D.Set(c) |
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// // wait for room on the buffer
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// for !u.TXBuffer.Put(c) {
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// gosched()
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// }
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// var wrote bool
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// for u.S1.HasBits(nxp.UART_S1_TDRE) {
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// n, ok := u.TXBuffer.Get()
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// if ok {
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// u.D.Set(n)
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// wrote = true
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// } else {
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// break
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// }
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// }
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// if wrote {
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// u.Transmitting.Set(1)
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// u.C2.Set(uartC2TXActive)
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// }
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return nil |
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} |
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@ -0,0 +1,19 @@ |
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.section .flash_config |
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.global __flash_config |
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.byte 0xFF |
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.byte 0xFF |
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.byte 0xFF |
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.byte 0xFF |
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.byte 0xFF |
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.byte 0xFF |
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.byte 0xFF |
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.byte 0xFF |
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.byte 0xFF |
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.byte 0xFF |
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.byte 0xFF |
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.byte 0xFF |
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.byte 0xDE |
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.byte 0xF9 |
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.byte 0xFF |
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.byte 0xFF |
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