From af02c09b56b3a5c60401a2416311c3f0b690aafb Mon Sep 17 00:00:00 2001 From: Kenneth Bell Date: Sun, 13 Dec 2020 23:47:27 -0800 Subject: [PATCH] nucleol552ze: implementation with CLOCK, LED, and UART --- Makefile | 2 + src/machine/board_nucleol552ze.go | 45 +++++ src/machine/i2c.go | 2 +- src/machine/machine_stm32_i2c.go | 2 +- src/machine/machine_stm32_l5_uart.go | 62 +++++++ src/machine/machine_stm32_spi.go | 2 +- src/machine/machine_stm32_uart.go | 2 +- src/machine/machine_stm32l5.go | 253 +++++++++++++++++++++++++++ src/machine/machine_stm32l5x2.go | 42 +++++ src/machine/spi.go | 2 +- src/runtime/runtime_stm32l5x2.go | 243 +++++++++++++++++++++++++ targets/cortex-m33.json | 9 + targets/nucleo-l552ze.json | 11 ++ targets/stm32l5x2xe.ld | 10 ++ 14 files changed, 682 insertions(+), 5 deletions(-) create mode 100644 src/machine/board_nucleol552ze.go create mode 100644 src/machine/machine_stm32_l5_uart.go create mode 100644 src/machine/machine_stm32l5.go create mode 100644 src/machine/machine_stm32l5x2.go create mode 100644 src/runtime/runtime_stm32l5x2.go create mode 100644 targets/cortex-m33.json create mode 100644 targets/nucleo-l552ze.json create mode 100644 targets/stm32l5x2xe.ld diff --git a/Makefile b/Makefile index 0413219f..c5672ab5 100644 --- a/Makefile +++ b/Makefile @@ -341,6 +341,8 @@ smoketest: @$(MD5SUM) test.hex $(TINYGO) build -size short -o test.hex -target=nucleo-f722ze examples/blinky1 @$(MD5SUM) test.hex + $(TINYGO) build -size short -o test.hex -target=nucleo-l552ze examples/blinky1 + @$(MD5SUM) test.hex $(TINYGO) build -size short -o test.hex -target=p1am-100 examples/blinky1 @$(MD5SUM) test.hex # test pwm diff --git a/src/machine/board_nucleol552ze.go b/src/machine/board_nucleol552ze.go new file mode 100644 index 00000000..fe06182b --- /dev/null +++ b/src/machine/board_nucleol552ze.go @@ -0,0 +1,45 @@ +// +build nucleol552ze + +package machine + +import ( + "device/stm32" + "runtime/interrupt" +) + +const ( + LED = LED_BUILTIN + LED_BUILTIN = LED_GREEN + LED_GREEN = PC7 + LED_BLUE = PB7 + LED_RED = PA9 +) + +const ( + BUTTON = BUTTON_USER + BUTTON_USER = PC13 +) + +// UART pins +const ( + // PG7 and PG8 are connected to the ST-Link Virtual Com Port (VCP) + UART_TX_PIN = PG7 + UART_RX_PIN = PG8 + UART_ALT_FN = 8 // GPIO_AF8_LPUART1 +) + +var ( + // LPUART1 is the hardware serial port connected to the onboard ST-LINK + // debugger to be exposed as virtual COM port over USB on Nucleo boards. + // Both UART0 and UART1 refer to LPUART1. + UART0 = UART{ + Buffer: NewRingBuffer(), + Bus: stm32.LPUART1, + AltFuncSelector: UART_ALT_FN, + } + UART1 = &UART0 +) + +func init() { + UART0.Interrupt = interrupt.New(stm32.IRQ_LPUART1, UART0.handleInterrupt) +} diff --git a/src/machine/i2c.go b/src/machine/i2c.go index aa804f6b..f4112317 100644 --- a/src/machine/i2c.go +++ b/src/machine/i2c.go @@ -1,4 +1,4 @@ -// +build avr nrf sam stm32,!stm32f407,!stm32f7x2,!stm32l0 fe310 k210 +// +build avr nrf sam stm32,!stm32f407,!stm32f7x2,!stm32l5x2,!stm32l0 fe310 k210 package machine diff --git a/src/machine/machine_stm32_i2c.go b/src/machine/machine_stm32_i2c.go index 9453a24d..e83e486d 100644 --- a/src/machine/machine_stm32_i2c.go +++ b/src/machine/machine_stm32_i2c.go @@ -1,4 +1,4 @@ -// +build stm32,!stm32f103,!stm32f407,!stm32f7x2,!stm32l0 +// +build stm32,!stm32f103,!stm32f407,!stm32f7x2,!stm32l5x2,!stm32l0 package machine diff --git a/src/machine/machine_stm32_l5_uart.go b/src/machine/machine_stm32_l5_uart.go new file mode 100644 index 00000000..ffae11c5 --- /dev/null +++ b/src/machine/machine_stm32_l5_uart.go @@ -0,0 +1,62 @@ +// +build stm32,stm32l5x2 + +package machine + +// Peripheral abstraction layer for UARTs on the stm32 family. + +import ( + "device/stm32" + "runtime/interrupt" + "unsafe" +) + +// Configure the UART. +func (uart UART) Configure(config UARTConfig) { + // Default baud rate to 115200. + if config.BaudRate == 0 { + config.BaudRate = 115200 + } + + // Set the GPIO pins to defaults if they're not set + if config.TX == 0 && config.RX == 0 { + config.TX = UART_TX_PIN + config.RX = UART_RX_PIN + } + + // Enable USART clock + enableAltFuncClock(unsafe.Pointer(uart.Bus)) + + uart.configurePins(config) + + // Set baud rate + uart.SetBaudRate(config.BaudRate) + + // Enable USART port, tx, rx and rx interrupts + uart.Bus.CR1.Set(stm32.USART_CR1_TE | stm32.USART_CR1_RE | stm32.USART_CR1_RXNEIE | stm32.USART_CR1_UE) + + // Enable RX IRQ + uart.Interrupt.SetPriority(0xc0) + uart.Interrupt.Enable() +} + +// handleInterrupt should be called from the appropriate interrupt handler for +// this UART instance. +func (uart *UART) handleInterrupt(interrupt.Interrupt) { + uart.Receive(byte((uart.Bus.RDR.Get() & 0xFF))) +} + +// SetBaudRate sets the communication speed for the UART. Defer to chip-specific +// routines for calculation +func (uart UART) SetBaudRate(br uint32) { + divider := uart.getBaudRateDivisor(br) + uart.Bus.BRR.Set(divider) +} + +// WriteByte writes a byte of data to the UART. +func (uart UART) WriteByte(c byte) error { + uart.Bus.TDR.Set(uint32(c)) + + for !uart.Bus.ISR.HasBits(stm32.USART_ISR_TXE) { + } + return nil +} diff --git a/src/machine/machine_stm32_spi.go b/src/machine/machine_stm32_spi.go index 15573ed7..29b099c9 100644 --- a/src/machine/machine_stm32_spi.go +++ b/src/machine/machine_stm32_spi.go @@ -1,4 +1,4 @@ -// +build stm32,!stm32f7x2 +// +build stm32,!stm32f7x2,!stm32l5x2 package machine diff --git a/src/machine/machine_stm32_uart.go b/src/machine/machine_stm32_uart.go index e4fa4708..84bc1093 100644 --- a/src/machine/machine_stm32_uart.go +++ b/src/machine/machine_stm32_uart.go @@ -1,4 +1,4 @@ -// +build stm32,!stm32f7,!stm32l0 +// +build stm32,!stm32f7,!stm32l5x2,!stm32l0 package machine diff --git a/src/machine/machine_stm32l5.go b/src/machine/machine_stm32l5.go new file mode 100644 index 00000000..185bdfb7 --- /dev/null +++ b/src/machine/machine_stm32l5.go @@ -0,0 +1,253 @@ +// +build stm32l5 + +package machine + +// Peripheral abstraction layer for the stm32l5 + +import ( + "device/stm32" + "unsafe" +) + +const ( + PA0 = portA + 0 + PA1 = portA + 1 + PA2 = portA + 2 + PA3 = portA + 3 + PA4 = portA + 4 + PA5 = portA + 5 + PA6 = portA + 6 + PA7 = portA + 7 + PA8 = portA + 8 + PA9 = portA + 9 + PA10 = portA + 10 + PA11 = portA + 11 + PA12 = portA + 12 + PA13 = portA + 13 + PA14 = portA + 14 + PA15 = portA + 15 + + PB0 = portB + 0 + PB1 = portB + 1 + PB2 = portB + 2 + PB3 = portB + 3 + PB4 = portB + 4 + PB5 = portB + 5 + PB6 = portB + 6 + PB7 = portB + 7 + PB8 = portB + 8 + PB9 = portB + 9 + PB10 = portB + 10 + PB11 = portB + 11 + PB12 = portB + 12 + PB13 = portB + 13 + PB14 = portB + 14 + PB15 = portB + 15 + + PC0 = portC + 0 + PC1 = portC + 1 + PC2 = portC + 2 + PC3 = portC + 3 + PC4 = portC + 4 + PC5 = portC + 5 + PC6 = portC + 6 + PC7 = portC + 7 + PC8 = portC + 8 + PC9 = portC + 9 + PC10 = portC + 10 + PC11 = portC + 11 + PC12 = portC + 12 + PC13 = portC + 13 + PC14 = portC + 14 + PC15 = portC + 15 + + PD0 = portD + 0 + PD1 = portD + 1 + PD2 = portD + 2 + PD3 = portD + 3 + PD4 = portD + 4 + PD5 = portD + 5 + PD6 = portD + 6 + PD7 = portD + 7 + PD8 = portD + 8 + PD9 = portD + 9 + PD10 = portD + 10 + PD11 = portD + 11 + PD12 = portD + 12 + PD13 = portD + 13 + PD14 = portD + 14 + PD15 = portD + 15 + + PE0 = portE + 0 + PE1 = portE + 1 + PE2 = portE + 2 + PE3 = portE + 3 + PE4 = portE + 4 + PE5 = portE + 5 + PE6 = portE + 6 + PE7 = portE + 7 + PE8 = portE + 8 + PE9 = portE + 9 + PE10 = portE + 10 + PE11 = portE + 11 + PE12 = portE + 12 + PE13 = portE + 13 + PE14 = portE + 14 + PE15 = portE + 15 + + PF0 = portF + 0 + PF1 = portF + 1 + PF2 = portF + 2 + PF3 = portF + 3 + PF4 = portF + 4 + PF5 = portF + 5 + PF6 = portF + 6 + PF7 = portF + 7 + PF8 = portF + 8 + PF9 = portF + 9 + PF10 = portF + 10 + PF11 = portF + 11 + PF12 = portF + 12 + PF13 = portF + 13 + PF14 = portF + 14 + PF15 = portF + 15 + + PG0 = portG + 0 + PG1 = portG + 1 + PG2 = portG + 2 + PG3 = portG + 3 + PG4 = portG + 4 + PG5 = portG + 5 + PG6 = portG + 6 + PG7 = portG + 7 + PG8 = portG + 8 + PG9 = portG + 9 + PG10 = portG + 10 + PG11 = portG + 11 + PG12 = portG + 12 + PG13 = portG + 13 + PG14 = portG + 14 + PG15 = portG + 15 + + PH0 = portH + 0 + PH1 = portH + 1 +) + +func (p Pin) getPort() *stm32.GPIO_Type { + switch p / 16 { + case 0: + return stm32.GPIOA + case 1: + return stm32.GPIOB + case 2: + return stm32.GPIOC + case 3: + return stm32.GPIOD + case 4: + return stm32.GPIOE + case 5: + return stm32.GPIOF + case 6: + return stm32.GPIOG + case 7: + return stm32.GPIOH + default: + panic("machine: unknown port") + } +} + +// enableClock enables the clock for this desired GPIO port. +func (p Pin) enableClock() { + switch p / 16 { + case 0: + stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOAEN) + case 1: + stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOBEN) + case 2: + stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOCEN) + case 3: + stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIODEN) + case 4: + stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOEEN) + case 5: + stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOFEN) + case 6: + stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOGEN) + case 7: + stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOHEN) + default: + panic("machine: unknown port") + } +} + +// Enable peripheral clock +func enableAltFuncClock(bus unsafe.Pointer) { + switch bus { + case unsafe.Pointer(stm32.DAC): // DAC interface clock enable + stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_DAC1EN) + case unsafe.Pointer(stm32.PWR): // Power interface clock enable + stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_PWREN) + case unsafe.Pointer(stm32.I2C3): // I2C3 clock enable + stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C3EN) + case unsafe.Pointer(stm32.I2C2): // I2C2 clock enable + stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C2EN) + case unsafe.Pointer(stm32.I2C1): // I2C1 clock enable + stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C1EN) + case unsafe.Pointer(stm32.UART5): // UART5 clock enable + stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_UART5EN) + case unsafe.Pointer(stm32.UART4): // UART4 clock enable + stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_UART4EN) + case unsafe.Pointer(stm32.USART3): // USART3 clock enable + stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_USART3EN) + case unsafe.Pointer(stm32.USART2): // USART2 clock enable + stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_USART2EN) + case unsafe.Pointer(stm32.SPI3): // SPI3 clock enable + stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_SP3EN) + case unsafe.Pointer(stm32.SPI2): // SPI2 clock enable + stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_SPI2EN) + case unsafe.Pointer(stm32.WWDG): // Window watchdog clock enable + stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_WWDGEN) + case unsafe.Pointer(stm32.TIM7): // TIM7 clock enable + stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM7EN) + case unsafe.Pointer(stm32.TIM6): // TIM6 clock enable + stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM6EN) + case unsafe.Pointer(stm32.TIM5): // TIM5 clock enable + stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM5EN) + case unsafe.Pointer(stm32.TIM4): // TIM4 clock enable + stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM4EN) + case unsafe.Pointer(stm32.TIM3): // TIM3 clock enable + stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM3EN) + case unsafe.Pointer(stm32.TIM2): // TIM2 clock enable + stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM2EN) + + case unsafe.Pointer(stm32.UCPD1): // UCPD1 clock enable + stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_UCPD1EN) + case unsafe.Pointer(stm32.FDCAN1): // FDCAN1 clock enable + stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_FDCAN1EN) + case unsafe.Pointer(stm32.LPTIM3): // LPTIM3 clock enable + stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_LPTIM3EN) + case unsafe.Pointer(stm32.LPTIM2): // LPTIM2 clock enable + stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_LPTIM2EN) + case unsafe.Pointer(stm32.I2C4): // I2C4 clock enable + stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_I2C4EN) + case unsafe.Pointer(stm32.LPUART1): // LPUART1 clock enable + stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_LPUART1EN) + + case unsafe.Pointer(stm32.TIM17): // TIM17 clock enable + stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM17EN) + case unsafe.Pointer(stm32.TIM16): // TIM16 clock enable + stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM16EN) + case unsafe.Pointer(stm32.TIM15): // TIM15 clock enable + stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM15EN) + case unsafe.Pointer(stm32.SYSCFG): // System configuration controller clock enable + stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SYSCFGEN) + case unsafe.Pointer(stm32.SPI1): // SPI1 clock enable + stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SPI1EN) + case unsafe.Pointer(stm32.USART1): // USART1 clock enable + stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART1EN) + case unsafe.Pointer(stm32.TIM8): // TIM8 clock enable + stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM8EN) + case unsafe.Pointer(stm32.TIM1): // TIM1 clock enable + stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM1EN) + } +} diff --git a/src/machine/machine_stm32l5x2.go b/src/machine/machine_stm32l5x2.go new file mode 100644 index 00000000..16344620 --- /dev/null +++ b/src/machine/machine_stm32l5x2.go @@ -0,0 +1,42 @@ +// +build stm32l5x2 + +package machine + +// Peripheral abstraction layer for the stm32f407 + +import ( + "device/stm32" + "runtime/interrupt" +) + +func CPUFrequency() uint32 { + return 110000000 +} + +//---------- UART related types and code + +// UART representation +type UART struct { + Buffer *RingBuffer + Bus *stm32.USART_Type + Interrupt interrupt.Interrupt + AltFuncSelector stm32.AltFunc +} + +// Configure the UART. +func (uart UART) configurePins(config UARTConfig) { + if config.RX.getPort() == stm32.GPIOG || config.TX.getPort() == stm32.GPIOG { + // Enable VDDIO2 power supply, which is an independant power supply for the PGx pins + stm32.PWR.CR2.SetBits(stm32.PWR_CR2_IOSV) + } + + // enable the alternate functions on the TX and RX pins + config.TX.ConfigureAltFunc(PinConfig{Mode: PinModeUARTTX}, uart.AltFuncSelector) + config.RX.ConfigureAltFunc(PinConfig{Mode: PinModeUARTRX}, uart.AltFuncSelector) +} + +// UART baudrate calc based on the bus and clockspeed +// NOTE: keep this in sync with the runtime/runtime_stm32l5x2.go clock init code +func (uart UART) getBaudRateDivisor(baudRate uint32) uint32 { + return 256 * (CPUFrequency() / baudRate) +} diff --git a/src/machine/spi.go b/src/machine/spi.go index e9e3c42d..238a5d0b 100644 --- a/src/machine/spi.go +++ b/src/machine/spi.go @@ -1,4 +1,4 @@ -// +build !baremetal sam stm32,!stm32f7x2 fe310 k210 atmega +// +build !baremetal sam stm32,!stm32f7x2,!stm32l5x2 fe310 k210 atmega package machine diff --git a/src/runtime/runtime_stm32l5x2.go b/src/runtime/runtime_stm32l5x2.go new file mode 100644 index 00000000..2249ffa2 --- /dev/null +++ b/src/runtime/runtime_stm32l5x2.go @@ -0,0 +1,243 @@ +// +build stm32,stm32l5x2 + +package runtime + +import ( + "device/arm" + "device/stm32" + "machine" + "runtime/interrupt" + "runtime/volatile" +) + +func init() { + initCLK() + initTIM15() + machine.UART0.Configure(machine.UARTConfig{}) + initTIM16() +} + +func putchar(c byte) { + machine.UART0.WriteByte(c) +} + +const ( + HSE_STARTUP_TIMEOUT = 0x0500 + PLL_M = 1 + PLL_N = 55 + PLL_P = 7 // RCC_PLLP_DIV7 + PLL_Q = 2 // RCC_PLLQ_DIV2 + PLL_R = 2 // RCC_PLLR_DIV2 +) + +/* + clock settings + +-------------+-----------+ + | LSE | 32.768khz | + | SYSCLK | 110mhz | + | HCLK | 110mhz | + | APB1(PCLK1) | 110mhz | + | APB2(PCLK2) | 110mhz | + +-------------+-----------+ +*/ +func initCLK() { + + // PWR_CLK_ENABLE + stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_PWREN) + _ = stm32.RCC.APB1ENR1.Get() + + // PWR_VOLTAGESCALING_CONFIG + stm32.PWR.CR1.ReplaceBits(0, stm32.PWR_CR1_VOS_Msk, 0) + _ = stm32.PWR.CR1.Get() + + // Initialize the High-Speed External Oscillator + initOsc() + + // Set flash wait states (min 5 latency units) based on clock + if (stm32.FLASH.ACR.Get() & 0xF) < 5 { + stm32.FLASH.ACR.ReplaceBits(5, 0xF, 0) + } + + // Ensure HCLK does not exceed max during transition + stm32.RCC.CFGR.ReplaceBits(8< 5 { + stm32.FLASH.ACR.ReplaceBits(5, 0xF, 0) + } + + // Set APB1 and APB2 clocks (0 = DIV1) + stm32.RCC.CFGR.ReplaceBits(0, stm32.RCC_CFGR_PPRE1_Msk, 0) + stm32.RCC.CFGR.ReplaceBits(0, stm32.RCC_CFGR_PPRE2_Msk, 0) +} + +func initOsc() { + // Enable HSI, wait until ready + stm32.RCC.CR.SetBits(stm32.RCC_CR_HSION) + for !stm32.RCC.CR.HasBits(stm32.RCC_CR_HSIRDY) { + } + + // Disable Backup domain protection + if !stm32.PWR.CR1.HasBits(stm32.PWR_CR1_DBP) { + stm32.PWR.CR1.SetBits(stm32.PWR_CR1_DBP) + for !stm32.PWR.CR1.HasBits(stm32.PWR_CR1_DBP) { + } + } + + // Set LSE Drive to LOW + stm32.RCC.BDCR.ReplaceBits(0, stm32.RCC_BDCR_LSEDRV_Msk, 0) + + // Enable LSE, wait until ready + stm32.RCC.BDCR.SetBits(stm32.RCC_BDCR_LSEON) + for !stm32.RCC.BDCR.HasBits(stm32.RCC_BDCR_LSEON) { + } + + // Ensure LSESYS disabled + stm32.RCC.BDCR.ClearBits(stm32.RCC_BDCR_LSESYSEN) + for stm32.RCC.BDCR.HasBits(stm32.RCC_BDCR_LSESYSEN) { + } + + // Enable HSI48, wait until ready + stm32.RCC.CRRCR.SetBits(stm32.RCC_CRRCR_HSI48ON) + for !stm32.RCC.CRRCR.HasBits(stm32.RCC_CRRCR_HSI48ON) { + } + + // Disable the PLL, wait until disabled + stm32.RCC.CR.ClearBits(stm32.RCC_CR_PLLON) + for stm32.RCC.CR.HasBits(stm32.RCC_CR_PLLRDY) { + } + + // Configure the PLL + stm32.RCC.PLLCFGR.ReplaceBits( + (1)| // 1 = RCC_PLLSOURCE_MSI + (PLL_M-1)<>1)-1)<>1)-1)<