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288 lines
9.5 KiB
288 lines
9.5 KiB
/* Linker script for the ESP32-C3
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*
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* The ESP32-C3 has a rather funky memory layout, more like its Xtensa
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* predecessors than like other RISC-V chips:
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* - It has 384kB of regular RAM. This RAM can be used both as data RAM and
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* instruction RAM, but needs to be accessed via a different address space
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* (DRAM/IRAM).
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* - It has another 16kB of RAM, that could be used as regular RAM but is
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* normally used by the flash cache.
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* - It has 8MB of address space for the DROM and IROM, but for some reason
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* this address space is shared. So it isn't possible to map all DROM at
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* 0x3C000000 and all DRAM at 0x42000000: they would overlap.
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* - The MMU works in pages of 64kB, which means the bottom 16 bits of the
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* address in flash and the address in DROM/IROM need to match.
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* - Memory in DRAM and IRAM is loaded at reset by the ROM bootloader.
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* Luckily, this doesn't have significant alignment requirements.
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*
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* This linker script has been written to carefully work around (or with) these
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* limitations:
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* - It adds dummy sections so that the bottom 16 bits of the virtual address
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* and the physical address (in the generated firmware image) match.
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* - It also offsets sections that share an address space using those same
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* dummy sections.
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* - It sorts the sections by load address, to avoid surprises as esptool.py
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* also does it.
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* This way, it's possible to create a very small firmware image that still
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* conforms to the expectations of esptool.py and the ROM bootloader.
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*/
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MEMORY
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{
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/* Note: DRAM and IRAM below are actually in the same 384K address space. */
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DRAM (rw) : ORIGIN = 0x3FC80000, LENGTH = 384K /* Internal SRAM 1 (data bus) */
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IRAM (x) : ORIGIN = 0x40380000, LENGTH = 384K /* Internal SRAM 1 (instruction bus) */
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/* Note: DROM and IROM below are actually in the same 8M address space. */
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DROM (r) : ORIGIN = 0x3C000000, LENGTH = 8M /* Data bus (read-only) */
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IROM (rx) : ORIGIN = 0x42000000, LENGTH = 8M /* Instruction bus */
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}
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/* The entry point. It is set in the image flashed to the chip, so must be
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* defined.
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*/
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ENTRY(call_start_cpu0)
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SECTIONS
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{
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/* Dummy section to make sure the .rodata section starts exactly behind the
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* image header.
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*/
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.rodata_dummy (NOLOAD): ALIGN(4)
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{
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. += 0x18; /* image header at start of flash: esp_image_header_t */
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. += 0x8; /* DROM segment header (8 bytes) */
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} > DROM
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/* Constant global variables, stored in DROM.
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*/
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.rodata : ALIGN(4)
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{
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*(.rodata .rodata.*)
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. = ALIGN (4);
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} >DROM
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/* Put the stack at the bottom of DRAM, so that the application will
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* crash on stack overflow instead of silently corrupting memory.
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* See: http://blog.japaric.io/stack-overflow-protection/
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* TODO: this might not actually work because memory protection hasn't been set up.
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*/
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.stack (NOLOAD) :
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{
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. = ALIGN(16);
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. += _stack_size;
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_stack_top = .;
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} >DRAM
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/* Global variables that are mutable and zero-initialized.
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* These must be zeroed at startup (unlike data, which is loaded by the
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* bootloader).
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*/
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.bss (NOLOAD) : ALIGN(4)
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{
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. = ALIGN (4);
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_sbss = ABSOLUTE(.);
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*(.sbss)
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*(.bss .bss.*)
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. = ALIGN (4);
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_ebss = ABSOLUTE(.);
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} >DRAM
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/* Mutable global variables. This data (in the DRAM segment) is initialized
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* by the ROM bootloader.
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*/
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.data : ALIGN(4)
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{
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. = ALIGN (4);
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_sdata = ABSOLUTE(.);
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*(.sdata)
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*(.data .data.*)
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. = ALIGN (4);
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_edata = ABSOLUTE(.);
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} >DRAM
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/* Dummy section to make sure the .init section (in the IRAM segment) is just
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* behind the DRAM segment. For IRAM and DRAM, we luckily don't have to
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* worry about 64kB pages or image headers as they're loaded in RAM by the
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* bootloader (not mapped from flash).
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*/
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.iram_dummy (NOLOAD): ALIGN(4)
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{
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. += SIZEOF(.stack);
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. += SIZEOF(.bss);
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. += SIZEOF(.data);
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} > IRAM
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/* Initialization code is loaded into IRAM. This memory area is also used by
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* the heap, so no RAM is wasted.
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*/
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.init : ALIGN(4)
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{
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*(.init)
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} >IRAM
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/* Dummy section to put the IROM segment exactly behind the IRAM segment.
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* This has to follow the app image format exactly.
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*/
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.text_dummy (NOLOAD): ALIGN(4)
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{
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/* Note: DRAM and DROM are not always present so the header should only
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* be inserted if it actually exists.
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*/
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. += 0x18; /* esp_image_header_t */
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. += SIZEOF(.rodata) + ((SIZEOF(.rodata) != 0) ? 0x8 : 0); /* DROM segment (optional) */
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. += SIZEOF(.data) + ((SIZEOF(.data) != 0) ? 0x8 : 0); /* DRAM segment (optional) */
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. += SIZEOF(.init) + 0x8; /* IRAM segment */
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. += 0x8; /* IROM segment header */
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} > IROM
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/* IROM segment. This contains all the actual code and is placed right after
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* the DROM segment.
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*/
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.text : ALIGN(4)
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{
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. = ALIGN (256);
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*(.text.exception_vectors)
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. = ALIGN (4);
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*(.text .text.*)
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} >IROM
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/DISCARD/ :
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{
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*(.eh_frame) /* causes 'no memory region specified' error in lld */
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}
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/* Check that the boot ROM stack (for the APP CPU) does not overlap with the
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* data that is loaded by the boot ROM. This is unlikely to happen in
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* practice.
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* The magic value comes from here:
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* https://github.com/espressif/esp-idf/blob/61299f879e/components/bootloader/subproject/main/ld/esp32c3/bootloader.ld#L191
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*/
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ASSERT((_edata + SIZEOF(.init)) < 0x3FCDE710, "the .init section overlaps with the stack used by the boot ROM, possibly causing corruption at startup")
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}
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/* For the garbage collector.
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* Note that _heap_start starts after _edata (without caring for the .init
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* section), because the .init section isn't necessary anymore after startup and
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* can thus be overwritten by the heap.
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*/
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_globals_start = _sbss;
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_globals_end = _edata;
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_heap_start = _edata;
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_heap_end = ORIGIN(DRAM) + LENGTH(DRAM);
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_stack_size = 4K;
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/* ROM functions used for setting up the flash mapping.
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*/
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Cache_Invalidate_ICache_All = 0x400004d8;
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Cache_Suspend_ICache = 0x40000524;
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Cache_Resume_ICache = 0x40000528;
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Cache_MMU_Init = 0x4000055c;
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Cache_Dbus_MMU_Set = 0x40000564;
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/* From ESP-IDF:
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* components/esp_rom/esp32c3/ld/esp32c3.rom.libgcc.ld
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* These are called from LLVM during codegen. The original license is Apache
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* 2.0.
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*/
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__absvdi2 = 0x40000764;
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__absvsi2 = 0x40000768;
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__adddf3 = 0x4000076c;
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__addsf3 = 0x40000770;
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__addvdi3 = 0x40000774;
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__addvsi3 = 0x40000778;
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__ashldi3 = 0x4000077c;
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__ashrdi3 = 0x40000780;
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__bswapdi2 = 0x40000784;
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__bswapsi2 = 0x40000788;
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__clear_cache = 0x4000078c;
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__clrsbdi2 = 0x40000790;
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__clrsbsi2 = 0x40000794;
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__clzdi2 = 0x40000798;
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__clzsi2 = 0x4000079c;
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__cmpdi2 = 0x400007a0;
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__ctzdi2 = 0x400007a4;
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__ctzsi2 = 0x400007a8;
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__divdc3 = 0x400007ac;
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__divdf3 = 0x400007b0;
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__divdi3 = 0x400007b4;
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__divsc3 = 0x400007b8;
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__divsf3 = 0x400007bc;
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__divsi3 = 0x400007c0;
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__eqdf2 = 0x400007c4;
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__eqsf2 = 0x400007c8;
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__extendsfdf2 = 0x400007cc;
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__ffsdi2 = 0x400007d0;
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__ffssi2 = 0x400007d4;
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__fixdfdi = 0x400007d8;
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__fixdfsi = 0x400007dc;
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__fixsfdi = 0x400007e0;
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__fixsfsi = 0x400007e4;
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__fixunsdfsi = 0x400007e8;
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__fixunssfdi = 0x400007ec;
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__fixunssfsi = 0x400007f0;
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__floatdidf = 0x400007f4;
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__floatdisf = 0x400007f8;
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__floatsidf = 0x400007fc;
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__floatsisf = 0x40000800;
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__floatundidf = 0x40000804;
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__floatundisf = 0x40000808;
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__floatunsidf = 0x4000080c;
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__floatunsisf = 0x40000810;
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__gcc_bcmp = 0x40000814;
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__gedf2 = 0x40000818;
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__gesf2 = 0x4000081c;
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__gtdf2 = 0x40000820;
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__gtsf2 = 0x40000824;
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__ledf2 = 0x40000828;
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__lesf2 = 0x4000082c;
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__lshrdi3 = 0x40000830;
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__ltdf2 = 0x40000834;
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__ltsf2 = 0x40000838;
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__moddi3 = 0x4000083c;
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__modsi3 = 0x40000840;
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__muldc3 = 0x40000844;
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__muldf3 = 0x40000848;
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__muldi3 = 0x4000084c;
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__mulsc3 = 0x40000850;
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__mulsf3 = 0x40000854;
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__mulsi3 = 0x40000858;
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__mulvdi3 = 0x4000085c;
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__mulvsi3 = 0x40000860;
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__nedf2 = 0x40000864;
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__negdf2 = 0x40000868;
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__negdi2 = 0x4000086c;
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__negsf2 = 0x40000870;
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__negvdi2 = 0x40000874;
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__negvsi2 = 0x40000878;
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__nesf2 = 0x4000087c;
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__paritysi2 = 0x40000880;
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__popcountdi2 = 0x40000884;
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__popcountsi2 = 0x40000888;
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__powidf2 = 0x4000088c;
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__powisf2 = 0x40000890;
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__subdf3 = 0x40000894;
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__subsf3 = 0x40000898;
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__subvdi3 = 0x4000089c;
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__subvsi3 = 0x400008a0;
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__truncdfsf2 = 0x400008a4;
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__ucmpdi2 = 0x400008a8;
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__udivdi3 = 0x400008ac;
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__udivmoddi4 = 0x400008b0;
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__udivsi3 = 0x400008b4;
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__udiv_w_sdiv = 0x400008b8;
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__umoddi3 = 0x400008bc;
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__umodsi3 = 0x400008c0;
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__unorddf2 = 0x400008c4;
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__unordsf2 = 0x400008c8;
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/* From ESP-IDF:
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* components/esp_rom/esp32c3/ld/esp32c3.rom.newlib.ld
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* These are called during codegen and thus it's a good idea to make them always
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* available. ROM functions may also be faster than functions in IROM (that go
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* through the flash cache) and are always available in interrupts.
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*/
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memset = 0x40000354;
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memcpy = 0x40000358;
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memmove = 0x4000035c;
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