chore: uopdate deps

Cargo.toml

@@ -22,16 +22,16 @@ vendored-libusb = ["rusb/vendored"]
 rand = "0.8"
 log = "0.4.8"
 serde = { version = "1.0.104", features = ["derive"] }
-serde_yaml = "0.8"
-clap = { version = "3.1", features = ["derive"] }
+serde_yaml = "0.9"
+clap = { version = "3", features = ["derive"] }
 anyhow = "1.0"
 rusb = { version = "0.9.1" }
-bitfield = "0.13.2"
+bitfield = "0.14"
 scroll = "0.11"
 simplelog = "0.12"
 hex = "0.4"
 ihex = "3"
-object = { version = "0.28.3", default-features = false, features = [
+object = { version = "0.29", default-features = false, features = [
     "elf",
     "read_core",
     "std",

src/device.rs

@@ -19,6 +19,18 @@ pub struct ChipFamily {
     pub config_registers: Vec<ConfigRegister>,
 }
 
+impl ChipFamily {
+    fn validate(&self) -> Result<()> {
+        for variant in &self.variants {
+            variant.validate()?;
+        }
+        for register in &self.config_registers {
+            register.validate()?;
+        }
+        Ok(())
+    }
+}
+
 /// Represents an MCU chip
 #[derive(Debug, Clone, Serialize, Deserialize)]
 pub struct Chip {
@@ -61,6 +73,15 @@ impl ::std::fmt::Display for Chip {
     }
 }
 
+impl Chip {
+    pub fn validate(&self) -> Result<()> {
+        for reg in &self.config_registers {
+            reg.validate()?;
+        }
+        Ok(())
+    }
+}
+
 /// A u32 config register, with reset values.
 ///
 /// The reset value is NOT the value of the register when the device is reset,
@@ -80,25 +101,50 @@ pub struct ConfigRegister {
     pub fields: Vec<RegisterField>,
 }
 
+impl ConfigRegister {
+    fn validate(&self) -> Result<()> {
+        if self.offset % 4 != 0 {
+            anyhow::bail!("Config register offset must be 4-byte aligned");
+        }
+        for field in &self.fields {
+            field.validate()?;
+        }
+        Ok(())
+    }
+}
+
 /// A range of bits in a register, with a name and a description
 #[derive(Debug, Clone, Serialize, Deserialize)]
 pub struct RegisterField {
-    pub bit_range: std::ops::RangeInclusive<u8>,
+    // RangeInclusive is not supported well since serde_yaml 0.9
+    pub bit_range: Vec<u8>,
     pub name: String,
     #[serde(default)]
     pub description: String,
-    // NOTE: use BTreeMap for strict ordering or digits and `_`
+    // NOTE: use BTreeMap for strict ordering for digits and `_`
     #[serde(default)]
     pub explaination: BTreeMap<String, String>,
 }
 
+impl RegisterField {
+    fn validate(&self) -> Result<()> {
+        if self.bit_range.len() != 2 {
+            anyhow::bail!("Invalid bit range: {:?}", self.bit_range);
+        }
+        if self.bit_range[0] < self.bit_range[1] {
+            anyhow::bail!("Invalid bit range: {:?}", self.bit_range);
+        }
+        Ok(())
+    }
+}
+
 pub struct ChipDB {
     pub families: Vec<ChipFamily>,
 }
 
 impl ChipDB {
     pub fn load() -> Result<Self> {
-        let families = vec![
+        let families: Vec<ChipFamily> = vec![
             serde_yaml::from_str(include_str!("../devices/0x10-CH56x.yaml"))?,
             serde_yaml::from_str(include_str!("../devices/0x11-CH55x.yaml"))?,
             serde_yaml::from_str(include_str!("../devices/0x12-CH54x.yaml"))?,
@@ -111,6 +157,9 @@ impl ChipDB {
             serde_yaml::from_str(include_str!("../devices/0x19-CH32V20x.yaml"))?,
             serde_yaml::from_str(include_str!("../devices/0x19-CH32V20x.yaml"))?,
         ];
+        for family in &families {
+            family.validate()?;
+        }
         Ok(ChipDB { families })
     }
 

src/flashing.rs

@@ -304,16 +304,11 @@ impl<T: Transport> Flashing<T> {
             }
 
             for field_def in &reg_def.fields {
-                let bit_width =
-                    (field_def.bit_range.start() - field_def.bit_range.end()) as u32 + 1;
-                let b = (n >> field_def.bit_range.end()) & (2_u32.pow(bit_width) - 1);
+                let bit_width = (field_def.bit_range[0] - field_def.bit_range[1]) as u32 + 1;
+                let b = (n >> field_def.bit_range[1]) & (2_u32.pow(bit_width) - 1);
                 println!(
                     "  [{}:{}] {} 0b{:b} (0x{:X})",
-                    field_def.bit_range.start(),
-                    field_def.bit_range.end(),
-                    field_def.name,
-                    b,
-                    b
+                    field_def.bit_range[0], field_def.bit_range[1], field_def.name, b, b
                 );
                 for (val, expain) in &field_def.explaination {
                     if val == "_" || Some(b) == parse_number(val) {

src/lib.rs

@@ -3,9 +3,9 @@
 pub mod constants;
 pub mod device;
 pub mod flashing;
+pub mod format;
 pub mod protocol;
 pub mod transport;
-pub mod format;
 
 pub use self::device::Chip;
 pub use self::flashing::Flashing;