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1.5 KiB
1.5 KiB
CH32V003
RISC-V2A, 16KB Flash, 2KB SRAM, 48MHz.
Note CH32V003 is a riscv32ec core, which is not supported by ofiicial Rust yet. ch32-rs team maintains a fork of Rust at https://github.com/ch32-rs/rust. You can check Noxim's Blog for riscv32ec support.
Debug support
1-wire debug.
SWDIO <-> D1/DIO@MCU, PD1
GND <-> GND@MCU
3V3 <-> 3V3@MCU (No need if you connect your MCU board with USB-C power supply)
- Flash support
- Memory dump support
- Reset / Resume
- Reg read/write support
> wlink -v flash ./firmware.bin
13:41:49 [INFO] WCH-Link v2.8 (WCH-LinkE-CH32V305)
13:41:49 [INFO] attached chip: CH32V003(0x00300500)
13:41:49 [DEBUG] (1) wlink::operations: Chip UID: cd-ab-80-17-48-bc-95-7f
13:41:49 [DEBUG] (1) wlink::operations: flash protected: false
13:41:49 [DEBUG] (1) wlink::operations: SRAM CODE mode: 3
13:41:49 [DEBUG] (1) wlink::operations: already halted
13:41:49 [DEBUG] (1) wlink::operations: RISC-V core version: Some("WCH-V2A")
13:41:49 [INFO] flash 860 bytes
13:41:49 [DEBUG] (1) wlink::operations: Code start address 0x08000000
13:41:49 [DEBUG] (1) wlink::operations: flash op written
13:41:49 [DEBUG] (1) wlink::operations: fastprogram done
13:41:49 [INFO] flash done
13:41:50 [INFO] now reset...
13:41:51 [INFO] resume executing...
13:41:51 [WARN] resume fails
Chips
* CH32V003F4P6-0x003005x0
* CH32V003F4U6-0x003105x0
* CH32V003A4M6-0x003205x0
* CH32V003J4M6-0x003305x0