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93 lines
2.0 KiB
93 lines
2.0 KiB
18 years ago
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BDMR4102
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BDMR4102
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Description
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The BDMR4102 is the evaluation board for the 4102 TinyRISC Processor. It
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comes with it's own special power supply.
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Memory Map
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On the LR4102, the memory map is determined by how the chip-select
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registers have been programmed. The only thing that's fixed is the GP
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number to which each peripheral is connected.
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RAM GP3 SRAM 128KB
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GP2 SDRAM 16MB Module (optional) (must be located
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on a 32MB boundary).
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ROM GP0 1 eprom socket
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bfd0.0000 when not configured as boot device
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DUART GP4 16550
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Flash GP0 29F080 1MB.
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bfd0.0000 when not configured as boot device
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Ethernet PCI AMD 79C970A 10BaseT only
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Interrupts
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int0 ?
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int1 timer0
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int2 SerialICE Port
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int3 timer1+(16550 scr1:cpc1en=1)
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int4 Am79C970A Ethernet
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int5 ?
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External Connections
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Power - 5V DC via coaxial power connector
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RS232
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J10 16550 (PMON console)
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J9 SerialICE Port via level shifters
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SerialICE
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J8 SerialICE Port direct
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Clocks
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U?Clock for CPU.
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U6Clock for SerialICE Port.
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1.8432MHz=115200, 20MHz=1250000.
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Jumpers
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Jumper In Jumper Out
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JP6 Little Endian Big Endian
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JP9 Boot from EPROMBoot from flash
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JP15
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1-2 - J9 is connected to the SerialICE Port through level translators.
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This requires that the onboard osc be selected and installed.
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2-3 - Connect J8 (the SerialICE header) to the SerialICE Port.
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JP161-2 SerialICE Port Clock comes from oscillator (U6)
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2-3 SerialICE Port Clock comes from SerialICE Port connector.
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A board will always transmit it's osc clock to the connector.
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It is swapped with the clock input on the other board in the cable.
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IceKernel
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� For the wiggler: JP15 2-3, JP16 1-2.
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� For tty1: JP15 1-2, JP16 1-2.
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Seven-segment Display
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Address: UART base + 0x20
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01
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-----
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20 | | 02
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----- 40
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10 | | 04
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----- o 80
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08
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Note: the specified value turns the selected segment off.
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��������������������������������������������������������������������������������
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Navigation:
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Document Home |
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Document Contents |
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Document Index
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