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73 lines
1.4 KiB
73 lines
1.4 KiB
10 years ago
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/*whd : loongson3_fixup.S
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used to fix up the potential addressing miss
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caused by speculated execution
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*/
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#if 1
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#set XBAR to route all the DMA request to Scache0
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#define SINGLE_SCACHE
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#ifdef SINGLE_SCACHE
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dli a0,0xf #using 37:36
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#else
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//dli a0,0x2 #using 11:10
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dli a0,0xb #using 29:28
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#endif
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dli t0,0x900000003ff00400
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sd a0,0x0(t0)
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#if 0//config L1 xbar cpu port
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dli t2, 0x900000003ff02000
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dli t1, 0x900000003ff02400
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TTYDBG("Using Scache 3 \r\n")
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1:
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dli t0, 0x0000000000000000
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sd t0, 0x00(t2)
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dli t0, 0x0000000000000000
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sd t0, 0x40(t2)
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dli t0, 0x00000000000000f3
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sd t0, 0x80(t2)
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#endif
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PRINTSTR("Scache index setup done\r\n")
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#endif
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#if 1//config L1 xbar cpu port
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dli t2, 0x900000003ff02000
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dli t1, 0x900000003ff02400
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TTYDBG("Fix L1xbar illegal access \r\n")
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1:
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#ifndef MULTI_CHIP
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####### address space to other nodes ############
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// dli t0, 0x0000200000000000
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// sd t0, 0x30(t2)
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// dli t0, 0x0000200000000000
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// sd t0, 0x70(t2)
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// dli t0, 0x00002000000000f7
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// sd t0, 0xb0(t2)
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//
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// dli t0, 0x0000100000000000
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// sd t0, 0x38(t2)
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// dli t0, 0x0000300000000000
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// sd t0, 0x78(t2)
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// dli t0, 0x00001000000000f7
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// sd t0, 0xb8(t2)
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dli t0, 0x0000000000000000
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sd t0, 0x38(t2)
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dli t0, 0x0000000000000000
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sd t0, 0x78(t2)
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dli t0, 0x00000000000000f0
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sd t0, 0xb8(t2)
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daddiu t2, t2, 0x100
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bne t2, t1, 1b
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nop
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#endif
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#endif
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