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100 lines
2.8 KiB
100 lines
2.8 KiB
15 years ago
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/*--------------------------------------------------------------------------*/
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//add by lycheng(liych@3adawning.com.cn)
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#define PCI_ADDR(BUS, DEV, FN, WHERE) ( \
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(((BUS) & 0xFF) << 16) | \
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(((DEV) & 0x1f) << 11) | \
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(((FN) & 0x07) << 8) | \
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((WHERE) & 0xFF))
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#define PCI_DEV(BUS, DEV, FN) ( \
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(((BUS) & 0xFF) << 16) | \
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(((DEV) & 0x1f) << 11) | \
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(((FN) & 0x7) << 8))
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#define CPU_POST_PORT 0xbff00080
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#define HT_CONFIG_ADDR 0x90000efdfe000000 //type0: 0x90000efdfe000000 type1:0x90000efdff000000
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#define NBMISC_INDEX 0x60
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//end by lycheng
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//lycheng
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PRINTSTR("\r\n enable rs780 dev8...\r\n")
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nop
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bal enable_rs780_dev8
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nop
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PRINTSTR("\r\n test GPPSB\r\n")
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li a0, 0x0
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li a1, 0x0
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bal nbmisc_read_index_mips
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nop
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li t0, 0x40 // (1 << 6)
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and v1, v0, t0
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bnez v1, 1f
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nop
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PRINTSTR("\r\n Enabled GPPSB fail...\r\n")
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nop
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b 2f
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nop
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1:
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PRINTSTR("\r\n Enabled GPPSB success...\r\n")
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nop
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2:
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PRINTSTR("\r\n sb700 lpc init...\r\n")
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nop
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/* sb700_lpc_init();*/
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/* SMBUS controller */
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/* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! */
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PRINTSTR("\r\n set boottimerdisable\r\n")
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li a0, PCI_DEV(0x0,0x14,0x0)
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li a1, 0x4C
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bal pci_read_config32_mips
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nop
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or a2, v0, 1<<31
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bal pci_write_config32_mips
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nop
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PRINTSTR("\r\n enable lpc controller\r\n")
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/* Enable lpc controller */
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li a1, 0x64
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bal pci_read_config32_mips
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nop
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or a2, v0, 1<<20
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bal pci_write_config32_mips
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nop
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PRINTSTR("\r\n enable port 80 LPC decode\r\n")
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/* Enable port 80 LPC decode in pci function 3 configuration space. */
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li a0, PCI_DEV(0x0, 0x14, 0x3)
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li a1, 0x4a
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bal pci_read_config8_mips
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nop
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or a2, v0, 1<<5
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bal pci_write_config8_mips
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nop
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/* Decode port 0x3f8-0x3ff (Serial 0) */
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PRINTSTR("\r\n Decode port 0x3f8-0x3ff\r\n")
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li a1, 0x44
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bal pci_read_config8_mips
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nop
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or a2, v0, 1<<6
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bal pci_write_config8_mips
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nop
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/* Decode port 0x60 & 0x64 (PS/2 keyboard) and port 0x62 & 0x66 (ACPI)*/
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PRINTSTR("\r\n Decode port 0x60-0x66\r\n")
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li a1, 0x47
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bal pci_read_config8_mips
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nop
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or a2, v0, (1<<5)|(1<<6)
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bal pci_write_config8_mips
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nop
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PRINTSTR("\r\n SuperIO RTC\r\n")
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/* SuperIO, RTC */
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li a1, 0x48
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bal pci_read_config8_mips
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nop
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or a2, v0, (1<<1)|(1<<0)|(1<<6)
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bal pci_write_config8_mips
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nop
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li a0, 0x01
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bal post_code_mips
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nop
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