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154 lines
7.0 KiB
154 lines
7.0 KiB
18 years ago
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/* $Id: powerpc.h,v 1.1.1.1 2006/09/14 01:59:06 root Exp $ */
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/*
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* Copyright (c) 2001 ipUnplugged AB (www.ipunplugged.com)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for Patrik Lindergren, by
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* ipUnplugged AB, Sweden.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* PowerPC Special Registers
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*/
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#define CTR 9
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#define SPRG0 272
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#define SPRG1 273
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#define SPRG2 274
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#define SPRG3 275
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#define PVR 287
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#define HID0 1008
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#define HID1 1009
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#define L2CR 1017
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/*
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* Hardware Implementation-Dependent Register 0 (HID0)
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*/
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#define HID0_NMCP 0x80000000 /* Enable MCP */
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#define HID0_EBA 0x20000000 /* Enable/Disable system bus address parity check */
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#define HID0_EBD 0x10000000 /* Enable/Disable system bus data parity check */
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#define HID0_BCLK 0x08000000 /* CLK_OUT output enable aned clock selection */
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#define HID0_ECLK 0x02000000 /* CLK_OUT output enable aned clock selection */
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#define HID0_PAR 0x01000000 /* Disable precharge of ARTRY* amd SHD[0] or SHD[1] */
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#define HID0_DOZE 0x00800000 /* Doze Mode Enable */
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#define HID0_NAP 0x00400000 /* NAP Mode enable */
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#define HID0_SLEEP 0x00200000 /* Sleep Mode Enable */
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#define HID0_DPM 0x00100000 /* Dynamic Power Management enable */
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#define HID0_EIEC 0x00040000 /* Enable internal error checking */
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#define HID0_NHR 0x00010000 /* Not hard reset */
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#define HID0_ICE 0x00008000 /* Instruction Cache Enable */
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#define HID0_DCE 0x00004000 /* Data Cache enable */
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#define HID0_ILOCK 0x00002000 /* Instruction cache Lock */
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#define HID0_DLOCK 0x00001000 /* Data cache Lock*/
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#define HID0_ICFI 0x00000800 /* Instruction cache invalidate */
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#define HID0_DCFI 0x00000400 /* Data cache flash invalidate */
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#define HID0_SPD 0x00000200 /* Speculative data and instruction cache */
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#define HID0_IFTT 0x00000100 /* I-Fetch TTx encoding differentiation */
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#define HID0_SGE 0x00000080 /* Store gathering enable */
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#define HID0_DCFA 0x00000040 /* Data Cache Flush assist */
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#define HID0_BTIC 0x00000020 /* Branch Target Instruction Cache enable */
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#define HID0_BHTE 0x00000004 /* Branch History Table enable */
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#define HID0_NOPDST 0x00000002 /* No-Op dst, dstt, dstst and dststt instructions */
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#define HID0_NOPTI 0x00000001 /* No-Op the data cache touch instructions */
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/* Defines for MPC740/750/7400 L2-Cache register L2CR */
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#define L2CR_L2E (0x80000000) /* Enable cache */
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#define L2CR_L2PE (0x40000000) /* Parity enable */
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#define L2CR_L2SIZ_256 (0x10000000) /* Cache of 256KB */
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#define L2CR_L2SIZ_512 (0x20000000) /* Cache of 512KB */
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#define L2CR_L2SIZ_1024 (0x30000000) /* Cache of 1024KB */
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#define L2CR_L2SIZ_2048 (0x00000000) /* Cache of 2048KB */
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#define L2CR_L2CLK_DIS (0x00000000) /* Disable DLL+CLK */
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#define L2CR_L2CLK_1 (0x02000000) /* Div by 1 */
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#define L2CR_L2CLK_15 (0x04000000) /* Div by 1.5 */
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#define L2CR_L2CLK_35 (0x06000000) /* Div by 3.5 */
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#define L2CR_L2CLK_2 (0x08000000) /* Div by 2 */
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#define L2CR_L2CLK_25 (0x0A000000) /* Div by 2.5 */
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#define L2CR_L2CLK_3 (0x0C000000) /* Div by 3 */
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#define L2CR_L2CLK_4 (0x0E000000) /* Div by 4 */
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#define L2CR_L2CLK_SPEED_MSK (0x10) /* Cache speed mask */
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#define L2CR_L2RAM_FLOW (0x00000000) /* flow sync burst RAM*/
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#define L2CR_L2RAM_RES (0x00800000) /* reserved */
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#define L2CR_L2RAM_PIPE (0x01000000) /* pipl sync burst RAM*/
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#define L2CR_L2RAM_LATEW (0x01800000) /* late write sync RAM*/
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#define L2CR_L2DO (0x00400000) /* Enable Data only caching*/
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#define L2CR_L2I (0x00200000) /* Enable Cache Invalidation*/
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#define L2CR_L2CTL (0x00100000) /* Enable low power mode ZZ */
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#define L2CR_L2WT (0x00080000) /* Enable write-thru mode */
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#define L2CR_L2TS (0x00040000) /* Enable test mode */
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#define L2CR_L2OH_05 (0x00000000) /* Output hold of 0.5ns */
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#define L2CR_L2OH_10 (0x00010000) /* Output hold of 1.0ns */
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#define L2CR_L2OH_MOUT (0x00020000) /* more output hold */
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#define L2CR_L2OH_EMOUT (0x00030000) /* even more output hold */
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#define L2CR_L2SL (0x00008000) /* Enable DLL slow for L2-clock < 100MHz*/
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#define L2CR_L2DF (0x00004000) /* Enable differential clock pins */
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#define L2CR_L2BYP (0x00002000) /* Enable DLL bypass */
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#define L2CR_L2FA (0x00001000) /* Flush Assist bit */
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#define L2CR_L2HWF (0x00000800) /* Start HW flusg operation of L2 Cache */
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#define L2CR_L2IO (0x00000400) /* L2 Instruction cache only enable */
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#define L2CR_L2CLKSTP (0x00000200) /* Enable clock stop to L2 cache rams */
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#define L2CR_L2DRO (0x00000100) /* Roll-over enable for DLL */
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#define L2CR_L2CTR (0x000000FE) /* Mask for L2CR_L2CTR DLL 127..0 counter */
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#define L2CR_L2IP (0x00000001) /* RO, Indicate invalidate in progress */
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/*
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* Machine State Register (MSR)
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*/
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#define PPC_MSR_FP 0x00002000
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#define GETHID1(x) \
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__asm __volatile("mfspr %0, 1009" : "=r"(x));
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#ifdef __ASSEMBLER__
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#define HIADJ(x) (x)@ha
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#define HI(x) (x)@h
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#define LO(x) (x)@l
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/*
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* Use this macro to prevent reordering by as/ld and processor
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*/
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#define IORDER eieio; sync
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/*
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* Macros used to setup BAT regs.
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*/
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#define IBAT_SETUP(batno, batuval, batlval) \
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lis 3, HIADJ(batuval); addi 3, 3, LO(batuval); \
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lis 4, HIADJ(batlval); addi 4, 4, LO(batlval); \
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mtibatu batno, 3; mtibatl batno, 4
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#define DBAT_SETUP(batno, batuval, batlval) \
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lis 3, HIADJ(batuval); addi 3, 3, LO(batuval); \
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lis 4, HIADJ(batlval); addi 4, 4, LO(batlval); \
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mtdbatu batno, 3; mtdbatl batno, 4
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#endif /* __ASSEMBLER__ */
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