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/*
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* Bonito Register Map
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* Copyright (c) 1999 Algorithmics Ltd
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*
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* Algorithmics gives permission for anyone to use and modify this file
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* without any obligation or license condition except that you retain
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* this copyright message in any source redistribution in whole or part.
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*
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* Updated copies of this and other files can be found at
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* ftp://ftp.algor.co.uk/pub/bonito/
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*
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* Users of the Bonito controller are warmly recommended to contribute
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* any useful changes back to Algorithmics (mail to
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* bonito@algor.co.uk).
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*/
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/* Revision 1.48 autogenerated on 08/17/99 15:20:01 */
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#ifndef _FCR_H__
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#ifdef __ASSEMBLER__
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#else /* !__ASSEMBLER */
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extern char *heaptop;
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#endif /* __ASSEMBLER__ */
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/* APB bus control registers */
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#define APB_MISC_BASE 0x1f004100
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#define GPIO_OE28_0 0x00
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#define GPIO_R28_0 0x10
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#define GPIO_W28_0 0x20
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#define APB_MISC_CTL 0x40
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/*
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#define GPIO_OE47_20 0x00
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#define GPIO_OE77_48 0x08
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#define GPIO_R47_20 0x10
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#define GPIO_R77_48 0x18
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#define GPIO_W47_20 0x20
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#define GPIO_W77_48 0x28
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#define APB_MISC_CTL 0x40
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*/
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#define AHB_MISC_BASE 0x1f003200
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#define GPIO_OE60_29 0x20
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#define GPIO_R60_29 0x24
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#define GPIO_W60_29 0x28
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#define RTC_INDEX_REG 0x70
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#define RTC_DATA_REG 0x71
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#define RTC_NVRAM_BASE 0x0e
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#define COM2_BASE_ADDR 0xbfd003f8
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#define COM3_BASE_ADDR 0xbf004080
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#define COM1_BASE_ADDR 0xbf004080
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//#define NS16550HZ 1843200
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//#define NS16550HZ (33350000/4)
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#define NS16550HZ (APB_CLK/4)
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/*********************************************************************/
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/*nvram define */
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/*********************************************************************/
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#ifdef NVRAM_IN_FLASH
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# define NVRAM_SIZE 494
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# define NVRAM_SECSIZE 500
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# define NVRAM_OFFS 0x0007f000
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# define ETHER_OFFS 494 /* Ethernet address base */
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#else /* Use clock ram, 256 bytes only */
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# define NVRAM_SIZE 114
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# define NVRAM_SECSIZE NVRAM_SIZE /* Helper */
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# define NVRAM_OFFS 0
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# define ETHER_OFFS 108 /* Ethernet address base */
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#endif
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/*********************************************************************/
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/*PCI map */
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/*********************************************************************/
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#ifdef X86_LIKE_SPACE
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/* To make address spaces alike with x86 system, we put sdram
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* start address at 0 and pci devices' start address at 0x14000000 for
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* both CPU address space & PCI memory address space.
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*
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* We have 3 64M window in CPU address space to access PCI memory,but the
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* legacy PCI start pci memory from 0x10000000, so we can use the same address to access
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* them from cpu memory space. But to access the 0xc0000 vga ram, we have to
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* reserve the first window. Only the last two are used for pci devices.
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* --zfx 060716
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*/
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/* make sdram appear at both cpu & pci memory space 0,
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* so for dma the physical address can be directly used
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* as bus address. --zfx 060716
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*/
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#define PCI_MEM_SPACE_PCI_BASE 0x10000000
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#define PCI_LOCAL_MEM_PCI_BASE 0x00000000
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#define PCI_LOCAL_MEM_ISA_BASE 0x80000000
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#define PCI_LOCAL_REG_PCI_BASE 0x90000000
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#else
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#define PCI_MEM_SPACE_PCI_BASE 0x00000000
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#define PCI_LOCAL_MEM_PCI_BASE 0x80000000
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#define PCI_LOCAL_MEM_ISA_BASE 0x00800000
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#define PCI_LOCAL_REG_PCI_BASE 0x90000000
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#endif
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#define PCI_IO_SPACE_BASE 0x00000000
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#endif /* _BONITO_H_ */
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