update ls3a3000 7a1000 clock setting.

Change-Id: I2562c65a141c03818d32b3b23ebc04684136fd3c
Signed-off-by: QiaoChong <qiaochong@loongson.cn>

Targets/Bonito3a3000_7a/Bonito/loongson3_clksetting.S

@@ -19,6 +19,7 @@ ATTENTION:
 #define USE_LS_PLL 1
 #define DDR_SEL_ST 0
 
+#ifndef CORE_FREQ
 #ifdef  MULTI_CHIP
 #define CORE_FREQ   1400
 #define DDR_FREQ    660
@@ -26,6 +27,7 @@ ATTENTION:
 #define CORE_FREQ   1400
 #define DDR_FREQ    600
 #endif
+#endif
 
 #define DDR_REFC    1   //do not modify
 #if (DDR_FREQ < 400)
@@ -33,9 +35,9 @@ ATTENTION:
 #else
 #define DDR_DIV     4
 #endif
-#define DDR_LOOPC  (DDR_FREQ*DDR_DIV/33)   //72 //600MHz
-//#define DDRPLL_IN 33 
-//#define DDR_LOOPC  DDR_FREQ*DDR_DIV*DDR_REFC/DDRPLL_IN
+//#define DDR_LOOPC  (DDR_FREQ*DDR_DIV/33)   //72 //600MHz
+#define DDRPLL_IN 33 
+#define DDR_LOOPC  DDR_FREQ*DDR_DIV*DDR_REFC/DDRPLL_IN
 
 // L1_* define core frequency
 #define LS_PLL  USE_LS_PLL
@@ -43,7 +45,7 @@ ATTENTION:
 
 #define L1_REFC     1   //do not modify
 #define L1_DIV      2
-#define L1_LOOPC    (CORE_FREQ*L1_DIV/25)
+//#define L1_LOOPC    (CORE_FREQ*L1_DIV/25)
 
 #ifdef REF_33M
 #define CPUPLL_IN 33
@@ -51,9 +53,11 @@ ATTENTION:
 #define CPUPLL_IN 100
 #elif defined(REF_25M)
 #define CPUPLL_IN 25
+#else
+#define CPUPLL_IN 25
 #endif
 
-//#define L1_LOOPC CORE_FREQ*L1_DIV*L1_REFC/CPUPLL_IN
+#define L1_LOOPC CORE_FREQ*L1_DIV*L1_REFC/CPUPLL_IN
 
 #define BYPASS_CORE 0x0
 #define BYPASS_NODE 0x0