diff --git a/Targets/Bonito2fdev/conf/Bonito.2fdev.via b/Targets/Bonito2fdev/conf/Bonito.2fdev.via
index 004a0f24..0d30f8aa 100644
--- a/Targets/Bonito2fdev/conf/Bonito.2fdev.via
+++ b/Targets/Bonito2fdev/conf/Bonito.2fdev.via
@@ -168,3 +168,5 @@ option FLOATINGPT
 option PCI_IDSEL_VIA686B=17
 option WDC_NORESET
 select gzip
+option INPUT_FROM_BOTH
+option OUTPUT_TO_BOTH
diff --git a/sys/dev/pci/cs5536.c b/sys/dev/pci/cs5536.c
index 33833041..9b4a5d85 100644
--- a/sys/dev/pci/cs5536.c
+++ b/sys/dev/pci/cs5536.c
@@ -368,6 +368,7 @@ void cs5536_ohci_init(void)
 
 void cs5536_i8259_init(void)
 {
+	int hi,lo;
 	outb(CS5536_LEGACY_BASE_ADDR | 0x20, 0x11); /* Initialization sequence (8259A-1). */
 	outb(CS5536_LEGACY_BASE_ADDR | 0xA0, 0x11); /* Initialization sequence (8259A-2). */
 	outb(CS5536_LEGACY_BASE_ADDR | 0x21, 0x0);  /* Start of hardware INTs (0x20). */
@@ -381,6 +382,15 @@ void cs5536_i8259_init(void)
 	outb(CS5536_LEGACY_BASE_ADDR | 0x21, 0xFB); /* Mask all IRQs but IRQ2 is cascaded.*/
 //	outb(CS5536_LEGACY_BASE_ADDR | 0xA1, 0x00); /* Mask off all interrupts for now. */
 //	outb(CS5536_LEGACY_BASE_ADDR | 0x21, 0x00); /* Mask all IRQs but IRQ2 is cascaded.*/
+	_rdmsr(DIVIL_MSR_REG(PIC_IRQM_LPC), &hi, &lo);
+	lo |= 0x1002;
+	_wrmsr(DIVIL_MSR_REG(PIC_IRQM_LPC), hi, lo);
+	_rdmsr(DIVIL_MSR_REG(PIC_IRQM_PRIM), &hi, &lo);
+	lo &=~(0x1002) ;
+	_wrmsr(DIVIL_MSR_REG(PIC_IRQM_PRIM), hi, lo);
+	_rdmsr(DIVIL_MSR_REG(LPC_SIRQ), &hi, &lo);
+	lo |=0xc0 ;
+	_wrmsr(DIVIL_MSR_REG(LPC_SIRQ), hi, lo);			
 	return;
 }
 
diff --git a/zloader/Makefile.inc b/zloader/Makefile.inc
index 9af54d1b..38599053 100755
--- a/zloader/Makefile.inc
+++ b/zloader/Makefile.inc
@@ -1,7 +1,7 @@
 CC=mips-elf-gcc
 GZROMSTARTADDR=0xffffffff81000000
 ROMSTARTADDR=0xffffffff80010000
-RAMSTARTADDR=0xffffffff80200000
+RAMSTARTADDR=0xffffffff88000000
 export CC += ${MYCC}
 
 ifdef obj