diff --git a/Targets/Bonito3a82h/Bonito/start.S b/Targets/Bonito3a82h/Bonito/start.S
index 5bb0b63a..4e5303c6 100644
--- a/Targets/Bonito3a82h/Bonito/start.S
+++ b/Targets/Bonito3a82h/Bonito/start.S
@@ -561,6 +561,7 @@ after_ht:
 #endif
 //#define DEBUG_AUTO_ARB_LEVEL
 #endif
+//#define DISABLE_DDR_A15
 //#define DEBUG_DDR
 //#define DEBUG_DDR_PARAM
 
diff --git a/Targets/Bonito3a82w/Bonito/start.S b/Targets/Bonito3a82w/Bonito/start.S
index bf7631fc..6cb36eef 100644
--- a/Targets/Bonito3a82w/Bonito/start.S
+++ b/Targets/Bonito3a82w/Bonito/start.S
@@ -699,6 +699,7 @@ no_reboot:
 #endif
 //#define DEBUG_AUTO_ARB_LEVEL
 #endif
+//#define DISABLE_DDR_A15
 //#define DEBUG_DDR
 //#define DEBUG_DDR_PARAM
 
diff --git a/Targets/Bonito3a84w/Bonito/start.S b/Targets/Bonito3a84w/Bonito/start.S
index 4ae9b233..2e0beba1 100644
--- a/Targets/Bonito3a84w/Bonito/start.S
+++ b/Targets/Bonito3a84w/Bonito/start.S
@@ -516,6 +516,7 @@ no_reboot:
 #endif
 //#define DEBUG_AUTO_ARB_LEVEL
 #endif
+//#define DISABLE_DDR_A15
 //#define DEBUG_DDR
 //#define DEBUG_DDR_PARAM
 //#define DEBUG_DDR_NODE
diff --git a/Targets/Bonito3a8780e/Bonito/start.S b/Targets/Bonito3a8780e/Bonito/start.S
index efa99458..01d214d0 100644
--- a/Targets/Bonito3a8780e/Bonito/start.S
+++ b/Targets/Bonito3a8780e/Bonito/start.S
@@ -569,7 +569,7 @@ soft_out:
 #endif
 //#define DEBUG_AUTO_ARB_LEVEL
 #endif
-#define  DDR_ADDR_PIN_15
+#define  DISABLE_DDR_A15
 //#define DEBUG_DDR
 //#define DEBUG_DDR_PARAM
 
diff --git a/Targets/Bonito3a92h/Bonito/start.S b/Targets/Bonito3a92h/Bonito/start.S
index 4555ce5a..8b5b5f3d 100644
--- a/Targets/Bonito3a92h/Bonito/start.S
+++ b/Targets/Bonito3a92h/Bonito/start.S
@@ -692,7 +692,7 @@ soft_out:
 #endif
 //#define DEBUG_DDR
 //#define DEBUG_DDR_PARAM
-#define DDR_ADDR_PIN_15
+#define DISABLE_DDR_A15
 #define PRINT_DDR_LEVELING 
 
 	TTYDBG("\r\nStart Init Memory, wait a while......\r\n")
diff --git a/Targets/Bonito3a92w/Bonito/start.S b/Targets/Bonito3a92w/Bonito/start.S
index ed3a8a6d..7c231436 100644
--- a/Targets/Bonito3a92w/Bonito/start.S
+++ b/Targets/Bonito3a92w/Bonito/start.S
@@ -504,6 +504,7 @@ no_reboot:
 #endif
 //#define DEBUG_AUTO_ARB_LEVEL
 #endif
+//#define DISABLE_DDR_A15
 //#define DEBUG_DDR
 //#define DEBUG_DDR_PARAM
 
diff --git a/Targets/Bonito3a94w/Bonito/start.S b/Targets/Bonito3a94w/Bonito/start.S
index 6330b5ac..a31ccb53 100644
--- a/Targets/Bonito3a94w/Bonito/start.S
+++ b/Targets/Bonito3a94w/Bonito/start.S
@@ -516,6 +516,7 @@ no_reboot:
 #endif
 //#define DEBUG_AUTO_ARB_LEVEL
 #endif
+//#define DISABLE_DDR_A15
 //#define DEBUG_DDR
 //#define DEBUG_DDR_PARAM
 //#define DEBUG_DDR_NODE
diff --git a/Targets/Bonito3a9780e/Bonito/start.S b/Targets/Bonito3a9780e/Bonito/start.S
index 1c758515..f0402609 100644
--- a/Targets/Bonito3a9780e/Bonito/start.S
+++ b/Targets/Bonito3a9780e/Bonito/start.S
@@ -684,7 +684,7 @@ soft_out:
 #endif
 //#define DEBUG_AUTO_ARB_LEVEL
 #endif
-#define  DDR_ADDR_PIN_15
+#define  DISABLE_DDR_A15
 //#define DEBUG_DDR
 //#define DEBUG_DDR_PARAM
 //#define DISABLE_HARD_LEVELING
diff --git a/Targets/Bonito3a9780e/conf/Bonito.3a9780e b/Targets/Bonito3a9780e/conf/Bonito.3a9780e
index 687b1cae..4a8802b9 100644
--- a/Targets/Bonito3a9780e/conf/Bonito.3a9780e
+++ b/Targets/Bonito3a9780e/conf/Bonito.3a9780e
@@ -21,7 +21,6 @@ option		TARGETNAME="\"Bonito\""
 # Platform options
 #
 option      loongson3A3
-option      LS_DDR_HALF
 option      LSMC_2
 #option      ARB_LEVEL
 option      DDR3_DIMM
diff --git a/pmon/arch/mips/mm/loongson3A2000_ddr2_config.S b/pmon/arch/mips/mm/loongson3A2000_ddr2_config.S
index 3bccef3f..95b0c4db 100644
--- a/pmon/arch/mips/mm/loongson3A2000_ddr2_config.S
+++ b/pmon/arch/mips/mm/loongson3A2000_ddr2_config.S
@@ -112,7 +112,7 @@
 #endif
 
 
-#ifdef LS_DDR_HALF
+#ifdef DISABLE_DDR_A15
 #ifndef LSMCD3_2
 //hot fix for lack of address pin A15 when use LSMC. For example RS780E R1.03
     //check MC1 first
diff --git a/pmon/arch/mips/mm/loongson3_ddr2_config.S b/pmon/arch/mips/mm/loongson3_ddr2_config.S
index 1cdb591c..336788f2 100644
--- a/pmon/arch/mips/mm/loongson3_ddr2_config.S
+++ b/pmon/arch/mips/mm/loongson3_ddr2_config.S
@@ -181,7 +181,7 @@
 #endif
 
 #ifndef LSMCD3_2
-#ifdef  DDR_ADDR_PIN_15
+#ifdef  DISABLE_DDR_A15
 //hot fix for lack of address pin A15 when use LSMC. For example RS780E R1.03
     //check MC1 first
     move    t1, s1  //store s1