From 141cd086bb9fe2bc3e22a6011f8a1fe193dd7e80 Mon Sep 17 00:00:00 2001 From: Huang Shuai Date: Thu, 3 Jan 2019 16:59:01 +0800 Subject: [PATCH] fix bug caused by misuse of t3 reg, which will lead to panic Change-Id: Ibe2485ff6c5cc58d9d2db4b6d395aba00a9a4891 --- pmon/arch/mips/ls7a/ls7a_init.S | 96 ++++++++++++++++----------------- 1 file changed, 48 insertions(+), 48 deletions(-) diff --git a/pmon/arch/mips/ls7a/ls7a_init.S b/pmon/arch/mips/ls7a/ls7a_init.S index 5702ca93..9b393649 100644 --- a/pmon/arch/mips/ls7a/ls7a_init.S +++ b/pmon/arch/mips/ls7a/ls7a_init.S @@ -1085,14 +1085,14 @@ cal_one_pcie_x8: sw a0, 0x10(t3) dli t1, 0x90000e0060000000 - li t3, (0x1<<18) - not t3, t3 + li a1, (0x1<<18) + not a1, a1 lw a0, 0x54(t1) - and a0, a0, t3 + and a0, a0, a1 sw a0, 0x54(t1) lw a0, 0x58(t1) - and a0, a0, t3 + and a0, a0, a1 sw a0, 0x58(t1) @@ -1147,14 +1147,14 @@ cal_one_pcie_x8: sw a0, 0x10(t3) dli t1, 0x90000e0060100000 - li t3, (0x1<<18) - not t3, t3 + li a1, (0x1<<18) + not a1, a1 lw a0, 0x54(t1) - and a0, a0, t3 + and a0, a0, a1 sw a0, 0x54(t1) lw a0, 0x58(t1) - and a0, a0, t3 + and a0, a0, a1 sw a0, 0x58(t1) dli t1, 0x90000e0060100000 @@ -1196,14 +1196,14 @@ cal_one_pcie_x8: sw a0, 0x10(t3) dli t1, 0x90000e0060200000 - li t3, (0x1<<18) - not t3, t3 + li a1, (0x1<<18) + not a1, a1 lw a0, 0x54(t1) - and a0, a0, t3 + and a0, a0, a1 sw a0, 0x54(t1) lw a0, 0x58(t1) - and a0, a0, t3 + and a0, a0, a1 sw a0, 0x58(t1) dli t1, 0x90000e0060200000 @@ -1245,14 +1245,14 @@ cal_one_pcie_x8: sw a0, 0x10(t3) dli t1, 0x90000e0060300000 - li t3, (0x1<<18) - not t3, t3 + li a1, (0x1<<18) + not a1, a1 lw a0, 0x54(t1) - and a0, a0, t3 + and a0, a0, a1 sw a0, 0x54(t1) lw a0, 0x58(t1) - and a0, a0, t3 + and a0, a0, a1 sw a0, 0x58(t1) dli t1, 0x90000e0060300000 @@ -1349,14 +1349,14 @@ cal_one_pcie_x8: sw a0, 0x10(t3) dli t1, 0x90000e0060000000 - li t3, (0x1<<18) - not t3, t3 + li a1, (0x1<<18) + not a1, a1 lw a0, 0x54(t1) - and a0, a0, t3 + and a0, a0, a1 sw a0, 0x54(t1) lw a0, 0x58(t1) - and a0, a0, t3 + and a0, a0, a1 sw a0, 0x58(t1) dli t1, 0x90000e0060000000 @@ -1410,14 +1410,14 @@ cal_one_pcie_x8: sw a0, 0x10(t3) dli t1, 0x90000e0060100000 - li t3, (0x1<<18) - not t3, t3 + li a1, (0x1<<18) + not a1, a1 lw a0, 0x54(t1) - and a0, a0, t3 + and a0, a0, a1 sw a0, 0x54(t1) lw a0, 0x58(t1) - and a0, a0, t3 + and a0, a0, a1 sw a0, 0x58(t1) dli t1, 0x90000e0060100000 @@ -1529,14 +1529,14 @@ cal_one_pcie_x8: sw a0, 0x10(t3) dli t1, 0x90000e0060000000 - li t3, (0x1<<18) - not t3, t3 + li a1, (0x1<<18) + not a1, a1 lw a0, 0x54(t1) - and a0, a0, t3 + and a0, a0, a1 sw a0, 0x54(t1) lw a0, 0x58(t1) - and a0, a0, t3 + and a0, a0, a1 sw a0, 0x58(t1) dli t1, 0x90000e0060000000 @@ -1590,14 +1590,14 @@ cal_one_pcie_x8: sw a0, 0x10(t3) dli t1, 0x90000e0060100000 - li t3, (0x1<<18) - not t3, t3 + li a1, (0x1<<18) + not a1, a1 lw a0, 0x54(t1) - and a0, a0, t3 + and a0, a0, a1 sw a0, 0x54(t1) lw a0, 0x58(t1) - and a0, a0, t3 + and a0, a0, a1 sw a0, 0x58(t1) dli t1, 0x90000e0060100000 @@ -1709,14 +1709,14 @@ cal_one_pcie_x8: sw a0, 0x10(t3) dli t1, 0x90000e0060000000 - li t3, (0x1<<18) - not t3, t3 + li a1, (0x1<<18) + not a1, a1 lw a0, 0x54(t1) - and a0, a0, t3 + and a0, a0, a1 sw a0, 0x54(t1) lw a0, 0x58(t1) - and a0, a0, t3 + and a0, a0, a1 sw a0, 0x58(t1) @@ -1771,14 +1771,14 @@ cal_one_pcie_x8: sw a0, 0x10(t3) dli t1, 0x90000e0060100000 - li t3, (0x1<<18) - not t3, t3 + li a1, (0x1<<18) + not a1, a1 lw a0, 0x54(t1) - and a0, a0, t3 + and a0, a0, a1 sw a0, 0x54(t1) lw a0, 0x58(t1) - and a0, a0, t3 + and a0, a0, a1 sw a0, 0x58(t1) dli t1, 0x90000e0060100000 @@ -1890,14 +1890,14 @@ cal_one_pcie_x8: sw a0, 0x10(t3) dli t1, 0x90000e0060000000 - li t3, (0x1<<18) - not t3, t3 + li a1, (0x1<<18) + not a1, a1 lw a0, 0x54(t1) - and a0, a0, t3 + and a0, a0, a1 sw a0, 0x54(t1) lw a0, 0x58(t1) - and a0, a0, t3 + and a0, a0, a1 sw a0, 0x58(t1) dli t1, 0x90000e0060000000 @@ -1951,14 +1951,14 @@ cal_one_pcie_x8: sw a0, 0x10(t3) dli t1, 0x90000e0060100000 - li t3, (0x1<<18) - not t3, t3 + li a1, (0x1<<18) + not a1, a1 lw a0, 0x54(t1) - and a0, a0, t3 + and a0, a0, a1 sw a0, 0x54(t1) lw a0, 0x58(t1) - and a0, a0, t3 + and a0, a0, a1 sw a0, 0x58(t1) dli t1, 0x90000e0060100000