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last version before 3A1

master
wanghuandong 15 years ago
parent
97b5c8ef0d
commit
18385c1998
5 changed files with 875 additions and 764 deletions
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  1. 1044
      Targets/Bonito3amcp68/Bonito/loongson3_HT_init.S
  2. 169
      Targets/Bonito3amcp68/Bonito/loongson3_ddr2_config.S
  3. 212
      Targets/Bonito3amcp68/Bonito/loongson3_ddr_debug.S
  4. 185
      Targets/Bonito3amcp68/Bonito/loongson3_fixup.S
  5. 29
      Targets/Bonito3amcp68/Bonito/start.S

1044
Targets/Bonito3amcp68/Bonito/loongson3_HT_init.S
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File diff suppressed because it is too large

169
Targets/Bonito3amcp68/Bonito/loongson3_ddr2_config.S
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@ -1,40 +1,50 @@
###Enable the reg space###
#if 1
TTYDBG ("Enable register space of MEMORY\r\n")
li t2,0xbfe00180
lw a1, 0x0(t2)
li a0, 0xfffffeff
and a1,a1,a0
sw a1,0x0(t2)
#endif
//#define MC0_ONLY
/*whd : loongson3_ddr2_config.S
used to set up all ddr controllers
and set up the memory space on L2 Xbar
*/
#######################################################
/* Undefine the two to enable both */
#define MC0_ONLY
//#define MC1_ONLY
/* Size of each DDR controller */
//#define DDR_512
#define DDR_1G
/* Interleave pattern when both controller enabled */
//#define INTERLEAVE_27
//#define INTERLEAVE_13
//#define INTERLEAVE_12
#define INTERLEAVE_11
#######################################################
###Enable the reg space###
#if 1
TTYDBG ("Enable register space of MEMORY\r\n")
li t2, 0xbfe00180
lw a1, 0x0(t2)
li a0, 0xfffffeff
and a1, a1,a0
sw a1, 0x0(t2)
#endif
#ifdef DDR_1G
#ifdef MC0_ONLY
li msize,0x3f000000
dfadf
li msize, 0x3f000000
#else
#ifdef MC1_ONLY
li msize,0x3f000000
li msize, 0x3f000000
#else
li msize,0x7f000000
li msize, 0x7f000000
#endif
#endif
#else
#ifdef DDR_512
li msize,0x1f000000
li msize, 0x1f000000
#else
li msize,0x0f000000
li msize, 0x0f000000
#endif
#endif
@ -94,7 +104,6 @@
dli t0, 0x900000003ff00090 #mmap
dli t1, 0x000000f0
sd t1, 0(t0)
sync
#else
#ifdef MC1_ONLY
@ -110,7 +119,6 @@
dli t0, 0x900000003ff00090 #mmap
dli t1, 0x000000f1
sd t1, 0(t0)
sync
#else
#ifdef INTERLEAVE_27
@ -139,7 +147,6 @@
dli t0, 0x900000003ff00098 #mmap
dli t1, 0x000000f1
sd t1, 0(t0)
sync
#else
#ifdef INTERLEAVE_13
PRINTSTR("DDR Interleave space open : 0x00000000 - 0x0FFFFFFF\r\n")
@ -167,7 +174,33 @@
dli t0, 0x900000003ff00098 #mmap
dli t1, 0x00000000000000f1
sd t1, 0(t0)
sync
#else
#ifdef INTERLEAVE_12
PRINTSTR("DDR Interleave space open : 0x00000000 - 0x0FFFFFFF\r\n")
PRINTSTR("DDR Interleave using Bit 12\r\n")
dli t0, 0x900000003ff00010 #base
dli t1, 0x0000000000000000
sd t1, 0(t0)
dli t0, 0x900000003ff00050 #mask
dli t1, 0xfffffffff0001000
sd t1, 0(t0)
dli t0, 0x900000003ff00090 #mmap
dli t1, 0x00000000000000f0
sd t1, 0(t0)
dli t0, 0x900000003ff00018 #base
dli t1, 0x0000000000001000
sd t1, 0(t0)
dli t0, 0x900000003ff00058 #mask
dli t1, 0xfffffffff0001000
sd t1, 0(t0)
dli t0, 0x900000003ff00098 #mmap
dli t1, 0x00000000000000f1
sd t1, 0(t0)
#else
#ifdef INTERLEAVE_11
PRINTSTR("DDR Interleave space open : 0x00000000 - 0x0FFFFFFF\r\n")
@ -195,7 +228,6 @@
dli t0, 0x900000003ff00098 #mmap
dli t1, 0x00000000000000f1
sd t1, 0(t0)
sync
#else
PRINTSTR("DDR Interleave space open : 0x00000000 - 0x0FFFFFFF\r\n")
dli t0, 0x900000003ff00010 #base
@ -209,7 +241,6 @@
dli t0, 0x900000003ff00090 #mmap
dli t1, 0x00000000000000f0
sd t1, 0(t0)
sync
dli t0, 0x900000003ff00018 #base
dli t1, 0x0000000000000400
@ -222,7 +253,7 @@
dli t0, 0x900000003ff00098 #mmap
dli t1, 0x00000000000000f1
sd t1, 0(t0)
sync
#endif
#endif
#endif
#endif
@ -234,22 +265,21 @@
#ifdef DDR_512
PRINTSTR("MC0 pace open : 0x20000000 - 0x2FFFFFFF\r\n")
dli t0, 0x900000003ff00020 #base
dli t1, 0x20000000
dli t1, 0x0000000020000000
sd t1, 0(t0)
dli t0, 0x900000003ff00060 #mask
dli t1, 0xffffffffe0000000
dli t1, 0xfffffffff0000000
sd t1, 0(t0)
dli t0, 0x900000003ff000a0 #mmap
dli t1, 0x100000f0
dli t1, 0x00000000100000f0
sd t1, 0(t0)
sync
#else
#ifdef DDR_1G
PRINTSTR("MC0 space open : 0x40000000 - 0x7FFFFFFF\r\n")
dli t0, 0x900000003ff00020 #base
dli t1, 0x40000000
dli t1, 0x0000000040000000
sd t1, 0(t0)
dli t0, 0x900000003ff00060 #mask
@ -257,9 +287,8 @@
sd t1, 0(t0)
dli t0, 0x900000003ff000a0 #mmap
dli t1, 0x000000f0
dli t1, 0x00000000000000f0
sd t1, 0(t0)
sync
#endif
#endif
@ -269,22 +298,21 @@
#ifdef DDR_512
PRINTSTR("MC1 space open : 0x20000000 - 0x2FFFFFFF\r\n")
dli t0, 0x900000003ff00020 #base
dli t1, 0x20000000
dli t1, 0x0000000020000000
sd t1, 0(t0)
dli t0, 0x900000003ff00060 #mask
dli t1, 0xffffffffe0000000
dli t1, 0xfffffffff0000000
sd t1, 0(t0)
dli t0, 0x900000003ff000a0 #mmap
dli t1, 0x100000f1
dli t1, 0x00000000100000f1
sd t1, 0(t0)
sync
#else
#ifdef DDR_1G
PRINTSTR("MC1 space open : 0x40000000 - 0x7FFFFFFF\r\n")
dli t0, 0x900000003ff00020 #base
dli t1, 0x40000000
dli t1, 0x0000000040000000
sd t1, 0(t0)
dli t0, 0x900000003ff00060 #mask
@ -292,9 +320,8 @@
sd t1, 0(t0)
dli t0, 0x900000003ff000a0 #mmap
dli t1, 0x000000f1
dli t1, 0x00000000000000f1
sd t1, 0(t0)
sync
#endif
#endif
@ -334,8 +361,6 @@
dli t1, 0x00000000080000F1
sd t1, 0xb8(t0)
sync
#else
#ifdef INTERLEAVE_13
PRINTSTR("DDR Interleave space open : 0x80000000 - 0xFFFFFFFF\r\n")
@ -371,7 +396,40 @@
dli t1, 0x00000000000020F1
sd t1, 0xb8(t0)
sync
#else
#ifdef INTERLEAVE_12
PRINTSTR("DDR Interleave space open : 0x80000000 - 0xFFFFFFFF\r\n")
PRINTSTR("DDR Interleave using Bit 12\r\n")
dli t0, 0x900000003ff00000 #base
dli t1, 0x0000000080000000
sd t1, 0x20(t0)
dli t1, 0xFFFFFFFFC0001000
sd t1, 0x60(t0)
dli t1, 0x00000000000000F0
sd t1, 0xa0(t0)
dli t1, 0x0000000080001000
sd t1, 0x28(t0)
dli t1, 0xFFFFFFFFC0001000
sd t1, 0x68(t0)
dli t1, 0x00000000000000F1
sd t1, 0xa8(t0)
dli t1, 0x00000000C0000000
sd t1, 0x30(t0)
dli t1, 0xFFFFFFFFC0001000
sd t1, 0x70(t0)
dli t1, 0x00000000000010F0
sd t1, 0xb0(t0)
dli t1, 0x00000000C0001000
sd t1, 0x38(t0)
dli t1, 0xFFFFFFFFC0001000
sd t1, 0x78(t0)
dli t1, 0x00000000000010F1
sd t1, 0xb8(t0)
#else
#ifdef INTERLEAVE_11
@ -408,8 +466,6 @@
dli t1, 0x00000000000008F1
sd t1, 0xb8(t0)
sync
#else
PRINTSTR("DDR Interleave space open : 0x80000000 - 0xFFFFFFFF\r\n")
@ -443,14 +499,14 @@
dli t1, 0x00000000000004F1
sd t1, 0xb8(t0)
sync
#endif
#endif
#endif
#endif
#endif
#endif
sync
#if 0 //print registers
li t1, 152 ##0x72
@ -471,6 +527,7 @@ reg_read:
#if 0 /* read ddr2 registers */
/* No use in Loongson 3A */
li t0, 0xaff00000
not_locked:
@ -481,40 +538,40 @@ not_locked:
PRINTSTR("DDR2 DLL locked\r\n")
ld t1, 0xf0(t0)
ld t1, 0xf0(t0)
move a0, t1
bal hexserial
nop
#endif
###disable the reg space###
###disable the reg space###
#if 1
TTYDBG ("Disable register space of MEMORY\r\n")
TTYDBG("Disable register space of MEMORY\r\n")
li t2,0xbfe00180
lw a1,0x0(t2)
or a1,a1,0x100
sw a1,0x0(t2)
#endif
#endif
#if 1 // AdonWang disable ddr3 readbuff
#if 0 // AdonWang disable ddr3 readbuff
/* !!!!!!!!!! IMPORTANT !!!!!!!!!! */
TTYDBG("Disable read buffer\r\n")
li t0,0xbfe00180
li t0, 0xbfe00180
//dli t1,0x1ffffff617
//dli t1,0x07fffff617
//dli t2,0x4000000000
//or t1,t1,t2
lw t1, 0x4(t0)
li a0, 0x18
or t1, t1, a0
sw t1,0x4(t0)
li a0, 0x18
or t1, t1, a0
sw t1, 0x4(t0)
#endif
#if 1 // AdonWang disable cpu buffered read
/* !!!!!!!!!! IMPORTANT !!!!!!!!!! */
TTYDBG("Disable cpu buffered read\r\n")
li t0,0xbfe00180
li t0, 0xbfe00180
lw t1, 0x0(t0)
li a0, 0xfffffdff
and t1, t1, a0

212
Targets/Bonito3amcp68/Bonito/loongson3_ddr_debug.S
View File

@ -1204,7 +1204,7 @@ uncache_test:
nop
#endif
#if 1 //all space scan whd
#if 0 //all space scan whd
#define SPACE_1G_AT_MC1
#define SPACE_2G
#ifdef 0
@ -1835,11 +1835,11 @@ tmem:
beq t1, t0, 2f
nop
and t4, t1, 0x000fffff
bnez t4, skipdot
bnez t4, skipdot_0
li a0, '.'
bal tgt_putchar
nop
skipdot:
skipdot_0:
b 1b
nop
1:
@ -1871,7 +1871,16 @@ skipdot:
#endif
#if 0 /* Read adustment */
#if 1 /* Read adustment */
//#define SLICE_0
#define SLICE_1
TTYDBG ("Enable register space of MEMORY\r\n")
li t2, 0xbfe00180
lw a1, 0x0(t2)
li a0, 0xfffffeff
and a1, a1,a0
sw a1, 0x0(t2)
//CACHE WRITE whd
TTYDBG("Write \r\n")
li t0, 0x80000400
@ -1900,32 +1909,36 @@ skipdot:
li t0, 0x80000400
cache 23, 0x0(t0) //HitWBInvalidate_S
//SLICE 0: Set Delay of DQS
#ifdef SLICE_0
dli t0, 0
dli t1, 0xff
li v0, 0
li v1, 0
//SLICE 0: Set Delay of DQS
set_0:
TTYDBG("SLICE 0.\r\n")
TTYDBG("Posedge.\r\n")
pos_set_0:
li t2, 0xaff001f0
ld a0, 0x0(t2)
li a1, 0xffff00ffffffffff
dli a1, 0xffff00ffffffffff
and a0, a0, a1
dsll a1, t0, 40
or a0, a0, a1
sd a0, 0x0(t2)
TTYDBG("\r\nLOOP until value change done.\r\n")
li t1, 0xfffffff #360Mhz
//TTYDBG("\r\nLOOP until value change done.\r\n")
li a2, 0x1fffffff #360Mhz
1:
bnez t1, 1b
addi t1, t1, -1
bnez a2, 1b
addi a2, a2, -1
TTYDBG("LOOP done.\r\n")
//TTYDBG("LOOP done.\r\n")
TTYDBG(".")
//Test DQS
read_right_0:
read_posedge_0:
li t2, 0xa0000400
lw a0, 0x0(t2)
li a1, 0x000000ff
@ -1934,23 +1947,190 @@ read_right_0:
daddi t0, t0, 1
bne a0, a1, set_0
bne a0, a1, pos_set_0
nop
lw a0, 0x10(t2)
li a1, 0x000000ff
and a0, a0, a1
li a1, 0x55
bne a0, a1, set_0
bne a0, a1, pos_set_0
nop
addi v0, t0, -1
move a0, v0
bal hexserial
nop
TTYDBG("\r\n")
bne t0, t1, pos_set_0
nop
TTYDBG("\r\nNegedge.\r\n")
dli t0, 0
dli t1, 0xff
li v0, 0
li v1, 0
neg_set_0:
li t2, 0xaff00240
ld a0, 0x0(t2)
li a1, 0xffffffffffff00ff
and a0, a0, a1
dsll a1, t0, 8
or a0, a0, a1
sd a0, 0x0(t2)
//TTYDBG("\r\nLOOP until value change done.\r\n")
li a2, 0x1fffffff #360Mhz
1:
bnez a2, 1b
addi a2, a2, -1
//TTYDBG("LOOP done.\r\n")
TTYDBG(".")
//Test DQS
read_negedge_0:
li t2, 0xa0000408
lw a0, 0x0(t2)
li a1, 0x000000ff
and a0, a0, a1
li a1, 0x66
daddi t0, t0, 1
bne a0, a1, neg_set_0
nop
lw a0, 0x10(t2)
li a1, 0x000000ff
and a0, a0, a1
li a1, 0xaa
bne a0, a1, neg_set_0
nop
addi v0, t0, -1
move a0, v0
bal hexserial
nop
TTYDBG("\r\n")
bne t0, t1, neg_set_0
nop
#endif
//SLICE 1: Set Delay of DQS
#ifdef SLICE_1
dli t0, 0
dli t1, 0xff
li v0, 0
li v1, 0
TTYDBG("SLICE 1.\r\n")
TTYDBG("Posedge.\r\n")
pos_set_1:
li t2, 0xaff00200
ld a0, 0x0(t2)
dli a1, 0xffffffffffff00ff
and a0, a0, a1
dsll a1, t0, 8
or a0, a0, a1
sd a0, 0x0(t2)
//TTYDBG("\r\nLOOP until value change done.\r\n")
li a2, 0x1fffffff #360Mhz
1:
bnez a2, 1b
addi a2, a2, -1
//TTYDBG("LOOP done.\r\n")
TTYDBG(".")
//Test DQS
read_posedge_1:
li t2, 0xa0000400
lw a0, 0x0(t2)
li a1, 0x0000ff00
and a0, a0, a1
li a1, 0x9900
daddi t0, t0, 1
bne a0, a1, pos_set_1
nop
lw a0, 0x10(t2)
li a1, 0x0000ff00
and a0, a0, a1
li a1, 0x5500
bne a0, a1, pos_set_1
nop
addi v0, t0, -1
move a0, v0
bal hexserial
nop
bne t0, t1, set_0
TTYDBG("\r\n")
bne t0, t1, pos_set_1
nop
TTYDBG("\r\nNegedge.\r\n")
dli t0, 0
dli t1, 0xff
li v0, 0
li v1, 0
neg_set_1:
li t2, 0xaff00240
ld a0, 0x0(t2)
li a1, 0xffff00ffffffffff
and a0, a0, a1
dsll a1, t0, 40
or a0, a0, a1
sd a0, 0x0(t2)
//TTYDBG("\r\nLOOP until value change done.\r\n")
li a2, 0x1fffffff #360Mhz
1:
bnez a2, 1b
addi a2, a2, -1
//TTYDBG("LOOP done.\r\n")
TTYDBG(".")
//Test DQS
read_negedge_1:
li t2, 0xa0000408
lw a0, 0x0(t2)
li a1, 0x0000ff00
and a0, a0, a1
li a1, 0x6600
daddi t0, t0, 1
bne a0, a1, neg_set_1
nop
lw a0, 0x10(t2)
li a1, 0x0000ff00
and a0, a0, a1
li a1, 0xaa00
bne a0, a1, neg_set_1
nop
addi v0, t0, -1
move a0, v0
bal hexserial
nop
TTYDBG("\r\n")
bne t0, t1, neg_set_1
nop
#endif
#endif
/*

185
Targets/Bonito3amcp68/Bonito/loongson3_fixup.S
View File

@ -3,10 +3,10 @@
caused by execute speculated
*/
#define SINGLE_SCACHE
#if 0
#set XBAR to route all the DMA request to Scache0
//#define SINGLE_SCACHE
#ifdef SINGLE_SCACHE
dli a0,0xf #using 37:36
#else
@ -25,13 +25,15 @@
TTYDBG("Fix L1xbar illegal access \r\n")
1:
####### Unused HT0 port #########################
dli t0, 0x00000c0000000000
sd t0, 0x30(t2)
sd t0, 0x28(t2)
dli t0, 0xfffffe0000000000
sd t0, 0x70(t2)
sd t0, 0x68(t2)
dli t0, 0x00000c00000000f7
sd t0, 0xb0(t2)
sd t0, 0xa8(t2)
####### address space to other nodes ############
dli t0, 0x0000200000000000
sd t0, 0x30(t2)
dli t0, 0x0000200000000000
@ -80,178 +82,3 @@
#endif
#if 0 /* map 0xexxxx to HT1 */
//map 0x90000e00_00000000
dli t0, 0x900000003ff02000
dli t1, 0x00000e0000000000
sd t1, 0x30(t0)
dli t1, 0xffffff0000000000
sd t1, 0x70(t0)
dli t1, 0x00000000000000f7
sd t1, 0xb0(t0)
//map 0x90000e00_00000000
dli t0, 0x900000003ff02100
dli t1, 0x00000e0000000000
sd t1, 0x30(t0)
dli t1, 0xffffff0000000000
sd t1, 0x70(t0)
dli t1, 0x00000000000000f7
sd t1, 0xb0(t0)
//map 0x90000e00_00000000
dli t0, 0x900000003ff02200
dli t1, 0x00000e0000000000
sd t1, 0x30(t0)
dli t1, 0xffffff0000000000
sd t1, 0x70(t0)
dli t1, 0x00000000000000f7
sd t1, 0xb0(t0)
//map 0x90000e00_00000000
dli t0, 0x900000003ff02300
dli t1, 0x00000e0000000000
sd t1, 0x30(t0)
dli t1, 0xffffff0000000000
sd t1, 0x70(t0)
dli t1, 0x00000000000000f7
sd t1, 0xb0(t0)
/* all address using CACHE 1 */
//map 0x00000000_00000000
dli t0, 0x900000003ff02000
dli t1, 0x0000000000000000
sd t1, 0x38(t0)
dli t1, 0x0000000000000000
sd t1, 0x78(t0)
dli t1, 0x00000000000000f1
sd t1, 0xb8(t0)
//map 0x00000000_00000000
dli t0, 0x900000003ff02100
dli t1, 0x0000000000000000
sd t1, 0x38(t0)
dli t1, 0x0000000000000000
sd t1, 0x78(t0)
dli t1, 0x00000000000000f1
sd t1, 0xb8(t0)
//map 0x00000000_00000000
dli t0, 0x900000003ff02200
dli t1, 0x0000000000000000
sd t1, 0x38(t0)
dli t1, 0x0000000000000000
sd t1, 0x78(t0)
dli t1, 0x00000000000000f1
sd t1, 0xb8(t0)
//map 0x00000000_00000000
dli t0, 0x900000003ff02300
dli t1, 0x0000000000000000
sd t1, 0x38(t0)
dli t1, 0x0000000000000000
sd t1, 0x78(t0)
dli t1, 0x00000000000000f1
sd t1, 0xb8(t0)
TTYDBG("HT RX DMA address TRANSLATE to Scache n\r\n")
dli t2, 0x900000003ff02700
dli t0, 0x0000000000000000
sd t0, 0x0(t2)
dli t2, 0x900000003ff02740
dli t0, 0xffffffff00000000
sd t0, 0x0(t2)
dli t2, 0x900000003ff02780
dli t0, 0xf1
sd t0, 0x0(t2)
sync
#endif
/*
//Core 1
TTYDBG("Fix L1xbar illegal access \r\n")
dli t2, 0x900000003ff02128
dli t0, 0x00000e0000000000
sd t0, 0x0(t2)
dli t2, 0x900000003ff02168
dli t0, 0xffffff0000000000
sd t0, 0x0(t2)
dli t2, 0x900000003ff021a8
dli t0, 0x87
sd t0, 0x0(t2)
dli t2, 0x900000003ff02130
dli t0, 0x00000e0000000000
sd t0, 0x0(t2)
dli t2, 0x900000003ff02170
dli t0, 0xffffff0000000000
sd t0, 0x0(t2)
dli t2, 0x900000003ff021b0
dli t0, 0xf0
sd t0, 0x0(t2)
//Core 2
TTYDBG("Fix L1xbar illegal access \r\n")
dli t2, 0x900000003ff02228
dli t0, 0x00000e0000000000
sd t0, 0x0(t2)
dli t2, 0x900000003ff02268
dli t0, 0xffffff0000000000
sd t0, 0x0(t2)
dli t2, 0x900000003ff022a8
dli t0, 0x87
sd t0, 0x0(t2)
dli t2, 0x900000003ff02230
dli t0, 0x00000e0000000000
sd t0, 0x0(t2)
dli t2, 0x900000003ff02270
dli t0, 0xffffff0000000000
sd t0, 0x0(t2)
dli t2, 0x900000003ff022b0
dli t0, 0xf0
sd t0, 0x0(t2)
//Core 3
TTYDBG("Fix L1xbar illegal access \r\n")
dli t2, 0x900000003ff02328
dli t0, 0x00000e0000000000
sd t0, 0x0(t2)
dli t2, 0x900000003ff02368
dli t0, 0xffffff0000000000
sd t0, 0x0(t2)
dli t2, 0x900000003ff023a8
dli t0, 0x87
sd t0, 0x0(t2)
dli t2, 0x900000003ff02330
dli t0, 0x00000e0000000000
sd t0, 0x0(t2)
dli t2, 0x900000003ff02370
dli t0, 0xffffff0000000000
sd t0, 0x0(t2)
dli t2, 0x900000003ff023b0
dli t0, 0xf0
sd t0, 0x0(t2)
*/

29
Targets/Bonito3amcp68/Bonito/start.S
View File

@ -138,14 +138,6 @@ nop;
#define CP0_DEPC $24
#define CP0_DESAVE $31
#define DDR100 0x1d441091
/*
#define DDR100 0x0c011091*/
#define DDR266 0x0410435e
#define DDR300 0x041453df
#define DDR_DQ 0xbff00030 /* zgj */
/*
* Register usage:
*
@ -1026,7 +1018,7 @@ gs_2f_v3_ddr2_cfg:
TTYDBG("Init tlb...\r\n")
bal tlb_init
nop
TTYDBG("\r\nInit caches...\r\n")
//TTYDBG("Init caches...\r\n")
#if 1
//mfc0 a0, COP_0_PRID
@ -1457,9 +1449,6 @@ END(tgt_putchar)
#define B57600 57600
#define B115200 115200
#define GS3_UART0_BASE 0xbfe001e0
#define GS3_UART1_BASE 0xbfe001e8
#define GS3_UART_BASE GS3_UART0_BASE
LEAF(initserial_uart)
li a0, GS3_UART_BASE
@ -1546,7 +1535,7 @@ LEAF(initserial)
END(initserial)
#else
LEAF(initserial)
li a0, GS3_UART_BASE
li a0, GS3_UART_BASE
li t1,128
# addiu a2,a0,3
@ -1829,6 +1818,8 @@ tlb_flush_all:
1:
###tlb_init finish####
tlbp
jr ra
nop
END(tlb_init)
###############################
LEAF(hexserial64)
@ -2266,11 +2257,6 @@ reg_write_mc1:
.end ddr2_config_mc1
.data
.align 5
data_aaa0:
.dword 0x0
.rdata
.align 5
.global ddr2_reg_data
@ -2289,9 +2275,9 @@ MC0_CTL_050 : .dword 0x0000000404050100
//00000_000 q_fullness(RW) 00000_000 port_data_error_type(RD) 000_00000 out_of_range_type(RD) 00000_000 max_cs_reg(RD) 00000_100 column_size(RW) 0000_0101 caslat(RW) 00000_010 addr_pins(RW) 00000000
MC0_CTL_060 : .dword 0x0a04040603040003
//0000_1010 aprebit(RW) 0000_0101 wrlat(RW) 0000_0100 twtr(RW) 000_00110 twr_int(RW) 00000_011 trtp(RW) 00000_100 trrd(RW) 0000000000000_011 tcke(RW)
MC0_CTL_070 : .dword 0x0f0e020000010a08
MC0_CTL_070 : .dword 0x0f0e020000040a08
//0000_0000 max_row_reg(RD) 0000_0000 max_col_reg(RD) 0000_0000 initaref(RW) 00000000000000000000_1111 cs_map(RW) 000_01010 caslat_lin_gate(RW) 000_01010 caslat_lin(RW)
MC0_CTL_080 : .dword 0x0104040101000400
MC0_CTL_080 : .dword 0x0004000100000000
//0000_0001 odt_wr_map_cs3(RW) 0000_0010 odt_wr_map_cs2(RW) 0000_0100 odt_wr_map_cs1(RW) 0000_1000 odt_wr_map_cs0(RW) 0000_0001 odt_rd_map_cs3(RW) 0000_0010 odt_rd_map_cs2(RW) 0000_0100 odt_rd_map_cs1(RW) 0000_1000 odt_rd_map_cs0(RW)
MC0_CTL_090 : .dword 0x0000050b00000000
//000_00000 ocd_adjust_pup_cs_0(RW) 000_00000 ocd_adjust_pdn_cs_0(RW) 0000_0101 trp(RW) 000_01011 tdal(RW) 000000000000_0000 port_cmd_error_type(RD) 0000000000000000
@ -2473,6 +2459,7 @@ MC0_CTL_8c0 : .dword 0x0004000000000000
MC0_CTL_8d0 : .dword 0x00000000c8000000
MC0_CTL_8e0 : .dword 0x0000000000000050
//MC0_CTL_8f0 : .dword 0x0000000020202080
//MC0_CTL_8f0 : .dword 0x000000002b352180
MC0_CTL_8f0 : .dword 0x000000002b352180
//MC0_CTL_8f0 : .dword 0x0000000040404080
//0000000000000000000000000111100_000000000000000000000000001111000 dll_ctrl_reg_2(RW)
@ -2680,7 +2667,7 @@ MC1_CTL_870 : .dword 0x0046004600460046
//0_000000000000010 emrs1_data_3(RW) 0_000000000000010 emrs1_data_2(RW) 0_000000000000010 emrs1_data_1(RW) 0_000000000000010 emrs1_data_0(RW)
MC1_CTL_880 : .dword 0x0000000000000000
//MC1_CTL_890 : .dword 0x0a520a520a520a52
MC1_CTL_890 : .dword 0x0a520a520a520a52
MC1_CTL_890 : .dword 0x0a5a0a5a0a5a0a52
//0_000010000010000 mrs_data_3(RW) 0_000010000010000 mrs_data_2(RW) 0_000010000010000 mrs_data_1(RW) 0_000010000010000 mrs_data_0(RW)
MC1_CTL_8a0 : .dword 0x00000000001c001c
MC1_CTL_8b0 : .dword 0x0000000000000000

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