Huang Pei
10 years ago
66 changed files with 24283 additions and 0 deletions
@ -0,0 +1,99 @@ |
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/*--------------------------------------------------------------------------*/ |
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//add by lycheng(liych@3adawning.com.cn) |
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#define PCI_ADDR(BUS, DEV, FN, WHERE) ( \ |
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(((BUS) & 0xFF) << 16) | \ |
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(((DEV) & 0x1f) << 11) | \ |
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(((FN) & 0x07) << 8) | \ |
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((WHERE) & 0xFF)) |
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#define PCI_DEV(BUS, DEV, FN) ( \ |
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(((BUS) & 0xFF) << 16) | \ |
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(((DEV) & 0x1f) << 11) | \ |
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(((FN) & 0x7) << 8)) |
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#define CPU_POST_PORT 0xbff00080 |
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#define HT_CONFIG_ADDR 0x90000efdfe000000 //type0: 0x90000efdfe000000 type1:0x90000efdff000000 |
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#define NBMISC_INDEX 0x60 |
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|
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//end by lycheng |
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|
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//lycheng |
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PRINTSTR("\r\n enable rs780 dev8...\r\n") |
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nop |
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bal enable_rs780_dev8 |
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nop |
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// PRINTSTR("\r\n test GPPSB\r\n") |
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li a0, 0x0 |
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li a1, 0x0 |
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bal nbmisc_read_index_mips |
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nop |
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li t0, 0x40 // (1 << 6) |
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and v1, v0, t0 |
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bnez v1, 1f |
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nop |
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PRINTSTR("\r\n Enabled GPPSB fail...\r\n") |
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nop |
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b 2f |
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nop |
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1: |
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PRINTSTR("\r\n Enabled GPPSB success...\r\n") |
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nop |
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2: |
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PRINTSTR("\r\n sb700 lpc init...\r\n") |
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nop |
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/* sb700_lpc_init();*/ |
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/* SMBUS controller */ |
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/* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! */ |
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PRINTSTR("\r\n set boottimerdisable\r\n") |
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li a0, PCI_DEV(0x0,0x14,0x0) |
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li a1, 0x4C |
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bal pci_read_config32_mips |
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nop |
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or a2, v0, 1<<31 |
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bal pci_write_config32_mips |
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nop |
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PRINTSTR("\r\n enable lpc controller\r\n") |
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/* Enable lpc controller */ |
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li a1, 0x64 |
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bal pci_read_config32_mips |
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nop |
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or a2, v0, 1<<20 |
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bal pci_write_config32_mips |
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nop |
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PRINTSTR("\r\n enable port 80 LPC decode\r\n") |
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/* Enable port 80 LPC decode in pci function 3 configuration space. */ |
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li a0, PCI_DEV(0x0, 0x14, 0x3) |
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li a1, 0x4a |
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bal pci_read_config8_mips |
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nop |
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or a2, v0, 1<<5 |
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bal pci_write_config8_mips |
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nop |
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/* Decode port 0x3f8-0x3ff (Serial 0) */ |
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PRINTSTR("\r\n Decode port 0x3f8-0x3ff\r\n") |
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li a1, 0x44 |
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bal pci_read_config8_mips |
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nop |
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or a2, v0, 1<<6 |
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bal pci_write_config8_mips |
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nop |
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/* Decode port 0x60 & 0x64 (PS/2 keyboard) and port 0x62 & 0x66 (ACPI)*/ |
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PRINTSTR("\r\n Decode port 0x60-0x66\r\n") |
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li a1, 0x47 |
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bal pci_read_config8_mips |
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nop |
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or a2, v0, (1<<5)|(1<<6) |
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bal pci_write_config8_mips |
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nop |
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|
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PRINTSTR("\r\n SuperIO RTC\r\n") |
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/* SuperIO, RTC */ |
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li a1, 0x48 |
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bal pci_read_config8_mips |
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nop |
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or a2, v0, (1<<1)|(1<<0)|(1<<6) |
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bal pci_write_config8_mips |
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nop |
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li a0, 0x01 |
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bal post_code_mips |
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nop |
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|
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|
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@ -0,0 +1,20 @@ |
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|
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TTYDBG("cww X2 fixup \r\n") |
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############ PCI Space |
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dli t2, 0x900000003ff00090 |
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dli t0, 0x0000000000000000 |
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sd t0, 0x0(t2) |
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|
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dli t2, 0x900000003ff00050 |
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dli t0, 0xffffffffc0000000 |
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sd t0, 0x0(t2) |
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|
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dli t2, 0x900000003ff00010 |
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dli t0, 0x0000000040000000 |
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sd t0, 0x0(t2) |
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|
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dli t2, 0x900000003ff00090 |
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dli t0, 0x00000000000000f0 |
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sd t0, 0x0(t2) |
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@ -0,0 +1 @@ |
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../../../pmon/arch/mips/mm |
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@ -0,0 +1,229 @@ |
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################## DMA memory-to-memory test ##################### |
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/* |
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* This test is used for detecting HT controller's rx_buff bug. |
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* This bug may cause system hang when the first DMA & IRQ request emit. |
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* DMA read & write can detect this bug if operation not complete. |
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* |
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* ch5 & ch6 are ch0 & ch1 in DMAC2 indeed. |
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* |
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* Fixme: DMAC1 is not work in this platform, and channel4 in DMAC2 either. |
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* It semms memory-to-memory mode must use the channel4,5 if use DMAC2. |
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* Now I have to use channel5,6 to emulate memory-to-memory operation, |
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* Although the result is wrong, DMA read & write commands are done. |
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*/ |
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|
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#define DMA2_CMD_REG 0xD0 /* w */ |
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#define DMA2_STATUS_REG 0xD0 /* r */ |
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#define DMA2_REQ_REG 0xD2 |
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#define DMA2_MASK_REG 0xD4 |
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#define DMA2_MODE_REG 0xD6 |
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#define DMA2_CLEAR_REG 0xD8 |
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#define DMA2_MASK_ALL_REG 0xDE |
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|
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#define CH5_PAGE_REG 0x8B |
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#define CH5_ADDR_REG 0xC4 |
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#define CH5_COUNT_REG 0xC6 |
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|
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#define CH6_PAGE_REG 0x89 |
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#define CH6_ADDR_REG 0xC8 |
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#define CH6_COUNT_REG 0xCA |
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|
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/* |
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* This function is same as linux_outb_p in C code |
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* Notice: |
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* port --- should be limited in 16 bits |
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* val --- 8 bits |
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* this code use macro BONITO_PCIIO_BASE_VA defined in bonito.h |
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* |
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* v0 & v1 will be change if after function executing |
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*/ |
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#define mips_outb_p(val, port)\ |
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li v0, (val);\ |
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li v1, BONITO_PCIIO_BASE_VA + (port);\ |
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sb v0, 0(v1);\ |
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nop;\ |
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nop;\ |
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nop;\ |
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nop;\ |
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nop;\ |
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nop;\ |
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nop |
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|
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#define mips_inb_p(port)\ |
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li v1, BONITO_PCIIO_BASE_VA + (port);\ |
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lb v0, 0(v1);\ |
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nop;\ |
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nop;\ |
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nop;\ |
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nop;\ |
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nop;\ |
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nop;\ |
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nop |
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|
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#define mips_outw_p(val, port)\ |
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li v0, (val);\ |
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li v1, BONITO_PCIIO_BASE_VA + (port);\ |
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sw v0, 0(v1);\ |
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nop;\ |
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nop;\ |
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nop;\ |
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nop;\ |
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nop;\ |
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nop;\ |
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nop |
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|
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#define mips_inw_p(port)\ |
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li v1, BONITO_PCIIO_BASE_VA + (port);\ |
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lw v0, 0(v1);\ |
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nop;\ |
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nop;\ |
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nop;\ |
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nop;\ |
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nop;\ |
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nop;\ |
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nop |
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|
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|
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/* some code I don't know, but needed by DMA */ |
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|
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#define AX_INDXC 0 |
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#define AX_INDXP 1 |
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#define AXCFG 2 |
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#define ABCFG 3 |
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|
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#define AB_INDX 0xCD8 |
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#define AB_DATA 0xCDC |
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|
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#define alink_ab_indx(type, reg, mask, val)\ |
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mips_outw_p((type & 3) << 30 | reg, AB_INDX);\ |
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mips_inw_p(AB_DATA);\ |
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li a0, ~mask;\ |
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li a1, val;\ |
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and v0, v0, a0;\ |
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or a0, v0, a1;\ |
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mips_outw_p(((type & 3) << 30 | reg), AB_INDX);\ |
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li v1, BONITO_PCIIO_BASE_VA + AB_DATA;\ |
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sb a0, 0(v1);\ |
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nop |
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|
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#define alink_ax_indx(type, reg, mask, val)\ |
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mips_outw_p(type << 30 | type << 3 | 0x30, AB_INDX);\ |
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mips_outw_p(reg, AB_INDX);\ |
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mips_outw_p(type << 30 | type << 3 | 0x34, AB_INDX);\ |
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mips_inw_p(AB_DATA);\ |
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li a0, ~mask;\ |
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li a1, val;\ |
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and v0, v0, a0;\ |
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or a0, v0, a1;\ |
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mips_outw_p(type << 30 | type << 3 | 0x30, AB_INDX);\ |
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mips_outw_p(reg, AB_INDX);\ |
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mips_outw_p(type << 30 | type << 3 | 0x34, AB_INDX);\ |
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li v1, BONITO_PCIIO_BASE_VA + AB_DATA;\ |
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sb a0, 0(v1);\ |
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nop |
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|
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#define CH0 0 |
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#define CH1 1 |
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#define CH2 2 |
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#define CH3 3 |
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#define SINGLE_MODE 1 |
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#define BLOCK_MODE 2 |
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#define WRITE_MODE 1 |
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#define READ_MODE 2 |
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|
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#define MODE_SHIFT 6 |
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#define TRANSFER_TYPE_SHIFT 2 |
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#define CHANNEL_SELECT_SHIFT 0 |
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|
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#define CH5_MODE ((BLOCK_MODE << MODE_SHIFT) | \ |
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(WRITE_MODE << TRANSFER_TYPE_SHIFT) | \ |
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(CH1 << CHANNEL_SELECT_SHIFT)) |
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|
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#define CH6_MODE ((BLOCK_MODE << MODE_SHIFT) | \ |
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(READ_MODE << TRANSFER_TYPE_SHIFT) | \ |
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(CH2 << CHANNEL_SELECT_SHIFT)) |
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|
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#define SRC_ADDR 0x00000000 //(bus address, 0x8000_0000 in cpu's eyes) |
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#define DST_ADDR 0x00000040 //(bus address, 0x8000_0040 in cpu's eyes) |
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#define TRANSFER_LEN 0x10 |
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|
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/* this procedure only use 5 regs(a0, a1, v0, v1, ra)*/ |
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dma_test: |
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############ prepare for DMA testing ########### |
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/* set A-link bridge register address base which I can't understand */ |
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dli a1, 0x90000efdfe00a0f0 |
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li a0, 0xcd8 |
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sw a0, 0(a1) |
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|
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dli a1, 0x90000efdfe000004 |
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lw a0, 0(a1) |
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ori a0, a0, 7 |
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sw a0, 0(a1) |
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|
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dli a1, 0x90000efdfe000090 |
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li a0, 0xffffffff |
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sw a0, 0(a1) |
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|
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/* I can't find any descrition about 0xcd8 & 0xcdc in AMD documents */ |
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alink_ab_indx(AXCFG, 0x4, (1<<2), (1<<2)) |
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alink_ax_indx(AX_INDXC, 0x21, 0xff, 0) |
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|
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############ begin to test DMA ########### |
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/* enable all channel on DMA2 */ |
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mips_outb_p(0, DMA2_MASK_ALL_REG) |
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|
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/* mask ch5 & ch6 before initialize */ |
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mips_outb_p(4|1, DMA2_MASK_REG) |
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mips_outb_p(4|2, DMA2_MASK_REG) |
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|
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/* clear any transfer which are currently executing */ |
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mips_outb_p(0, DMA2_CLEAR_REG) |
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mips_outb_p(0, DMA2_CLEAR_REG) |
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|
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/* setting ch5 & ch6 mode */ |
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mips_outb_p(CH5_MODE, DMA2_MODE_REG) |
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mips_outb_p(CH6_MODE, DMA2_MODE_REG) |
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|
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/* Notice: DMAC2 transfer is base on 2-bytes, |
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* address and length is not in unit of byte */ |
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|
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/* setting transfer read address*/ |
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mips_outb_p((SRC_ADDR>>1) & 0xff, CH6_ADDR_REG) |
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mips_outb_p((SRC_ADDR>>9) & 0xff, CH6_ADDR_REG) |
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mips_outb_p((SRC_ADDR>>17) & 0xff, CH6_PAGE_REG) |
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|
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/* setting transfer write address */ |
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mips_outb_p((DST_ADDR>>1) & 0xff, CH5_ADDR_REG) |
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mips_outb_p((DST_ADDR>>9) & 0xff, CH5_ADDR_REG) |
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mips_outb_p((DST_ADDR>>17) & 0xff, CH5_PAGE_REG) |
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|
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/* send the tranfer length, assume length is not great than 256 bytes */ |
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mips_outb_p((TRANSFER_LEN >> 1) - 1, CH5_COUNT_REG) |
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mips_outb_p(0, CH5_COUNT_REG) |
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mips_outb_p((TRANSFER_LEN >> 1) - 1, CH6_COUNT_REG) |
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mips_outb_p(0, CH6_COUNT_REG) |
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|
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/* enable ch5 & ch6*/ |
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mips_outb_p(CH2, DMA2_MASK_REG) |
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mips_outb_p(CH1, DMA2_MASK_REG) |
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|
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/* send the request */ |
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mips_outb_p((4 | CH2), DMA2_REQ_REG) |
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mips_outb_p((4 | CH1), DMA2_REQ_REG) |
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|
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/* start this transfer*/ |
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mips_outb_p(7, DMA2_CMD_REG) |
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|
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/* wait until DMA done or HT bus hang */ |
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1: |
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mips_inb_p(DMA2_STATUS_REG) |
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li a0, ((1 << CH1) | (1 << CH2)) |
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bne v0, a0, 1b |
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nop |
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|
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/* check bus is hang or not */ |
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mips_inb_p(0x70) |
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|
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/* jr ra */ |
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nop |
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@ -0,0 +1,546 @@ |
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#define CP0_HWRENA $7 |
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|
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#.align 7 /* bfc00480 */ |
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//////////////////////////////////////////// |
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/* only concern mem copy in bios now */ |
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/* used below addres to simulate virtual EJTAG registers */ |
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/* for DUMP ALL registers and restore context */ |
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/* COMMON USED REGISTERS */ |
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#define EJTAG_V0 0xff200000 |
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#define EJTAG_V1 0xff200008 |
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#define EJTAG_A0 0xff200010 |
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#define EJTAG_A1 0xff200018 |
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#define EJTAG_A2 0xff200020 |
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#define EJTAG_A3 0xff200028 |
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#define EJTAG_T0 0xff200030 |
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#define EJTAG_T1 0xff200038 |
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#define EJTAG_T2 0xff200040 |
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#define EJTAG_T3 0xff200048 |
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#define EJTAG_T4 0xff200050 |
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#define EJTAG_T5 0xff200058 |
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#define EJTAG_T6 0xff200060 |
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#define EJTAG_T7 0xff200068 |
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#define EJTAG_T8 0xff200070 |
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#define EJTAG_T9 0xff200078 |
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#define EJTAG_S0 0xff200080 |
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#define EJTAG_S1 0xff200088 |
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#define EJTAG_S2 0xff200090 |
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#define EJTAG_S3 0xff200098 |
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#define EJTAG_S4 0xff2000a0 |
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#define EJTAG_S5 0xff2000a8 |
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#define EJTAG_S6 0xff2000b0 |
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#define EJTAG_S7 0xff2000b8 |
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#define EJTAG_K0 0xff2000c0 |
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#define EJTAG_K1 0xff2000c8 |
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#define EJTAG_GP 0xff2000d0 |
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#define EJTAG_SP 0xff2000d8 |
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#define EJTAG_FP 0xff2000e0 |
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#define EJTAG_RA 0xff2000e8 |
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|
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/* CP0 registers */ |
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#define EJTAG_INDEX 0xff200100 |
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#define EJTAG_RANDOM 0xff200108 |
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#define EJTAG_ENTRYLO0 0xff200110 |
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#define EJTAG_ENTRYLO1 0xff200118 |
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#define EJTAG_CONTEXT 0xff200120 |
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#define EJTAG_PAGEMASK 0xff200128 |
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#define EJTAG_WIRED 0xff200130 |
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#define EJTAG_HWRENA 0xff200138 |
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#define EJTAG_BADVADDR 0xff200140 |
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#define EJTAG_COUNT 0xff200148 |
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#define EJTAG_ENTRYHI 0xff200150 |
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#define EJTAG_COMPARE 0xff200158 |
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#define EJTAG_STATUS 0xff200160 |
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#define EJTAG_CAUSE 0xff200168 |
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#define EJTAG_EPC 0xff200170 |
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#define EJTAG_PRID 0xff200178 |
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#define EJTAG_CONFIG 0xff200180 |
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#define EJTAG_CONFIG1 0xff200188 |
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#define EJTAG_CONFIG2 0xff200190 |
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#define EJTAG_LLADDR 0xff200198 |
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#define EJTAG_WATCHLO 0xff2001a0 |
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#define EJTAG_WATCHHI 0xff2001a8 |
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#define EJTAG_XCONTEXT 0xff2001b0 |
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#define EJTAG_DEPC 0xff2001b8 |
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#define EJTAG_ERROREPC 0xff2001c0 |
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#define EJTAG_DESAVE 0xff2001c8 |
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|
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#define DUMPREGS_START EJTAG_V0 |
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#define DUMPREGS_END EJTAG_DESAVE |
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#define CONTEXT_REGCNT 10 |
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#define REGS_TATOAL 47 |
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#define DUMP_CNT (REGS_TATOAL - CONTEXT_REGCNT) |
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|
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|
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/* for memory access */ |
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#define STATUSREG 0xff200200 /* identify wheter begin to start bios copying */ |
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#define ADDRREG 0xff200208 /* address to access memory or CP0 index */ |
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#define DATAREG 0xff200210 /* value to sotre to mem or move to CP0 */ |
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#define LENGREG 0xff200218 /* length of memory to access */ |
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#define TYPEREG 0xff200220 /* type for access mem or CP0 */ |
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#define DBGREG 0xff200228 /* get data during DBG modle */ |
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#define TLBENREG 0xff200230 /* identify wheterh use TLB */ |
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#define CMDCNTREG 0xff200238 /* identify wheter begin to start bios copying */ |
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#define EPCREG 0xff200240 /* identify wheter begin to start bios copying */ |
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|
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|
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#define CP0_DESAVE $31 |
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|
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//#define CONTEXTREG 0xff200000 |
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#define CONTEXTREG EJTAG_T0 |
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#define STATUSREG 0xff200200 /* identify wheter begin to start bios copying */ |
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#define ADDRREG 0xff200208 /* address to access memory or CP0 index */ |
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#define DATAREG 0xff200210 /* value to sotre to mem or move to CP0 */ |
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#define LENGREG 0xff200218 /* length of memory to access */ |
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#define TYPEREG 0xff200220 /* type for access mem or CP0 */ |
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#define DBGREG 0xff200228 /* type for access mem or CP0 */ |
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#define TLBENREG 0xff200230 /* identify whether enabel TLB DUMP */ |
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#define CMDCNTREG 0xff200238 /* cmd counter */ |
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#define EPCREG 0xff200240 /* cmd counter */ |
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|
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//#define BIOS_ENTRY 0xa1000000 /* cmd counter */ |
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#define BIOS_ENTRY 0x80010000 /* cmd counter */ |
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|
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/********************************************/ |
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// type |
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#define BYTE 0 |
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#define HALF 1 |
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#define WORD 2 |
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#define DWORD 3 |
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// mem |
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#define CP0 1 |
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#define MEM 0 |
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// dircetion |
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#define WTOLS3 0 |
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#define RFROMLS3 1 |
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// reserved |
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//#define NULL 0 |
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#define TLB 0 |
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#define CACHE 1 |
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|
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#define RESERVE_OFFSET 0x4 |
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#define TYPE_MASK 0x3 |
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#define MEM_MASK 0x4 |
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#define DIR_MASK 0x8 |
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#define MEM_OFFSET 0x2 |
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#define DIR_OFFSET 0x3 |
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|
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#define IRET 0xf0 |
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|
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// below is operation TYPE |
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/* sd means to store a data to some address fixed which are loaded from X86 host */ |
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#define SD (DWORD | MEM << MEM_OFFSET | WTOLS3 << DIR_OFFSET) |
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/* ld means to load a data to x86 host from some address which are loaded from X86 host */ |
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#define LD (DWORD | MEM << MEM_OFFSET | RFROMLS3 << DIR_OFFSET) |
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/* sd means to store a data to some address fixed which are loaded from X86 host */ |
|||
#define SW (WORD | MEM << MEM_OFFSET | WTOLS3 << DIR_OFFSET) |
|||
/* lw means to load a data to x86 host from some address which are loaded from X86 host */ |
|||
#define LW (WORD | MEM << MEM_OFFSET | RFROMLS3 << DIR_OFFSET) |
|||
/* sw means to store a data to some address fixed which are loaded from X86 host */ |
|||
#define SH (HALF | MEM << MEM_OFFSET | WTOLS3 << DIR_OFFSET) |
|||
/* lh means to load a data to x86 host from some address which are loaded from X86 host */ |
|||
#define LH (HALF | MEM << MEM_OFFSET | RFROMLS3 << DIR_OFFSET) |
|||
/* sh means to store a data to some address fixed which are loaded from X86 host */ |
|||
#define SB (BYTE | MEM << MEM_OFFSET | WTOLS3 << DIR_OFFSET) |
|||
/* lb means to load a data to x86 host from some address which are loaded from X86 host */ |
|||
#define LB (BYTE | MEM << MEM_OFFSET | RFROMLS3 << DIR_OFFSET) |
|||
/* sb means to store a data to some address fixed which are loaded from X86 host */ |
|||
|
|||
#define LDDW SD |
|||
#define LDW SW |
|||
#define LDH SH |
|||
#define LDB SB |
|||
#define STDW LD |
|||
#define STW LW |
|||
#define STH LH |
|||
#define STB LB |
|||
|
|||
/********************************************/ |
|||
|
|||
#define DUMPREGS 0x0f |
|||
#define ERET 0xf0 |
|||
|
|||
#define DEBUG //it seems has bug here, because cpu stop if not in DEBUG |
|||
|
|||
.set mips64 |
|||
// save context |
|||
dmtc0 t0, CP0_DESAVE |
|||
li t0, CONTEXTREG |
|||
sd t1, 0x08(t0) |
|||
dmfc0 t1, CP0_DESAVE |
|||
sd t1, 0x00(t0) // save t0 |
|||
li t0, CONTEXTREG |
|||
sd t2, 0x10(t0) |
|||
sd t3, 0x18(t0) |
|||
sd t4, 0x20(t0) |
|||
sd t5, 0x28(t0) |
|||
sd t6, 0x30(t0) |
|||
sd t7, 0x38(t0) |
|||
sd t8, 0x40(t0) |
|||
sd t9, 0x48(t0) |
|||
dmfc0 t1, CP0_STATUS |
|||
li t0, EJTAG_STATUS |
|||
sd t1, 0x00(t0) |
|||
li t0, EJTAG_CONFIG |
|||
dmfc0 t1, CP0_CONFIG |
|||
sd t1, 0x00(t0) |
|||
li t0, EJTAG_CAUSE |
|||
dmfc0 t1, CP0_CAUSE |
|||
sd t1, 0x00(t0) |
|||
|
|||
li t0, TLBENREG |
|||
ld t1, 0x0(t0) |
|||
beqz t1, tlbdump_end |
|||
nop |
|||
tlbdump_end: |
|||
|
|||
/* t6 used as cmd counter */ |
|||
li t6,0x0 |
|||
|
|||
/* t7: get cmds total number to execute */ |
|||
li t0, STATUSREG |
|||
ld t7, 0x0(t0) |
|||
#ifdef DEBUG |
|||
li t0, DBGREG |
|||
sd t7, 0x0(t0) |
|||
#endif |
|||
beqz t7, 12f |
|||
nop |
|||
|
|||
11: |
|||
/* get cmds type */ |
|||
li t0, TYPEREG |
|||
ld t1, 0x0(t0) |
|||
#ifdef DEBUG |
|||
li t0, DBGREG |
|||
sd t1, 0x0(t0) |
|||
#endif |
|||
|
|||
/* check whether current cmds is "eret" */ |
|||
bne t1,ERET, 15f |
|||
nop |
|||
li t0, EPCREG |
|||
//lw t2, 0x0(t0) |
|||
ld t2, 0x0(t0) |
|||
//dmtc0 t2,CP0_DEXC_PC |
|||
dmtc0 t2, CP0_DEPC |
|||
|
|||
/* should avoid this because C client doesn't support */ |
|||
##ifdef DEBUG |
|||
# li t0, DBGREG |
|||
# sw t2, 0x0(t0) |
|||
##endif |
|||
#li t2,BIOS_ENTRY |
|||
// to check whether this cmds and below nop lead PC dead !!! |
|||
|
|||
#if 1 |
|||
#.set at |
|||
#.set push |
|||
#.set mips3 |
|||
#eret |
|||
#.set pop |
|||
#.set noreorder |
|||
#.set volatile |
|||
nop |
|||
// now not used jump |
|||
li t0, CONTEXTREG |
|||
ld t1, 0x08(t0) |
|||
ld t2, 0x10(t0) |
|||
ld t3, 0x18(t0) |
|||
ld t4, 0x20(t0) |
|||
ld t5, 0x28(t0) |
|||
ld t6, 0x30(t0) |
|||
ld t7, 0x38(t0) |
|||
ld t8, 0x40(t0) |
|||
ld t9, 0x48(t0) |
|||
#mtc0 t8, CP0_STATUS_REG |
|||
#ld t8, 0x48(t0) |
|||
#mtc0 t8, CP0_CONFIG |
|||
#ld t8, 0x50(t0) |
|||
#mtc0 t8, CP0_CAUSE_REG |
|||
dmfc0 t0, CP0_DESAVE |
|||
|
|||
#mtc0 t2,CP0_EXC_PC |
|||
.set mips64 |
|||
deret |
|||
.set mips3 |
|||
nop |
|||
nop |
|||
#endif |
|||
|
|||
#b 12f |
|||
#nop |
|||
|
|||
15: |
|||
/* first check whether local instruction is to dump registers */ |
|||
bne t1, DUMPREGS, 16f |
|||
nop |
|||
li t0, EJTAG_V0 |
|||
sd v0, 0x0(t0) |
|||
li t0, EJTAG_V1 |
|||
sd v1, 0x0(t0) |
|||
li t0, EJTAG_A0 |
|||
sd a0, 0x0(t0) |
|||
li t0, EJTAG_A1 |
|||
sd a1, 0x0(t0) |
|||
li t0, EJTAG_A2 |
|||
sd a2, 0x0(t0) |
|||
li t0, EJTAG_A3 |
|||
sd a3, 0x0(t0) |
|||
li t0, EJTAG_S0 |
|||
sd s0, 0x0(t0) |
|||
li t0, EJTAG_S1 |
|||
sd s1, 0x0(t0) |
|||
li t0, EJTAG_S2 |
|||
sd s2, 0x0(t0) |
|||
li t0, EJTAG_S3 |
|||
sd s3, 0x0(t0) |
|||
li t0, EJTAG_S4 |
|||
sd s4, 0x0(t0) |
|||
li t0, EJTAG_S5 |
|||
sd s5, 0x0(t0) |
|||
li t0, EJTAG_S6 |
|||
sd s6, 0x0(t0) |
|||
li t0, EJTAG_S7 |
|||
sd s7, 0x0(t0) |
|||
li t0, EJTAG_K0 |
|||
sd k0, 0x0(t0) |
|||
li t0, EJTAG_K1 |
|||
sd k1, 0x0(t0) |
|||
li t0, EJTAG_GP |
|||
sd gp, 0x0(t0) |
|||
li t0, EJTAG_SP |
|||
sd sp, 0x0(t0) |
|||
li t0, EJTAG_FP |
|||
sd s8, 0x0(t0) |
|||
li t0, EJTAG_RA |
|||
sd ra, 0x0(t0) |
|||
|
|||
li t0, EJTAG_INDEX |
|||
dmfc0 t1, CP0_INDEX |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_RANDOM |
|||
dmfc0 t1, CP0_RANDOM |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_RANDOM |
|||
dmfc0 t1, CP0_ENTRYLO0 |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_ENTRYLO1 |
|||
dmfc0 t1, CP0_ENTRYLO1 |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_CONTEXT |
|||
dmfc0 t1, CP0_CONTEXT |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_PAGEMASK |
|||
dmfc0 t1, CP0_PAGEMASK |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_WIRED |
|||
dmfc0 t1, CP0_WIRED |
|||
sd t1, 0x0(t0) |
|||
.set mips64 |
|||
li t0, EJTAG_HWRENA |
|||
mfc0 t1, CP0_HWRENA,0 |
|||
.set mips3 |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_BADVADDR |
|||
dmfc0 t1, CP0_BADVADDR |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_COUNT |
|||
dmfc0 t1, CP0_COUNT |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_ENTRYHI |
|||
dmfc0 t1, CP0_ENTRYHI |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_COMPARE |
|||
dmfc0 t1, CP0_COMPARE |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_STATUS |
|||
dmfc0 t1, CP0_STATUS |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_CAUSE |
|||
dmfc0 t1, CP0_CAUSE |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_EPC |
|||
dmfc0 t1, CP0_EPC |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_PRID |
|||
dmfc0 t1, CP0_PRID |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_CONFIG |
|||
dmfc0 t1, CP0_CONFIG |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_LLADDR |
|||
dmfc0 t1, CP0_LLADDR |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_WATCHLO |
|||
dmfc0 t1, CP0_WATCHLO |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_WATCHHI |
|||
dmfc0 t1, CP0_WATCHHI |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_XCONTEXT |
|||
dmfc0 t1, CP0_XCONTEXT |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_DEPC |
|||
dmfc0 t1, CP0_DEPC |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_ERROREPC |
|||
dmfc0 t1, CP0_ERROREPC |
|||
sd t1, 0x0(t0) |
|||
/* get t0 from CP0_DESAVE and save it */ |
|||
li t0, EJTAG_DESAVE |
|||
dmfc0 t1, CP0_DESAVE |
|||
sd t1, 0x0(t0) |
|||
|
|||
/* below dump TLB Registers */ |
|||
//#include "lookuptlb_ejtag.S" |
|||
#include "lookuptlb.S" |
|||
|
|||
|
|||
b 18f |
|||
nop |
|||
|
|||
16: |
|||
|
|||
/* do sd/sw/ld/lw according value in TYPEREG */ |
|||
andi t3, t1,0xf; |
|||
|
|||
/* get accessing mem length */ |
|||
li t0, LENGREG |
|||
ld t2, 0x0(t0) |
|||
#ifdef DEBUG |
|||
li t0, DBGREG |
|||
sd t2, 0x0(t0) |
|||
#endif |
|||
#beqz t2,11f |
|||
beqz t2,11b |
|||
nop |
|||
14: |
|||
/* t4: get address for a store or load instruction */ |
|||
li t0, ADDRREG |
|||
ld t4, 0x0(t0) |
|||
#ifdef DEBUG |
|||
li t0, DBGREG |
|||
sd t4, 0x0(t0) |
|||
#endif |
|||
|
|||
/* if ld/lw instruction, no need ld DATAREG */ |
|||
bge t3,0x8, 110f |
|||
nop |
|||
|
|||
/* t5: get data for a store or load insturction */ |
|||
li t0, DATAREG |
|||
ld t5, 0x0(t0) //WARING HERRE!!!! first ld, but later lw maybe |
|||
//#ifdef DEBUG |
|||
#if 1 |
|||
li t0, DBGREG |
|||
sd t5, 0x0(t0) |
|||
#endif |
|||
|
|||
110: |
|||
beq t3, LDDW, 1110f |
|||
nop |
|||
beq t3, LDW, 1111f |
|||
nop |
|||
beq t3, LDH, 1114f |
|||
nop |
|||
beq t3, LDB, 1116f |
|||
nop |
|||
|
|||
beq t3, STDW, 1112f |
|||
nop |
|||
beq t3, STW, 1113f |
|||
nop |
|||
beq t3, STH, 1115f |
|||
nop |
|||
beq t3, STB, 1117f |
|||
nop |
|||
|
|||
|
|||
1110: |
|||
sd t5, 0x0(t4) |
|||
b 113f |
|||
nop |
|||
1111: |
|||
/* why using delay slot like below fail ? */ |
|||
sw t5, 0x0(t4) |
|||
b 113f |
|||
nop |
|||
1114: |
|||
/* why using delay slot like below fail ? */ |
|||
sh t5, 0x0(t4) |
|||
b 113f |
|||
nop |
|||
1116: |
|||
/* why using delay slot like below fail ? */ |
|||
sb t5, 0x0(t4) |
|||
b 113f |
|||
nop |
|||
|
|||
1112: |
|||
ld t5, 0x0(t4) |
|||
##ifdef DEBUG |
|||
# li t0, DBGREG |
|||
# sd t5, 0x0(t0) |
|||
##endif |
|||
li t0, DATAREG |
|||
sd t5, 0x0(t0) |
|||
b 113f |
|||
nop |
|||
1113: |
|||
lw t5, 0x0(t4) |
|||
li t0, DATAREG |
|||
sw t5, 0x0(t0) |
|||
b 113f |
|||
nop |
|||
1115: |
|||
lh t5, 0x0(t4) |
|||
li t0, DATAREG |
|||
sh t5, 0x0(t0) |
|||
b 113f |
|||
nop |
|||
1117: |
|||
lb t5, 0x0(t4) |
|||
li t0, DATAREG |
|||
sb t5, 0x0(t0) |
|||
b 113f |
|||
nop |
|||
|
|||
113: |
|||
subu t2, t2, 0x1 |
|||
bne t2, $0, 14b |
|||
nop |
|||
|
|||
18: |
|||
/* added for cmd executed counter */ |
|||
addu t6, t6,0x1; |
|||
li t0, CMDCNTREG |
|||
sd t6, 0x0(t0) |
|||
/* to check whether all cmds is done */ |
|||
bne t6, t7, 11b |
|||
nop |
|||
|
|||
// restore context |
|||
12: |
|||
li t0, CONTEXTREG |
|||
ld t1, 0x08(t0) |
|||
ld t2, 0x10(t0) |
|||
ld t3, 0x18(t0) |
|||
ld t4, 0x20(t0) |
|||
ld t5, 0x28(t0) |
|||
ld t6, 0x30(t0) |
|||
ld t7, 0x38(t0) |
|||
ld t8, 0x40(t0) |
|||
ld t9, 0x48(t0) |
|||
#mtc0 t8, CP0_STATUS_REG |
|||
#ld t8, 0x48(t0) |
|||
#mtc0 t8, CP0_CONFIG |
|||
#ld t8, 0x50(t0) |
|||
#mtc0 t8, CP0_CAUSE_REG |
|||
|
|||
dmfc0 t0, CP0_DESAVE |
|||
|
|||
.set mips64 |
|||
deret |
|||
.set mips3 |
|||
//////////////////////////////////////////// |
|||
@ -0,0 +1,129 @@ |
|||
/*
|
|||
* 0 single |
|||
* 1 smb block |
|||
*/ |
|||
int tgt_i2cread(int type,unsigned char *addr,int addrlen,unsigned char reg,unsigned char *buf,int count) |
|||
{ |
|||
int i; |
|||
int device,offset; |
|||
char c; |
|||
device=addr[0]; |
|||
offset=reg; |
|||
device |= 1; |
|||
memset(buf,-1,count); |
|||
switch(type&0xff) |
|||
{ |
|||
case I2C_SINGLE: |
|||
for(i=0;i<count;i++) |
|||
{ |
|||
linux_outb(device,SMBUS_HOST_ADDRESS); |
|||
linux_outb(offset+i,SMBUS_HOST_COMMAND); |
|||
linux_outb(0x8,SMBUS_HOST_CONTROL); |
|||
if((c=linux_inb(SMBUS_HOST_STATUS))&0x1f) |
|||
{ |
|||
linux_outb(c,SMBUS_HOST_STATUS); |
|||
} |
|||
|
|||
linux_outb(linux_inb(SMBUS_HOST_CONTROL)|0x40,SMBUS_HOST_CONTROL); |
|||
|
|||
while(linux_inb(SMBUS_HOST_STATUS)&SMBUS_HOST_STATUS_BUSY); |
|||
|
|||
if((c=linux_inb(SMBUS_HOST_STATUS))&0x1f) |
|||
{ |
|||
linux_outb(c,SMBUS_HOST_STATUS); |
|||
} |
|||
|
|||
buf[i]=linux_inb(SMBUS_HOST_DATA0); |
|||
} |
|||
break; |
|||
case I2C_SMB_BLOCK: |
|||
linux_outb(device,SMBUS_HOST_ADDRESS); //0xd3
|
|||
linux_outb(offset,SMBUS_HOST_COMMAND); |
|||
linux_outb(count,SMBUS_HOST_DATA0); |
|||
linux_outb(0x14,SMBUS_HOST_CONTROL); //0x14
|
|||
if((c=linux_inb(SMBUS_HOST_STATUS))&0x1f) |
|||
{ |
|||
linux_outb(c,SMBUS_HOST_STATUS); |
|||
} |
|||
|
|||
linux_outb(linux_inb(SMBUS_HOST_CONTROL)|0x40,SMBUS_HOST_CONTROL); |
|||
|
|||
while(linux_inb(SMBUS_HOST_STATUS)&SMBUS_HOST_STATUS_BUSY); |
|||
|
|||
if((c=linux_inb(SMBUS_HOST_STATUS))&0x1f) |
|||
{ |
|||
linux_outb(c,SMBUS_HOST_STATUS); |
|||
} |
|||
|
|||
for(i=0;i<count;i++) |
|||
{ |
|||
buf[i]=linux_inb(SMBUS_HOST_DATA1+1); |
|||
} |
|||
break; |
|||
|
|||
default: return 0;break; |
|||
} |
|||
return count; |
|||
} |
|||
|
|||
int tgt_i2cwrite(int type,unsigned char *addr,int addrlen,unsigned char reg,unsigned char *buf,int count) |
|||
{ |
|||
int i; |
|||
int device,offset; |
|||
char c; |
|||
device=addr[0]; |
|||
offset=reg; |
|||
device &= ~1; |
|||
switch(type) |
|||
{ |
|||
case I2C_SINGLE: |
|||
for(i=0;i<count;i++) |
|||
{ |
|||
linux_outb(device,SMBUS_HOST_ADDRESS); |
|||
linux_outb(offset+i,SMBUS_HOST_COMMAND); |
|||
linux_outb(0x8,SMBUS_HOST_CONTROL); |
|||
if((c=linux_inb(SMBUS_HOST_STATUS))&0x1f) |
|||
{ |
|||
linux_outb(c,SMBUS_HOST_STATUS); |
|||
} |
|||
|
|||
linux_outb(buf[i],SMBUS_HOST_DATA0); |
|||
|
|||
linux_outb(linux_inb(SMBUS_HOST_CONTROL)|0x40,SMBUS_HOST_CONTROL); |
|||
|
|||
while(linux_inb(SMBUS_HOST_STATUS)&SMBUS_HOST_STATUS_BUSY); |
|||
|
|||
if((c=linux_inb(SMBUS_HOST_STATUS))&0x1f) |
|||
{ |
|||
linux_outb(c,SMBUS_HOST_STATUS); |
|||
} |
|||
|
|||
} |
|||
break; |
|||
case I2C_SMB_BLOCK: |
|||
linux_outb(device,SMBUS_HOST_ADDRESS); //0xd3
|
|||
linux_outb(offset,SMBUS_HOST_COMMAND); |
|||
linux_outb(count,SMBUS_HOST_DATA0); |
|||
linux_outb(0x14,SMBUS_HOST_CONTROL); //0x14
|
|||
if((c=linux_inb(SMBUS_HOST_STATUS))&0x1f) |
|||
{ |
|||
linux_outb(c,SMBUS_HOST_STATUS); |
|||
} |
|||
|
|||
for(i=0;i<count;i++) |
|||
linux_outb(buf[i],SMBUS_HOST_DATA1+1); |
|||
c=linux_inb(SMBUS_HOST_CONTROL); |
|||
linux_outb(c|0x40,SMBUS_HOST_CONTROL); |
|||
|
|||
while(linux_inb(SMBUS_HOST_STATUS)&SMBUS_HOST_STATUS_BUSY); |
|||
|
|||
if((c=linux_inb(SMBUS_HOST_STATUS))&0x1f) |
|||
{ |
|||
linux_outb(c,SMBUS_HOST_STATUS); |
|||
} |
|||
break; |
|||
default:return -1;break; |
|||
} |
|||
return count; |
|||
} |
|||
|
|||
@ -0,0 +1,139 @@ |
|||
/*
|
|||
* 0 single |
|||
* 1 smb block |
|||
*/ |
|||
int tgt_i2cread(int type, unsigned char *addr, int addrlen,unsigned char reg, |
|||
unsigned char *buf, int count) |
|||
{ |
|||
int i; |
|||
int device; |
|||
int offset; |
|||
char c; |
|||
|
|||
device = addr[0]; |
|||
offset = reg; |
|||
device |= 1; |
|||
memset(buf,-1,count); |
|||
|
|||
switch(type&0xff) |
|||
{ |
|||
case I2C_SINGLE: |
|||
for(i=0;i<count;i++) |
|||
{ |
|||
linux_outb(device,SMBUS_HOST_ADDRESS); |
|||
linux_outb(offset+i,SMBUS_HOST_COMMAND); |
|||
linux_outb(0x8,SMBUS_HOST_CONTROL); |
|||
if((c=linux_inb(SMBUS_HOST_STATUS))&0x1f) |
|||
{ |
|||
linux_outb(c,SMBUS_HOST_STATUS); |
|||
} |
|||
|
|||
linux_outb(linux_inb(SMBUS_HOST_CONTROL)|0x40,SMBUS_HOST_CONTROL); |
|||
|
|||
while(linux_inb(SMBUS_HOST_STATUS)&SMBUS_HOST_STATUS_BUSY); |
|||
|
|||
if((c=linux_inb(SMBUS_HOST_STATUS))&0x1f) |
|||
{ |
|||
linux_outb(c,SMBUS_HOST_STATUS); |
|||
} |
|||
|
|||
buf[i]=linux_inb(SMBUS_HOST_DATA0); |
|||
} |
|||
break; |
|||
case I2C_SMB_BLOCK: |
|||
linux_outb(device,SMBUS_HOST_ADDRESS); //0xd3
|
|||
linux_outb(offset,SMBUS_HOST_COMMAND); |
|||
linux_outb(count,SMBUS_HOST_DATA0); |
|||
linux_outb(0x14,SMBUS_HOST_CONTROL); //0x14
|
|||
if((c=linux_inb(SMBUS_HOST_STATUS))&0x1f) |
|||
{ |
|||
linux_outb(c,SMBUS_HOST_STATUS); |
|||
} |
|||
|
|||
linux_outb(linux_inb(SMBUS_HOST_CONTROL)|0x40,SMBUS_HOST_CONTROL); |
|||
|
|||
while(linux_inb(SMBUS_HOST_STATUS)&SMBUS_HOST_STATUS_BUSY); |
|||
|
|||
if((c=linux_inb(SMBUS_HOST_STATUS))&0x1f) |
|||
{ |
|||
linux_outb(c,SMBUS_HOST_STATUS); |
|||
} |
|||
|
|||
for(i=0;i<count;i++) |
|||
{ |
|||
buf[i]=linux_inb(SMBUS_HOST_DATA1+1); |
|||
} |
|||
break; |
|||
|
|||
default: |
|||
return 0; |
|||
} |
|||
return count; |
|||
} |
|||
|
|||
int tgt_i2cwrite(int type,unsigned char *addr,int addrlen,unsigned char reg, |
|||
unsigned char *buf,int count) |
|||
{ |
|||
int i; |
|||
int device; |
|||
int offset; |
|||
char c; |
|||
|
|||
device = addr[0]; |
|||
offset = reg; |
|||
device &= ~1; |
|||
|
|||
switch(type) |
|||
{ |
|||
case I2C_SINGLE: |
|||
for(i = 0; i < count; i++) |
|||
{ |
|||
linux_outb(device,SMBUS_HOST_ADDRESS); |
|||
linux_outb(offset+i,SMBUS_HOST_COMMAND); |
|||
linux_outb(0x8,SMBUS_HOST_CONTROL); |
|||
if((c=linux_inb(SMBUS_HOST_STATUS))&0x1f) |
|||
{ |
|||
linux_outb(c,SMBUS_HOST_STATUS); |
|||
} |
|||
|
|||
linux_outb(buf[i],SMBUS_HOST_DATA0); |
|||
|
|||
linux_outb(linux_inb(SMBUS_HOST_CONTROL)|0x40,SMBUS_HOST_CONTROL); |
|||
|
|||
while(linux_inb(SMBUS_HOST_STATUS)&SMBUS_HOST_STATUS_BUSY); |
|||
|
|||
if((c=linux_inb(SMBUS_HOST_STATUS))&0x1f) |
|||
{ |
|||
linux_outb(c,SMBUS_HOST_STATUS); |
|||
} |
|||
|
|||
} |
|||
break; |
|||
case I2C_SMB_BLOCK: |
|||
linux_outb(device,SMBUS_HOST_ADDRESS); //0xd3
|
|||
linux_outb(offset,SMBUS_HOST_COMMAND); |
|||
linux_outb(count,SMBUS_HOST_DATA0); |
|||
linux_outb(0x14,SMBUS_HOST_CONTROL); //0x14
|
|||
if((c=linux_inb(SMBUS_HOST_STATUS)) & 0x1f) |
|||
{ |
|||
linux_outb(c,SMBUS_HOST_STATUS); |
|||
} |
|||
|
|||
for(i = 0 ; i < count; i++) |
|||
linux_outb(buf[i],SMBUS_HOST_DATA1+1); |
|||
c = linux_inb(SMBUS_HOST_CONTROL); |
|||
linux_outb(c|0x40,SMBUS_HOST_CONTROL); |
|||
|
|||
while(linux_inb(SMBUS_HOST_STATUS) & SMBUS_HOST_STATUS_BUSY); |
|||
|
|||
if((c=linux_inb(SMBUS_HOST_STATUS)) & 0x1f) |
|||
{ |
|||
linux_outb(c,SMBUS_HOST_STATUS); |
|||
} |
|||
break; |
|||
default: |
|||
return -1; |
|||
} |
|||
return count; |
|||
} |
|||
|
|||
@ -0,0 +1,172 @@ |
|||
/************************* |
|||
* Small modified by cxk. |
|||
*************************/ |
|||
#define BONITO_HTIO_BASE_VA 0x90000efdfc000000 |
|||
|
|||
#ifdef USE_SB_I2C |
|||
#ifndef MULTI_I2C_BUS |
|||
LEAF(i2cread) |
|||
/*************** |
|||
use register: |
|||
v0, v1 |
|||
a0, a1 |
|||
input: a0,a1 |
|||
a0: device ID |
|||
a1: register offset |
|||
***************/ |
|||
ori a0, a0, 1 |
|||
|
|||
/* set device address */ |
|||
dli v0, BONITO_HTIO_BASE_VA + SMBUS_HOST_ADDRESS |
|||
sb a0, 0(v0); |
|||
|
|||
/* store register offset */ |
|||
dli v0, BONITO_HTIO_BASE_VA + SMBUS_HOST_COMMAND |
|||
sb a1, 0(v0); |
|||
|
|||
/* read byte data protocol */ |
|||
dli v0, 0x08 |
|||
dli v1, BONITO_HTIO_BASE_VA + SMBUS_HOST_CONTROL |
|||
sb v0, 0(v1); |
|||
|
|||
/* make sure SMB host ready to start, important!--zfx */ |
|||
dli v1, BONITO_HTIO_BASE_VA + SMBUS_HOST_STATUS |
|||
lbu v0, 0(v1) |
|||
andi v0, v0, 0x1f |
|||
beqz v0, 1f |
|||
nop |
|||
sb v0, 0(v1) |
|||
lbu v0, 0(v1) #flush the write |
|||
1: |
|||
/* start */ |
|||
dli v1, BONITO_HTIO_BASE_VA + SMBUS_HOST_CONTROL |
|||
lbu v0, 0(v1) |
|||
ori v0, v0, 0x40 |
|||
sb v0, 0(v1); |
|||
|
|||
/* wait */ |
|||
dli v1, BONITO_HTIO_BASE_VA + SMBUS_HOST_STATUS |
|||
|
|||
1: |
|||
#if 1 |
|||
/* delay */ |
|||
dli v0, 0x100 |
|||
2: |
|||
bnez v0, 2b |
|||
daddiu v0, -1 |
|||
#endif |
|||
lbu v0, 0(v1) |
|||
andi v0, SMBUS_HOST_STATUS_BUSY |
|||
bnez v0, 1b #IDEL ? |
|||
nop |
|||
|
|||
dli v1, BONITO_HTIO_BASE_VA + SMBUS_HOST_STATUS |
|||
lbu v0, 0(v1) |
|||
andi v0, v0, 0x1f |
|||
beqz v0, 1f |
|||
nop |
|||
sb v0, 0(v1) #reset |
|||
lbu v0, 0(v1) #flush the write |
|||
1: |
|||
|
|||
dli v1, BONITO_HTIO_BASE_VA + SMBUS_HOST_DATA0 |
|||
lbu v0, 0(v1) |
|||
|
|||
jr ra |
|||
nop |
|||
END(i2cread) |
|||
#else |
|||
/****************************************************/ |
|||
/* support multi i2c bus mode */ |
|||
/****************************************************/ |
|||
LEAF(i2cread) |
|||
/*************** |
|||
use register: |
|||
v0, v1 |
|||
a0, a1, a2 |
|||
input: a0,a1,a2 |
|||
a0: device ID |
|||
a1: register offset |
|||
a2: chip ID (0,1,2,3) |
|||
***************/ |
|||
ori a0, a0, 1 |
|||
/* calculate address according chip ID */ |
|||
dsll a2, a2, 44 |
|||
|
|||
/* set device address */ |
|||
dli v0, BONITO_HTIO_BASE_VA + SMBUS_HOST_ADDRESS |
|||
daddu v0, v0, a2 |
|||
sb a0, 0(v0); |
|||
|
|||
/* store register offset */ |
|||
dli v0, BONITO_HTIO_BASE_VA + SMBUS_HOST_COMMAND |
|||
daddu v0, v0, a2 |
|||
sb a1, 0(v0); |
|||
|
|||
/* read byte data protocol */ |
|||
dli v0, 0x08 |
|||
dli v1, BONITO_HTIO_BASE_VA + SMBUS_HOST_CONTROL |
|||
daddu v1, v1, a2 |
|||
sb v0, 0(v1); |
|||
|
|||
/* make sure SMB host ready to start, important!--zfx */ |
|||
dli v1, BONITO_HTIO_BASE_VA + SMBUS_HOST_STATUS |
|||
daddu v1, v1, a2 |
|||
lbu v0, 0(v1) |
|||
andi v0, v0, 0x1f |
|||
beqz v0, 1f |
|||
nop |
|||
sb v0, 0(v1) |
|||
lbu v0, 0(v1) #flush the write |
|||
1: |
|||
/* start */ |
|||
dli v1, BONITO_HTIO_BASE_VA + SMBUS_HOST_CONTROL |
|||
daddu v1, v1, a2 |
|||
lbu v0, 0(v1) |
|||
ori v0, v0, 0x40 |
|||
sb v0, 0(v1); |
|||
|
|||
/* wait */ |
|||
dli v1, BONITO_HTIO_BASE_VA + SMBUS_HOST_STATUS |
|||
daddu v1, v1, a2 |
|||
|
|||
1: |
|||
#if 1 |
|||
/* delay */ |
|||
dli v0, 0x100 |
|||
2: |
|||
bnez v0, 2b |
|||
daddiu v0, -1 |
|||
#endif |
|||
lbu v0, 0(v1) |
|||
andi v0, SMBUS_HOST_STATUS_BUSY |
|||
bnez v0, 1b #IDEL ? |
|||
nop |
|||
|
|||
dli v1, BONITO_HTIO_BASE_VA + SMBUS_HOST_STATUS |
|||
daddu v1, v1, a2 |
|||
lbu v0, 0(v1) |
|||
andi v0, v0, 0x1f |
|||
beqz v0, 1f |
|||
nop |
|||
sb v0, 0(v1) #reset |
|||
lbu v0, 0(v1) #flush the write |
|||
1: |
|||
|
|||
dli v1, BONITO_HTIO_BASE_VA + SMBUS_HOST_DATA0 |
|||
daddu v1, v1, a2 |
|||
lbu v0, 0(v1) |
|||
|
|||
jr ra |
|||
nop |
|||
END(i2cread) |
|||
#endif |
|||
|
|||
#else |
|||
|
|||
#ifdef USE_GPIO_I2C |
|||
#include "i2c_firewall.S" |
|||
#endif |
|||
|
|||
#endif |
|||
|
|||
@ -0,0 +1,407 @@ |
|||
li k0,0 |
|||
li k1,0 |
|||
li msize,0 |
|||
PRINTSTR("DIMM read\r\n") |
|||
|
|||
li a1, 0x0 |
|||
li a0,0xa0 |
|||
bal i2cread |
|||
nop |
|||
beq v0,0xff,1f |
|||
nop |
|||
beq v0,0x80,1f |
|||
nop |
|||
move a0,v0 |
|||
// bal hexserial |
|||
nop |
|||
PRINTSTR ("\r\nNo DIMM in slot 0 \r\n"); |
|||
b 2f |
|||
nop |
|||
1: |
|||
li a0,0xa0 |
|||
bal ii2c_cfg |
|||
nop |
|||
2: |
|||
li a1, 0x0 |
|||
li a0,0xa2 |
|||
bal i2cread |
|||
nop |
|||
li a1,0x0 |
|||
beq v0,0xff,1f |
|||
nop |
|||
beq v0,0x80,1f |
|||
nop |
|||
move a0,v0 |
|||
// bal hexserial |
|||
nop |
|||
PRINTSTR ("\r\nNo DIMM in slot 1 \r\n"); |
|||
b 2f |
|||
nop |
|||
1: |
|||
li a0,0xa2 |
|||
bal ii2c_cfg |
|||
nop |
|||
|
|||
b 2f |
|||
nop |
|||
|
|||
2: |
|||
b 211f |
|||
nop |
|||
/*ic2 cfg |
|||
* a0=0xa0 for slot 0,a0=0xa2 for slot 1 |
|||
* t5 used for save i2c addr a0,t6 save ra. |
|||
* use t1 |
|||
*/ |
|||
LEAF(ii2c_cfg) |
|||
move t6,ra |
|||
move t5,a0 |
|||
|
|||
#ifdef I2C_DEBUG |
|||
li t1,0 |
|||
1: |
|||
move a1,t1 |
|||
move a0,t5 |
|||
bal i2cread |
|||
nop |
|||
|
|||
#print |
|||
move a0, v0 |
|||
bal hexserial |
|||
nop |
|||
PRINTSTR("\r\n") |
|||
addiu t1,t1,1 |
|||
li v0, 0x20 |
|||
bleu t1, v0, 1b |
|||
nop |
|||
#endif |
|||
|
|||
# set some parameters for DDR333 |
|||
# rank number and DDR type field will be filled later |
|||
# to check: fix TCAS? |
|||
|
|||
|
|||
PRINTSTR("read memory type\r\n") |
|||
|
|||
/* read DIMM number of rows */ |
|||
move a0,t5 /* #zgj-11-17 */ |
|||
li a1,3 |
|||
bal i2cread |
|||
nop |
|||
move s6,v0 |
|||
move a0, v0 |
|||
subu v0, 12 |
|||
bgtu v0, 2,.nodimm1 |
|||
nop |
|||
move t1, v0 |
|||
PRINTSTR("read number of rows :"); |
|||
move a0,s6 |
|||
bal hexserial |
|||
nop |
|||
|
|||
2: /* read DIMM number of cols */ |
|||
|
|||
move a0,t5 /* #zgj-11-17 */ |
|||
li a1,4 |
|||
bal i2cread |
|||
nop |
|||
////////////////////// |
|||
move a0,v0 |
|||
dsll a0,a0,32 |
|||
daddu s6,a0 |
|||
///////////////////// |
|||
subu v0, 8 |
|||
bgtu v0, 4,.nodimm1 |
|||
nop |
|||
|
|||
bne t1, 0, 10f |
|||
nop |
|||
bne v0, 2, 20f |
|||
nop |
|||
li v0, 0 |
|||
b .ddrtype1 |
|||
nop |
|||
|
|||
20: bne v0, 1, 21f |
|||
nop |
|||
li v0, 1 |
|||
b .ddrtype1 |
|||
nop |
|||
21: bne v0, 0, 22f |
|||
nop |
|||
|
|||
li v0, 2 |
|||
b .ddrtype1 |
|||
nop |
|||
22: bne v0, 3, 33f |
|||
nop |
|||
li v0, 3 |
|||
b .ddrtype1 |
|||
nop |
|||
10: bne t1, 1, 11f |
|||
nop |
|||
bne v0, 3, 20f |
|||
nop |
|||
li v0, 4 |
|||
b .ddrtype1 |
|||
nop |
|||
20: bne v0, 2, 21f |
|||
nop |
|||
li v0, 5 |
|||
b .ddrtype1 |
|||
nop |
|||
21: bne v0, 1, 22f |
|||
nop |
|||
li v0, 6 |
|||
b .ddrtype1 |
|||
nop |
|||
22: bne v0, 4, 33f |
|||
nop |
|||
li v0, 7 |
|||
b .ddrtype1 |
|||
nop |
|||
11: bne t1, 2, 33f |
|||
nop |
|||
bne v0, 4, 20f |
|||
nop |
|||
li v0, 8 |
|||
b .ddrtype1 |
|||
nop |
|||
20: bne v0, 3, 21f |
|||
nop |
|||
li v0, 9 |
|||
b .ddrtype1 |
|||
nop |
|||
21: bne v0, 2, 33f |
|||
nop |
|||
li v0, 10 |
|||
b .ddrtype1 |
|||
nop |
|||
33: PRINTSTR("DDR type not supported!\r\n"); |
|||
34: b 34b |
|||
nop |
|||
|
|||
.ddrtype1: |
|||
|
|||
move a0,t5 |
|||
li a1,17 |
|||
bal i2cread |
|||
nop |
|||
beq v0,4,2f |
|||
nop |
|||
bne v0,8,.nodimm1 |
|||
li k0,1 |
|||
nop |
|||
2: |
|||
|
|||
PRINTSTR("\r\nnumber of ranks ,package and height\r\n") ; |
|||
PRINTSTR("k1 to save cs_map filed valule\r\n") ; |
|||
move a0,t5 |
|||
li a1,5 |
|||
bal i2cread |
|||
nop |
|||
//*********** |
|||
andi v0,v0,0x7 |
|||
//*********** |
|||
beq v0,0,2f |
|||
nop |
|||
bne v0,1,.nodimm1 |
|||
nop |
|||
|
|||
//************ |
|||
bne t5,0xa0,123f |
|||
nop |
|||
ori k1,k1,0x3 |
|||
b 124f |
|||
nop |
|||
|
|||
123: ori k1,k1,0xc |
|||
|
|||
124: b 124f |
|||
nop |
|||
|
|||
|
|||
|
|||
2: bne t5,0xa0,123f |
|||
nop |
|||
ori k1,k1,0x1 |
|||
b 124f |
|||
nop |
|||
|
|||
123: ori k1,k1,0x4 |
|||
124: nop |
|||
|
|||
//************ |
|||
|
|||
|
|||
|
|||
/* read DIMM width */ |
|||
move a0,t5 |
|||
li a1,6 |
|||
|
|||
bal i2cread |
|||
nop |
|||
bleu v0,36,2f |
|||
nop |
|||
bgtu v0,72,.nodimm1 |
|||
nop |
|||
PRINTSTR("read width\r\n") ; |
|||
2: |
|||
PRINTSTR("module rank density\r\n") ; |
|||
move a0,t5 |
|||
li a1,31 |
|||
bal i2cread |
|||
nop |
|||
beqz v0,.nodimm1 |
|||
nop |
|||
//////////////////// |
|||
beq v0,0x80,1f |
|||
nop |
|||
beq v0,0x40,2f |
|||
nop |
|||
beq v0,0x20,3f |
|||
nop |
|||
beq v0,0x10,4f |
|||
nop |
|||
beq v0,0x08,5f |
|||
nop |
|||
beq v0,0x04,6f |
|||
nop |
|||
beq v0,0x02,7f |
|||
nop |
|||
li tmpsize,1<<10 |
|||
b 100f |
|||
nop |
|||
|
|||
7: li tmpsize,2<<10 |
|||
b 100f |
|||
nop |
|||
6: li tmpsize,4<<10 |
|||
b 100f |
|||
nop |
|||
5: li tmpsize,8<<10 |
|||
b 100f |
|||
nop |
|||
4: li tmpsize,16<<10 |
|||
b 100f |
|||
nop |
|||
3: li tmpsize,128 |
|||
b 100f |
|||
nop |
|||
2: li tmpsize,256 |
|||
b 100f |
|||
nop |
|||
1: li tmpsize,512 |
|||
|
|||
//////////////// |
|||
100: addu msize,tmpsize |
|||
|
|||
|
|||
PRINTSTR("sizing slot memory size\r\n") ; |
|||
move a0,t5 |
|||
li a1,5 |
|||
bal i2cread |
|||
nop |
|||
andi v0,0x7 |
|||
2: beq v0,0,1f |
|||
nop |
|||
addu msize,tmpsize |
|||
subu v0,v0,1 |
|||
|
|||
b 2b |
|||
nop |
|||
|
|||
.nodimm1: |
|||
PRINTSTR ("\r\nNo DIMM in this slot "); |
|||
1: |
|||
jr t6 |
|||
nop |
|||
END(ii2c_cfg) |
|||
|
|||
211: |
|||
beqz msize,212f |
|||
nop |
|||
move a0,k1 |
|||
|
|||
li v0,0xaffffe70 |
|||
lw v1,0(v0) |
|||
nop |
|||
sll a0,a0,16 |
|||
li t0,0xfff0ffff |
|||
and v1,v1,t0 |
|||
or v1,v1,a0 |
|||
sw v1,0(v0) |
|||
nop |
|||
|
|||
|
|||
PRINTSTR ("cs map : "); |
|||
move a0,k1 |
|||
bal hexserial |
|||
nop |
|||
|
|||
|
|||
PRINTSTR("\r\nconfig bank if bank 8: ") |
|||
li v0,0xaffffe10 |
|||
ld v1,0(v0) |
|||
nop |
|||
move a0,v1 |
|||
dsrl a0,a0,32 |
|||
or a0,a0,k0 |
|||
dsll a0,a0,32 |
|||
or v1,a0,v1 |
|||
sd v1,0(v0) |
|||
nop |
|||
move a0,v1 |
|||
dsrl a0,a0,32 |
|||
bal hexserial |
|||
nop |
|||
|
|||
PRINTSTR("\r\ncols rows: ") |
|||
|
|||
//row addr numbers |
|||
li v0,0xffffffff |
|||
and a0,s6,v0 |
|||
li v0,15 |
|||
subu a0,v0,a0 |
|||
|
|||
//col addr numbers |
|||
dsrl s6,s6,20 |
|||
dsrl s6,s6,12 |
|||
li v0,14 |
|||
|
|||
move a1,s6 |
|||
subu a1,v0,a1 |
|||
|
|||
sll a1,a1,24 |
|||
sll a0,a0,8 |
|||
|
|||
li v0,0xaffffe50 |
|||
lw v1,0(v0) |
|||
nop |
|||
li t0,0xf8fff8ff |
|||
and v1,v1,t0 |
|||
or v1,v1,a0 |
|||
or v1,v1,a1 |
|||
sw v1,0(v0) |
|||
nop |
|||
move a0,v1 |
|||
bal hexserial |
|||
nop |
|||
|
|||
PRINTSTR("\r\n") |
|||
b 213f |
|||
nop |
|||
212: |
|||
.nodimm: |
|||
li msize,0x100 |
|||
PRINTSTR ("\r\nNo DIMM in all slots,use default configure\r\n") |
|||
213: |
|||
|
|||
PRINTSTR ("\r\nDIMM size :") |
|||
move a0,msize |
|||
bal hexserial |
|||
nop |
|||
|
|||
PRINTSTR ("\r\n") |
|||
|
|||
sll msize,20 |
|||
@ -0,0 +1,72 @@ |
|||
#define EJTAG_TLB_INDEX EJTAG_INDEX |
|||
#define EJTAG_TLB_HIGH EJTAG_ENTRYHI |
|||
#define EJTAG_TLB_LO0 EJTAG_ENTRYLO0 |
|||
#define EJTAG_TLB_LO1 EJTAG_ENTRYLO1 |
|||
|
|||
li t0, 0x20000000 |
|||
.set mips64 |
|||
dmfc0 t1, COP_0_TLB_PG_MASK, 1 |
|||
or t1, t1, t0 |
|||
dmtc0 t1, COP_0_TLB_PG_MASK, 1 |
|||
|
|||
dmfc0 t0, COP_0_CONFIG, 3 |
|||
ori t0, t0, 0x80 |
|||
dmtc0 t0, COP_0_CONFIG, 3 |
|||
.set mips3 |
|||
|
|||
li t0, 0xfff000 |
|||
li t0, -1 |
|||
mtc0 t0, COP_0_TLB_PG_MASK # 16MB page |
|||
|
|||
li t0, 63 |
|||
1: |
|||
mtc0 t0, COP_0_TLB_INDEX |
|||
|
|||
#PRINTSTR("index:") |
|||
#move a0, t0 |
|||
# bal hexserial64 |
|||
#nop |
|||
# PRINTSTR("\r\n") |
|||
li t2,EJTAG_TLB_INDEX |
|||
sd t0, 0x0(t2) |
|||
|
|||
tlbr |
|||
nop |
|||
nop |
|||
nop |
|||
nop |
|||
|
|||
.set mips64 |
|||
dmfc0 t1, COP_0_TLB_HI |
|||
#PRINTSTR("tlb hi:") |
|||
#move a0, t3 |
|||
# bal hexserial64 |
|||
#nop |
|||
# PRINTSTR("\r\n") |
|||
li t2,EJTAG_TLB_HIGH |
|||
sd t1, 0x0(t2) |
|||
|
|||
|
|||
dmfc0 t1, COP_0_TLB_LO0 |
|||
#PRINTSTR("tlb lo0:") |
|||
#move a0, t4 |
|||
# bal hexserial64 |
|||
#nop |
|||
# PRINTSTR("\r\n") |
|||
li t2,EJTAG_TLB_LO0 |
|||
sd t1, 0x0(t2) |
|||
|
|||
|
|||
dmfc0 t1, COP_0_TLB_LO1 |
|||
#PRINTSTR("tlb lo1:") |
|||
#move a0, t5 |
|||
# bal hexserial64 |
|||
#nop |
|||
# PRINTSTR("\r\n") |
|||
li t2,EJTAG_TLB_LO1 |
|||
sd t1, 0x0(t2) |
|||
|
|||
.set mips3 |
|||
|
|||
bnez t0, 1b |
|||
addiu t0, -1 |
|||
@ -0,0 +1,890 @@ |
|||
.align 5 |
|||
//DDR2 param |
|||
ddr2_reg_data: |
|||
ddr2_reg_data_mc1: |
|||
|
|||
ddr2_RDIMM_reg_data: |
|||
ddr2_RDIMM_reg_data_mc1: |
|||
|
|||
.align 5 |
|||
//DDR3 param |
|||
ddr3_reg_data: |
|||
#ifdef DDR3_DIMM |
|||
MC0_DDR3_CTL_000 : .dword 0x0000010000000100 |
|||
//000000000000000_0 concurrentap(RW) 0000000_1 bank_split_en(RW) 0000000_0 auto_refresh_mode(RW) 0000000_0 arefresh(WR) 0000000_0 ap(RW) 0000000_1 addr_cmp_en(RW) 0000000_1 active_aging(RW) |
|||
MC0_DDR3_CTL_010 : .dword 0x0000000100010000 |
|||
//0000000_0 fwc(WR) 0000000_0 fast_write(RW) 0000000_1 enable_quick_srefresh(RW) 0000000_1 eight_bank_mode(RW) 0000000_0 ecc_disable_w_uc_err(RW) 0000000_1 dqs_n_en(RW) 0000000_0 dll_bypass_mode(RW) 0000000_0 dlllockreg(RD) |
|||
MC0_DDR3_CTL_020 : .dword 0x0100010000000000 |
|||
//0000000_1 priority_en(RW) 0000000_0 power_down(RW) 0000000_1 placement_en(RW) 0000000_0 odt_add_turn_clk_en(RD) 0000000_0 no_cmd_init(RW) 0000000_0 intrptwritea(RW) 0000000_0 intrptreada(RW) 0000000_0 intrptapburst(RW) |
|||
MC0_DDR3_CTL_030 : .dword 0x0001000001000000 |
|||
//0000000_1 swap_port_rw_same_en(RW) 0000000_1 swap_en(RW) 0000000_0 start(RW) 0000000_0 srefresh(RW+) 0000000_1 rw_same_en(RW) 0000000_0 reg_dimm_enable(RW) 0000000_0 reduc(RW) 0000000_0 pwrup_srefresh_exit(RW) |
|||
MC0_DDR3_CTL_040 : .dword 0x0002010100000101 |
|||
//000000_00 rtt_0(RD) 000000_11 ctrl_raw(RW) 000000_01 axi0_w_priority(RW) 000000_01 axi0_r_priority(RW) 0000000_0 write_modereg(WR) 0000000_1 writeinterp(RW) 0000000_1 tref_enable(RW) 0000000_1 tras_lockout(RW) |
|||
MC0_DDR3_CTL_050 : .dword 0x0700000004060100 |
|||
//00000_000 q_fullness(RW) 00000_000 port_data_error_type(RD) 000_00000 out_of_range_type(RD) 00000_000 max_cs_reg(RD) 00000_100 column_size(RW) 0000_0101 caslat(RW) 00000_010 addr_pins(RW) 00000000 |
|||
MC0_DDR3_CTL_060 : .dword 0x0a05050805050003 |
|||
//0000_1010 aprebit(RW) 0000_0101 wrlat(RW) 0000_0100 twtr(RW) 000_00110 twr_int(RW) 00000_011 trtp(RW) 00000_100 trrd(RW) 0000000000000_011 tcke(RW) |
|||
MC0_DDR3_CTL_070 : .dword 0x0000000000030c0c |
|||
//0000_1111 max_row_reg(RD) 0000_1110 max_col_reg(RD) 0000_0000 initaref(RW) 00000000000000000000_1111 cs_map(RW) 000_01010 caslat_lin_gate(RW) 000_01010 caslat_lin(RW) |
|||
MC0_DDR3_CTL_080 : .dword 0x0804020100000000 |
|||
//0000_0001 odt_wr_map_cs3(RW) 0000_0010 odt_wr_map_cs2(RW) 0000_0100 odt_wr_map_cs1(RW) 0000_1000 odt_wr_map_cs0(RW) 0000_0001 odt_rd_map_cs3(RW) 0000_0010 odt_rd_map_cs2(RW) 0000_0100 odt_rd_map_cs1(RW) 0000_1000 odt_rd_map_cs0(RW) |
|||
MC0_DDR3_CTL_090 : .dword 0x0000070f00000000 |
|||
//000_00000 ocd_adjust_pup_cs_0(RW) 000_00000 ocd_adjust_pdn_cs_0(RW) 0000_0101 trp(RW) 000_01011 tdal(RW) 000000000000_0000 port_cmd_error_type(RD) 0000000000000000 |
|||
MC0_DDR3_CTL_0a0 : .dword 0x0000001f3f140412 |
|||
//00000000000000000000000000_111111 command_age_count(RW) 00_111111 age_count(RW) 000_10100 trc(RW) 000_00110 tmrd(RW) 000_10010 tfaw(RW) |
|||
MC0_DDR3_CTL_0b0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_0c0 : .dword 0x000040060f000000 |
|||
//000000000000000000101100 trfc(RW) 00000101 trcd_int(RW) 00001111 tras_min(RW) 00000000 out_of_range_length(RD) 00000000 ecc_u_synd(RD) 00000000 ecc_c_synd(RD) |
|||
MC0_DDR3_CTL_0d0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_0e0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_0f0 : .dword 0x0000000000000000 |
|||
//Bit 21:16 dll_lock(RD) |
|||
MC0_DDR3_CTL_100 : .dword 0x0000000000000000 |
|||
//MC0_DDR3_CTL_110 : .dword 0x00000000000005e0 #200M+ |
|||
MC0_DDR3_CTL_110 : .dword 0x0000000000000900 #300M+ |
|||
//MC0_DDR3_CTL_110 : .dword 0x0000000000000c00 #400M+ |
|||
//0_000000000000000 emrs2_data_1(RW) 0_000000000000000 emrs2_data_0(RW) 000000000000000000_00110000101101 tref(RW) |
|||
MC0_DDR3_CTL_120 : .dword 0x001c000000000000 |
|||
//0000000000011100 axi0_en_size_lt_width_instr(RW) hXXXX 0_000000000000000 emrs2_data_3(RW) 0_000000000000000 emrs2_data_2(RW) |
|||
//MC0_DDR3_CTL_130 : .dword 0x36800003020000c8 #200M+ |
|||
MC0_DDR3_CTL_130 : .dword 0x52100003020000c8 #300M--400M |
|||
//MC0_DDR3_CTL_130 : .dword 0x6d800004020010b #400M--533M |
|||
//0110110101010110 tras_max(RW) 0000000000000011 tpdex(RW) 0000001000000000 tdll(RW) 0000000000000000 tcpd(RW) |
|||
MC0_DDR3_CTL_140 : .dword 0x0000000002000044 |
|||
//0000000000000000 xor_check_bits(RW) 0000000000000000 version(RD) 0000001000000000 txsr(RW) 0000000000110000 txsnr(RW) |
|||
MC0_DDR3_CTL_150 : .dword 0x0000000000027100 |
|||
//000_0000000000000000000000000000000000000 ecc_c_addr(RD) hXXXXXX tinit(RW) |
|||
MC0_DDR3_CTL_160 : .dword 0x0000000000000000 |
|||
//000000000000000000000000000_0000000000000000000000000000000000000 ecc_u_addr(RD) |
|||
MC0_DDR3_CTL_170 : .dword 0x0000000000000000 |
|||
//000000000000000000000000000_0000000000000000000000000000000000000 out_of_range_addr(RD) |
|||
MC0_DDR3_CTL_180 : .dword 0x0000000000000000 |
|||
//000000000000000000000000000_0000000000000000000000000000000000000 port_cmd_error_addr(RD) |
|||
MC0_DDR3_CTL_190 : .dword 0x0000000000000000 |
|||
//0000000000000000000000000000000000000000000000000000000000000000 ecc_c_data(RD) |
|||
MC0_DDR3_CTL_1a0 : .dword 0x0000000000000000 |
|||
//0000000000000000000000000000000000000000000000000000000000000000 ecc_u_data(RD) |
|||
MC0_DDR3_CTL_1b0 : .dword 0x0000000000000007 |
|||
//0000000000000000000000000000000000000000000000000000000000000_000 cke_delay(RW) |
|||
MC0_DDR3_CTL_1c0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_1d0 : .dword 0x02000b0000000001 |
|||
//0000_0010 tdfi_phy_wrlat_base(RW) 0000_0000 tdfi_phy_wrlat(RD) 000_00111 tdfi_phy_rdlat(RW) 0000_0100 tdfi_ctrlupd_min(RD) 000000000000_0000 dram_clk_disable(RW) 0000000_1 odt_alt_en(RW) 0000000_1 drive_dq_dqs(RW) |
|||
MC0_DDR3_CTL_1e0 : .dword 0x0000000000000200 |
|||
//00_00000000000000 tdfi_phyupd_type0(RD) 00_00000000000000 tdfi_phyupd_resp(RD) 00_00000000000000 tdfi_ctrlupd_max(RD) 000_00000 tdfi_rddata_en_base(RW) 000_00000 tdfi_rddata_en(RD) |
|||
|
|||
//hXXXXXXXX dll_ctrl_reg_0_0(RW) h000000 hXX dft_ctrl_reg(RW) |
|||
MC0_DDR3_CTL_1f0 : .dword 0x0020008000000000 |
|||
MC0_DDR3_CTL_200 : .dword 0x0020008000200080 |
|||
MC0_DDR3_CTL_210 : .dword 0x0020008000200080 |
|||
MC0_DDR3_CTL_220 : .dword 0x0020008000200080 |
|||
MC0_DDR3_CTL_230 : .dword 0x0020008000200080 |
|||
MC0_DDR3_CTL_240 : .dword 0x0000200000002000 |
|||
MC0_DDR3_CTL_250 : .dword 0x0000200000002000 |
|||
MC0_DDR3_CTL_260 : .dword 0x0000200000002000 |
|||
MC0_DDR3_CTL_270 : .dword 0x0000200000002000 |
|||
MC0_DDR3_CTL_280 : .dword 0x0000000000002000 |
|||
//hXXXXXXX 00_00 dll_obs_reg_0_0(RW) 00000000000000000000111000000000 dll_ctrl_reg_1_8(RW) |
|||
|
|||
MC0_DDR3_CTL_290 : .dword 0x0000000000000000 |
|||
//hXXXXXXX 00_00 dll_obs_reg_0_2(RW) hXXXXXXX 00_00 dll_obs_reg_0_1(RW) |
|||
MC0_DDR3_CTL_2a0 : .dword 0x0000000000000000 |
|||
//hXXXXXXX 00_00 dll_obs_reg_0_4(RW) hXXXXXXX 00_00 dll_obs_reg_0_3(RW) |
|||
MC0_DDR3_CTL_2b0 : .dword 0x0000000000000000 |
|||
//hXXXXXXX 00_00 dll_obs_reg_0_6(RW) hXXXXXXX 00_00 dll_obs_reg_0_5(RW) |
|||
MC0_DDR3_CTL_2c0 : .dword 0x0000000000000000 |
|||
//hXXXXXXX 00_00 dll_obs_reg_0_8(RW) hXXXXXXX 00_00 dll_obs_reg_0_7(RW) |
|||
//11110100000000000011101100100111 phy_ctrl_reg_0_0(RD) 000000_00000000000000000110011101 pad_ctrl_reg_0(RW) |
|||
MC0_DDR3_CTL_2d0 : .dword 0x04003733003c09b5 |
|||
MC0_DDR3_CTL_2e0 : .dword 0x0400373304003733 |
|||
MC0_DDR3_CTL_2f0 : .dword 0x0400373304003733 |
|||
MC0_DDR3_CTL_300 : .dword 0x0400373304003733 |
|||
MC0_DDR3_CTL_310 : .dword 0x0400373304003733 |
|||
MC0_DDR3_CTL_320 : .dword 0x26c0000126c00001 |
|||
MC0_DDR3_CTL_330 : .dword 0x26c0000126c00001 |
|||
MC0_DDR3_CTL_340 : .dword 0x26c0000126c00001 |
|||
MC0_DDR3_CTL_350 : .dword 0x26c0000126c00001 |
|||
MC0_DDR3_CTL_360 : .dword 0x0000c10026c00001 |
|||
//00000000000000001100000000000101 phy_ctrl_reg_2(RW) 00000111110000000000001100000001 phy_ctrl_reg_1_8(RW) |
|||
//-------------- |
|||
MC0_DDR3_CTL_370 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_380 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_390 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_3a0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_3b0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_3c0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_3d0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_3e0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_3f0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_400 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_410 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_420 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_430 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_440 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_450 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_460 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_470 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_480 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_490 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_4a0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_4b0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_4c0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_4d0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_4e0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_4f0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_500 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_510 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_520 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_530 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_540 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_550 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_560 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_570 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_580 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_590 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_5a0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_5b0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_5c0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_5d0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_5e0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_5f0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_600 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_610 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_620 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_630 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_640 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_650 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_660 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_670 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_680 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_690 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_6a0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_6b0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_6c0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_6d0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_6e0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_6f0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_CTL_700 : .dword 0x0000000000000000 |
|||
//------------- |
|||
MC0_DDR3_CTL_710 : .dword 0x0000000000000000 |
|||
//bit 48 en_wr_leveling(RD)(replaced by wrlvl_en in LS3A3) |
|||
MC0_DDR3_CTL_720 : .dword 0x0000000000000000 |
|||
//0000000_0 rdlvl_gate_req(WR) 0000000_0 rdlvl_gate_preamble_check_en(RW) 0000000_0 rdlvl_gate_en(RW) 0000000_0 rdlvl_en(RW) 0000000_0 rdlvl_begin_delay_en(RW) 00000000 0000000_0 swlvl_op_done(RD) 00000000 |
|||
MC0_DDR3_CTL_730 : .dword 0x0000000000000000 |
|||
//0000000_0 rdlvl_offset_dir_7(RW) 0000000_0 rdlvl_offset_dir_6(RW) 0000000_0 rdlvl_offset_dir_5(RW)0000000_0 rdlvl_offset_dir_4(RW) 0000000_0 rdlvl_offset_dir_3(RW) 0000000_0 rdlvl_offset_dir_2(RW) 0000000_0 rdlvl_offset_dir_1(RW) 0000000_0 rdlvl_offset_dir_0(RW) |
|||
MC0_DDR3_CTL_740 : .dword 0x0100000000000000 |
|||
//000000_00 axi1_port_ordering(RW) 000000_00 axi0_port_ordering(RW) 0000000_0 wrlvl_req(WR) 0000000_0 wrlvl_interval_ct_en(RW) 0000000_0 weight_round_robin_weight_sharing(RW) 0000000_0 weight_round_robin_latency_control 0000000_0(RW) rdlvl_req 0000000_0(WR) rdlvl_offset_dir_8(RW) |
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MC0_DDR3_CTL_750 : .dword 0x0000000101020101 |
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//000000_01 wrlvl_cs(RW) 000000_00 sw_leveling_mode(RW) 000000_00 rdlvl_cs(RW) 000000_01 axi2_w_priority(RW) 000000_01 axi2_r_priority(RW) 000000_10 axi2_port_ordering(RW) 000000_01 axi1_w_priority(RW) 000000_01 axi1_r_priority(RW) |
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MC0_DDR3_CTL_760 : .dword 0x0303030a00030002 |
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//0000_0011 axi0_priority2_relative_priority(RW) 0000_0011 axi0_priority1_relative_priority(RW) 0000_0011 axi0_priority0_relative_priority(RW) 0000_0000 address_mirroring(RW) 00000_000 tdfi_dram_clk_disable(RW) 00000_010 bstlen(RW) 000000_00 zq_req(WR) 000000_01 zq_on_sref_exit(RW) |
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MC0_DDR3_CTL_770 : .dword 0x0101010202020203 |
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//0000_0001 axi2_priority2_relative_priority(RW) 0000_0001 axi2_priority1_relative_priority(RW) 0000_0001 axi2_priority0_relative_priority(RW) 0000_0010 axi1_priority3_relative_priority(RW) 0000_0010 axi1_priority2_relative_priority(RW) 0000_0010 axi1_priority1_relative_priority(RW) 0000_0010 axi1_priority0_relative_priority(RW) 0000_0011 axi0_priority3_relative_priority(RW) |
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MC0_DDR3_CTL_780 : .dword 0x0102020400060c01 |
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//0000_0001 tdfi_dram_clk_enable(RW) 0000_0010 tdfi_ctrl_delay(RW) 0000_0010 rdlvl_gate_dq_zero_count(RW) 0000_0100 rdlvl_dq_zero_count(RW) 0000_0000 lowpower_refresh_enable(RW) 0000_0110 dram_class(RW) 0000_1100 burst_on_fly_bit(RW) 0000_0001 axi2_priority3_relative_priority(RW) |
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MC0_DDR3_CTL_790 : .dword 0x2819000000000f0f |
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//00_101000 wlmrd(RW) 00_011001 wldqsen(RW) 000_00000 lowpower_control(RW) 000_00000 lowpower_auto_enable(RW) 0000_1111 zqcs_chip(RD) 0000_0000 wrr_param_value_err(RD) 0000_0011 tdfi_wrlvl_dll(RW) 0000_0011 tdfi_rdlvl_dll(RW) |
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MC0_DDR3_CTL_7a0 : .dword 0x00000000000000ff |
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//_00000000 swlvl_resp_6(RW) _00000000 swlvl_resp_5(RW) _00000000 swlvl_resp_4 _00000000 swlvl_resp_3(RW) _00000000 swlvl_resp_2(RW) _00000000 swlvl_resp_1(RW) _00000000 swlvl_resp_0(RW) _00000000 dfi_wrlvl_max_delay(RW) |
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MC0_DDR3_CTL_7b0 : .dword 0x0000000000000000 |
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//_00000000 rdlvl_begin_delay_5(RW) _00000000 rdlvl_begin_delay_4(RW) _00000000 rdlvl_begin_delay_3(RW) _00000000 rdlvl_begin_delay_2(RW) _00000000 rdlvl_begin_delay_1(RW) _00000000 rdlvl_begin_delay_0(RW) _00000000 swlvl_resp_8(RW) _00000000 swlvl_resp_7(RW) |
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MC0_DDR3_CTL_7c0 : .dword 0x0000000000000000 |
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//_00000000 rdlvl_end_delay_4(RW) _00000000 rdlvl_end_delay_3(RW) _00000000 rdlvl_end_delay_2(RW) _00000000 rdlvl_end_delay_1(RW) _00000000 rdlvl_end_delay_0(RW) _00000000 rdlvl_begin_delay_8(RW) _00000000 rdlvl_begin_delay_7(RW) _00000000 rdlvl_begin_delay_6(RW) |
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MC0_DDR3_CTL_7d0 : .dword 0x0000000000000000 |
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//_00000000 rdlvl_gate_clk_adjust_3(RW) _00000000 rdlvl_gate_clk_adjust_2(RW) _00000000 rdlvl_gate_clk_adjust_1(RW) _00000000 rdlvl_gate_clk_adjust_0(RW) _00000000 rdlvl_end_delay_8(RW) _00000000 rdlvl_end_delay_7(RW) _00000000 rdlvl_end_delay_6(RW) 00000000 rdlvl_end_delay_5(RW) |
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MC0_DDR3_CTL_7e0 : .dword 0x0000000000000000 |
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//00000000 rdlvl_gate_delay_2(RD) 00000000 rdlvl_gate_delay_1(RD) 00000000 rdlvl_gate_delay_0(RD) 00000000 rdlvl_gate_clk_adjust_8(RW) 00000000 rdlvl_gate_clk_adjust_7(RW) 00000000 rdlvl_gate_clk_adjust_6(RW) 00000000 rdlvl_gate_clk_adjust_5(RW) 00000000 rdlvl_gate_clk_adjust_4(RW) |
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MC0_DDR3_CTL_7f0 : .dword 0x0000000000000000 |
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//11111111 rdlvl_max_delay(RW) 00001000 rdlvl_gate_max_delay(RW) 00000000 rdlvl_gate_delay_8(RW) 00000000 rdlvl_gate_delay_7(RW) 00000000 rdlvl_gate_delay_6(RW) 00000000 rdlvl_gate_delay_5(RW) 00000000 rdlvl_gate_delay_4(RW) 00000000 rdlvl_gate_delay_3(RW) |
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MC0_DDR3_CTL_800 : .dword 0x0000000000000000 |
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//00000000 rdlvl_midpoint_delay_7(RD) 00000000 rdlvl_midpoint_delay_6(RD) 00000000 rdlvl_midpoint_delay_5(RD) 00000000 rdlvl_midpoint_delay_4(RD) 00000000 rdlvl_midpoint_delay_3(RD) 00000000 rdlvl_midpoint_delay_2(RD) 00000000 rdlvl_midpoint_delay_1(RD) 00000000 rdlvl_midpoint_delay_0(RD) |
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MC0_DDR3_CTL_810 : .dword 0x0000000000000000 |
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//00000000 rdlvl_offset_delay_6(RW) 00000000 rdlvl_offset_delay_5(RW) 00000000 rdlvl_offset_delay_4(RW) 00000000 rdlvl_offset_delay_3(RW) 00000000 rdlvl_offset_delay_2(RW) 00000000 rdlvl_offset_delay_1(RW) 00000000 rdlvl_offset_delay_0(RW) 00000000 rdlvl_midpoint_delay_8(RD) |
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MC0_DDR3_CTL_820 : .dword 0xee0000ee00400000 |
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//00000100 tdfi_wrlvl_resplat(RW) 00000000 tdfi_wrlvl_resp(RD) 00000000 tdfi_rdlvl_rr(RW) 00001100 tdfi_rdlvl_resplat(RW) 00000000 tdfi_rdlvl_resp(RD) 01000000 refresh_per_zq(RW) 00000000 rdlvl_offset_delay_8(RW) 00000000 rdlvl_offset_delay_7(RW) |
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MC0_DDR3_CTL_830 : .dword 0x0000000000000c00 |
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//00000000 wrlvl_delay_5(RD) 00000000 wrlvl_delay_4(RD) 00000000 wrlvl_delay_3(RD) 00000000 wrlvl_delay_2(RD) 00000000 wrlvl_delay_1(RD) 00000000 wrlvl_delay_0(RD) 00000010 tmod(RW) 00000000 tdfi_wrlvl_ww(RD) |
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MC0_DDR3_CTL_840 : .dword 0x0000640064000000 |
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//00000000000000_0001100100 axi1_priority_relax(RW) 000000_0001100100 axi0_priority_relax(RW) 00000000 wrlvl_delay_8(RD) 00000000 wrlvl_delay_7(RD) 00000000 wrlvl_delay_6(RD) |
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MC0_DDR3_CTL_850 : .dword 0x0000000000000064 |
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//000000_0000000000 out_of_range_source_id(RD) 000000_0000000000 ecc_u_id(RD) 000000_0000000000 ecc_c_id(RD) 000000_0000000000 axi2_priority_relax(RW) |
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MC0_DDR3_CTL_860 : .dword 0x0200004000000000 |
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//0000_000000000000 zqini(RW) 0000_000000000000 zqcs(RW) 000000_0000000000 port_data_error_id(RD) 000000_0000000000 port_cmd_error_id(RD) |
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MC0_DDR3_CTL_870 : .dword 0x0000000000000000 |
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//0_000000000000010 emrs1_data_3(RD) 0_000000000000010 emrs1_data_2(RD) 0_000000000000010 emrs1_data_1(RD) 0_000000000000010 emrs1_data_0(RD) |
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MC0_DDR3_CTL_880 : .dword 0x0000000000000000 |
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//0_000000000000010 emrs3_data_3(RW) 0_000000000000010 emrs3_data_2(RW) 0_000000000000010 emrs3_data_1(RW) 0_000000000000010 emrs3_data_0(RW) |
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MC0_DDR3_CTL_890 : .dword 0x0000000000000000 |
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//0_000010000010000 mrs_data_3(RD) 0_000010000010000 mrs_data_2(RD) 0_000010000010000 mrs_data_1(RD) 0_000010000010000 mrs_data_0(RD) |
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MC0_DDR3_CTL_8a0 : .dword 0x00000000001c001c |
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//hXXXX lowpower_internal_cnt(RW) hXXXX lowpower_external_cnt(RW) hXXXX axi2_en_size_lt_width_instr(RW) hXXXX axi1_en_size_lt_width_instr(RW) |
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MC0_DDR3_CTL_8b0 : .dword 0x0000000000000000 |
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//hXXXX refresh_per_rdlvl(RW) hXXXX lowpower_self_refresh_cnt(RW) hXXXX lowpower_refresh_hold(RW) hXXXX lowpower_power_down_cnt(RW) |
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MC0_DDR3_CTL_8c0 : .dword 0x0000000000000000 |
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//hXXXX wrlvl_interval(RW) hXXXX tdfi_wrlvl_max(RW) hXXXX tdfi_rdlvl_max(RW) hXXXX refresh_per_rdlvl_gate(RW) |
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MC0_DDR3_CTL_8d0 : .dword 0x0000030d40000000 |
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//h00_XXXXXXXX cke_inactive(RW) 000000_000000000000000000 wrlvl_status(RD) |
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MC0_DDR3_CTL_8e0 : .dword 0x0000000023c34600 |
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//h00000000_XXXXXXXX trst_pwron(RW) |
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MC0_DDR3_CTL_8f0 : .dword 0x0000000000000080 |
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//hXXXXXXX 000_0 XXXXXXXX dll_ctrl_reg_2(RW) |
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MC0_DDR3_CTL_900 : .dword 0x0000000000000000 |
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//h000000 00_00 X XXXXXXXX rdlvl_error_status(RW) |
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MC0_DDR3_CTL_910 : .dword 0x0000000000000000 |
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//hXXXXXXXX XXXXXXXX rdlvl_gate_resp_mask[63:0](RW) |
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MC0_DDR3_CTL_920 : .dword 0x0000000000000000 |
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//h00000000000000_XX rdlvl_gate_resp_mask[71:64](RW) |
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MC0_DDR3_CTL_930 : .dword 0x0000000000000000 |
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//hXXXXXXXX XXXXXXXX rdlvl_resp_mask[63:0](RW) |
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MC0_DDR3_CTL_940 : .dword 0xff07070000060600 |
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//0000_0000 tdfi_rdlvl_en(RW) 00000_000 w2r_samecs_delay(RW) 00000_000 w2r_diffcs_delay(RW) 00000_000 lvl_status(RD) 0000000_0 rdlvl_edge(RW) 0000_0000 cksrx(RW) 0000_0000 cksre(RW) _00000000 rdlvl_resp_mask[71:64](RW) |
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MC0_DDR3_CTL_950 : .dword 0x0000000000000d00 |
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//hXXXXX 00_00 XXXX mask_int[17:0](RW) hXXXX txpdll(RW) 0000_0000 tdfi_wrlvl_en(RW) |
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MC0_DDR3_CTL_960 : .dword 0x0705000000000000 |
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//000_00101 rdlat_adj(RW) 0000_0100 wrlat_adj(RW) 0000000_0 swlvl_start(WR) 0000000_0 swlvl_load(WR) 0000000_0 swlvl_exit(WR) 000000_000000000000000000 int_status(RD) |
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MC0_DDR3_CTL_970 : .dword 0x010000000003e825 |
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//h00000 000_0 concurrentap_wr_only XXXX int_ack[16:0](WR) hXXXX dll_rst_delay(RW) hXX dll_rst_adj_dly(RW) |
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MC0_DDR3_CTL_980 : .dword 0x0001010001000101 |
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//0000000_0 zq_in_progress(RD) 0000000_1 zqcs_rotate(RW) 0000000_0 wrlvl_reg_en(RW) 0000000_0 wrlvl_en(RW) 0000000_1 resync_dll_per_aref_en(RW) 0000000_0 resync_dll(WR) 0000000_0 rdlvl_reg_en(RW) 0000000_0 rdlvl_gate_reg_en(RW) |
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MC0_DDR3_CTL_990 : .dword 0x0707040707070700 |
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//00000_000 w2w_samecs_dly(RW) 00000_001 w2w_diffcs_dly(RW) 00000_010 tbst_int_interval(RW) 00000_010 r2w_samecs_dly(RW) 00000_010 r2w_diffcs_dly(RW) 00000_000 r2r_samecs_dly(RW) 00000_001 r2r_diffcs_dly(RW) 00000_000 axi_aligned_strobe_disable(RW) |
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MC0_DDR3_CTL_9a0 : .dword 0x0707040804080404 |
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//00000111 tdfi_wrlvl_load(RW) 00000111 tdfi_rdlvl_load(RW) 000_00011 tckesr(RW) 000_00010 tccd(RW) 000_00000 add_odt_clk_difftype_diffcs(RW) 0000_0110 trp_ab(RW) 0000_0001 add_odt_clk_sametype_diffcs(RW) 0000_0000 add_odt_clk_difftype_samecs(RW) |
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MC0_DDR3_CTL_9b0 : .dword 0x02000100000a000f |
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//0000_001000000000 zqinit(RW) 0000_000100000000 zqcl(RW) 000000_0000001010 tdfi_wrlvl_ww(RW) 000000_0000001111 tdfi_rdlvl_rr(RW) |
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MC0_DDR3_CTL_9c0 : .dword 0x04200c2d0c2d0c2d |
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//0_000101001010010 mr0_data_0(RW) 00_00110000101101 tdfi_phyupd_type3(RW) 00_00110000101101 tdfi_phyupd_type2(RW) 00_00110000101101 tdfi_phyupd_type1(RW) |
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MC0_DDR3_CTL_9d0 : .dword 0x0044042004200420 |
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//0_000000000000100 mr1_data_0(RW) 0_000101001010010 mr0_data_3(RW) 0_000101001010010 mr0_data_2(RW) 0_000101001010010 mr0_data_1(RW) |
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MC0_DDR3_CTL_9e0 : .dword 0x0000004400440044 |
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//0_000000000000000 mr2_data_0(RW) 0_000000000000100 mr1_data_3(RW) 0_000000000000100 mr1_data_2(RW) 0_000000000000100 mr1_data_1(RW) |
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MC0_DDR3_CTL_9f0 : .dword 0x0000000000000000 |
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//0_000000000000000 mr3_data_0(RW) 0_000000000000000 mr2_data_3(RW) 0_000000000000000 mr2_data_2(RW) 0_000000000000000 mr2_data_1(RW) |
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MC0_DDR3_CTL_a00 : .dword 0x007f000000000000 |
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//0000000011111111 dfi_wrlvl_max_delay(RW) 0_000000000000000 mr3_data_3(RW) 0_000000000000000 mr3_data_2(RW) 0_000000000000000 mr3_data_1(RW) |
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MC0_DDR3_CTL_a10 : .dword 0x0000000000000000 |
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//0000000000000000 rdlvl_begin_delay_3(RD) 0000000000000000 rdlvl_begin_delay_2(RD) 0000000000000000 rdlvl_begin_delay_1(RD) 0000000000000000 rdlvl_begin_delay_0(RD) |
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MC0_DDR3_CTL_a20 : .dword 0x0000000000000000 |
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//0000000000000000 rdlvl_begin_delay_7(RD) 0000000000000000 rdlvl_begin_delay_6(RD) 0000000000000000 rdlvl_begin_delay_5(RD) 0000000000000000 rdlvl_begin_delay_4(RD) |
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MC0_DDR3_CTL_a30 : .dword 0x0020002000200000 |
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//0000111000001110 rdlvl_delay_2(RW) 0000111000001110 rdlvl_delay_1(RW) 0000111000001110 rdlvl_delay_0(RW) 0000000000000000 rdlvl_begin_delay_8(RD) |
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MC0_DDR3_CTL_a40 : .dword 0x0020002000200020 |
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//0000111000001110 rdlvl_delay_6(RW) 0000111000001110 rdlvl_delay_5(RW) 0000111000001110 rdlvl_delay_4(RW) 0000111000001110 rdlvl_delay_3(RW) |
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MC0_DDR3_CTL_a50 : .dword 0x0000000000200020 |
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//0000000000000000 rdlvl_end_delay_1(RD) 0000000000000000 rdlvl_end_delay_0(RD) 0000111000001110 rdlvl_delay_8(RW) 0000111000001110 rdlvl_delay_7(RW) |
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MC0_DDR3_CTL_a60 : .dword 0x0000000000000000 |
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//0000000000000000 rdlvl_end_delay_5(RD) 0000000000000000 rdlvl_end_delay_4(RD) 0000000000000000 rdlvl_end_delay_3(RD) 0000000000000000 rdlvl_end_delay_2(RD) |
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MC0_DDR3_CTL_a70 : .dword 0x0019000000000000 |
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//0000000000000000 rdlvl_gate_delay_0(RW+) 0000000000000000 rdlvl_end_delay_8(RD) 0000000000000000 rdlvl_end_delay_7(RD) 0000000000000000 rdlvl_end_delay_6(RD) |
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MC0_DDR3_CTL_a80 : .dword 0x0019001900190019 |
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//0000000000000000 rdlvl_gate_delay_4(RW+) 0000000000000000 rdlvl_gate_delay_3(RW+) 0000000000000000 rdlvl_gate_delay_2(RW+) 0000000000000000 rdlvl_gate_delay_1(RW+) |
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MC0_DDR3_CTL_a90 : .dword 0x0019001900190019 |
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//0000000000000000 rdlvl_gate_delay_8(RW+) 0000000000000000 rdlvl_gate_delay_7(RW+) 0000000000000000 rdlvl_gate_delay_6(RW+) 0000000000000000 rdlvl_gate_delay_5(RW+) |
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MC0_DDR3_CTL_aa0 : .dword 0x0000ffff00000022 |
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//0000000000000000 rdlvl_midpoint_delay_0(RD) 1111111111111111 rdlvl_max_delay(RW) 0000000000000000 rdlvl_gate_refresh_interval(RW) 0000000000010000 rdlvl_gate_max_delay(RW) |
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MC0_DDR3_CTL_ab0 : .dword 0x0000000000000000 |
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//0000000000000000 rdlvl_midpoint_delay_4(RD) 0000000000000000 rdlvl_midpoint_delay_3(RD) 0000000000000000 rdlvl_midpoint_delay_2(RD) 0000000000000000 rdlvl_midpoint_delay_1(RD) |
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MC0_DDR3_CTL_ac0 : .dword 0x0000000000000000 |
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//0000000000000000 rdlvl_midpoint_delay_8(RD) 0000000000000000 rdlvl_midpoint_delay_7(RD) 0000000000000000 rdlvl_midpoint_delay_6(RD) 0000000000000000 rdlvl_midpoint_delay_5(RD) |
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MC0_DDR3_CTL_ad0 : .dword 0x0000000000000000 |
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//0000000000000000 rdlvl_offset_delay_3(RW) 0000000000000000 rdlvl_offset_delay_2(RW) 0000000000000000 rdlvl_offset_delay_1(RW) 0000000000000000 rdlvl_offset_delay_0(RW) |
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MC0_DDR3_CTL_ae0 : .dword 0x0000000000000000 |
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//0000000000000000 rdlvl_offset_delay_7(RW) 0000000000000000 rdlvl_offset_delay_6(RW) 0000000000000000 rdlvl_offset_delay_5(RW) 0000000000000000 rdlvl_offset_delay_4(RW) |
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MC0_DDR3_CTL_af0 : .dword 0x0020001800000000 |
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//0000000000000000 wrlvl_delay_1(RW+) 0000000000000000 wrlvl_delay_0(RW+) 0000000000000000 rdlvl_refresh_interval(RW) 0000000000000000 rdlvl_offset_delay_8(RW) |
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MC0_DDR3_CTL_b00 : .dword 0x0042003c00300028 |
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//0000000000000000 wrlvl_delay_5(RW+) 0000000000000000 wrlvl_delay_4(RW+) 0000000000000000 wrlvl_delay_3(RW+) 0000000000000000 wrlvl_delay_2(RW+) |
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MC0_DDR3_CTL_b10 : .dword 0x00000028004e0048 |
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//0000000000000000 wrlvl_refresh_interval(RW) 0000000000000000 wrlvl_delay_8(RW+) 0000000000000000 wrlvl_delay_7(RW+) 0000000000000000 wrlvl_delay_6(RW+) |
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MC0_DDR3_CTL_b20 : .dword 0x00000c2d00000c2d |
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//00000000000000000000110000101101 tdfi_rdlvl_resp(RW) 00000000000000000000110000101101 tdfi_rdlvl_max(RW) |
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MC0_DDR3_CTL_b30 : .dword 0x00000c2d00000c2d |
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//00000000000000000000110000101101 tdfi_wrlvl_resp(RW) 00000000000000000000000000000000 tdfi_wrlvl_max(RW) |
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#endif |
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|
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ddr3_reg_data_mc1: |
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#ifdef DDR3_DIMM |
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MC1_DDR3_CTL_000 : .dword 0x0000010000000100 |
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//000000000000000_0 concurrentap(RW) 0000000_1 bank_split_en(RW) 0000000_0 auto_refresh_mode(RW) 0000000_0 arefresh(WR) 0000000_0 ap(RW) 0000000_1 addr_cmp_en(RW) 0000000_1 active_aging(RW) |
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MC1_DDR3_CTL_010 : .dword 0x0000000100010000 |
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//0000000_0 fwc(WR) 0000000_0 fast_write(RW) 0000000_1 enable_quick_srefresh(RW) 0000000_1 eight_bank_mode(RW) 0000000_0 ecc_disable_w_uc_err(RW) 0000000_1 dqs_n_en(RW) 0000000_0 dll_bypass_mode(RW) 0000000_0 dlllockreg(RD) |
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MC1_DDR3_CTL_020 : .dword 0x0100010000000000 |
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//0000000_1 priority_en(RW) 0000000_0 power_down(RW) 0000000_1 placement_en(RW) 0000000_0 odt_add_turn_clk_en(RD) 0000000_0 no_cmd_init(RW) 0000000_0 intrptwritea(RW) 0000000_0 intrptreada(RW) 0000000_0 intrptapburst(RW) |
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MC1_DDR3_CTL_030 : .dword 0x0001000001000000 |
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//0000000_1 swap_port_rw_same_en(RW) 0000000_1 swap_en(RW) 0000000_0 start(RW) 0000000_0 srefresh(RW+) 0000000_1 rw_same_en(RW) 0000000_0 reg_dimm_enable(RW) 0000000_0 reduc(RW) 0000000_0 pwrup_srefresh_exit(RW) |
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MC1_DDR3_CTL_040 : .dword 0x0002010100000101 |
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//000000_00 rtt_0(RD) 000000_11 ctrl_raw(RW) 000000_01 axi0_w_priority(RW) 000000_01 axi0_r_priority(RW) 0000000_0 write_modereg(WR) 0000000_1 writeinterp(RW) 0000000_1 tref_enable(RW) 0000000_1 tras_lockout(RW) |
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MC1_DDR3_CTL_050 : .dword 0x0700000004060100 |
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//00000_000 q_fullness(RW) 00000_000 port_data_error_type(RD) 000_00000 out_of_range_type(RD) 00000_000 max_cs_reg(RD) 00000_100 column_size(RW) 0000_0101 caslat(RW) 00000_010 addr_pins(RW) 00000000 |
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MC1_DDR3_CTL_060 : .dword 0x0a05050805050003 |
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//0000_1010 aprebit(RW) 0000_0101 wrlat(RW) 0000_0100 twtr(RW) 000_00110 twr_int(RW) 00000_011 trtp(RW) 00000_100 trrd(RW) 0000000000000_011 tcke(RW) |
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MC1_DDR3_CTL_070 : .dword 0x0000000000030c0c |
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//0000_1111 max_row_reg(RD) 0000_1110 max_col_reg(RD) 0000_0000 initaref(RW) 00000000000000000000_1111 cs_map(RW) 000_01010 caslat_lin_gate(RW) 000_01010 caslat_lin(RW) |
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MC1_DDR3_CTL_080 : .dword 0x0804020100000000 |
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//0000_0001 odt_wr_map_cs3(RW) 0000_0010 odt_wr_map_cs2(RW) 0000_0100 odt_wr_map_cs1(RW) 0000_1000 odt_wr_map_cs0(RW) 0000_0001 odt_rd_map_cs3(RW) 0000_0010 odt_rd_map_cs2(RW) 0000_0100 odt_rd_map_cs1(RW) 0000_1000 odt_rd_map_cs0(RW) |
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MC1_DDR3_CTL_090 : .dword 0x0000070f00000000 |
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//000_00000 ocd_adjust_pup_cs_0(RW) 000_00000 ocd_adjust_pdn_cs_0(RW) 0000_0101 trp(RW) 000_01011 tdal(RW) 000000000000_0000 port_cmd_error_type(RD) 0000000000000000 |
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MC1_DDR3_CTL_0a0 : .dword 0x0000001f3f140412 |
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//00000000000000000000000000_111111 command_age_count(RW) 00_111111 age_count(RW) 000_10100 trc(RW) 000_00110 tmrd(RW) 000_10010 tfaw(RW) |
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MC1_DDR3_CTL_0b0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_0c0 : .dword 0x000040060f000000 |
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//000000000000000000101100 trfc(RW) 00000101 trcd_int(RW) 00001111 tras_min(RW) 00000000 out_of_range_length(RD) 00000000 ecc_u_synd(RD) 00000000 ecc_c_synd(RD) |
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MC1_DDR3_CTL_0d0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_0e0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_0f0 : .dword 0x0000000000000000 |
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//Bit 21:16 dll_lock(RD) |
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MC1_DDR3_CTL_100 : .dword 0x0000000000000000 |
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//MC1_DDR3_CTL_110 : .dword 0x00000000000005e0 #200M+ |
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MC1_DDR3_CTL_110 : .dword 0x0000000000000900 #300M+ |
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//MC1_DDR3_CTL_110 : .dword 0x0000000000000c00 #400M+ |
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//0_000000000000000 emrs2_data_1(RW) 0_000000000000000 emrs2_data_0(RW) 000000000000000000_00110000101101 tref(RW) |
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MC1_DDR3_CTL_120 : .dword 0x001c000000000000 |
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//0000000000011100 axi0_en_size_lt_width_instr(RW) hXXXX 0_000000000000000 emrs2_data_3(RW) 0_000000000000000 emrs2_data_2(RW) |
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//MC1_DDR3_CTL_130 : .dword 0x36800003020000c8 #200M+ |
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MC1_DDR3_CTL_130 : .dword 0x52100003020000c8 #300M--400M |
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//MC1_DDR3_CTL_130 : .dword 0x6d800004020010b #400M--533M |
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//0110110101010110 tras_max(RW) 0000000000000011 tpdex(RW) 0000001000000000 tdll(RW) 0000000000000000 tcpd(RW) |
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MC1_DDR3_CTL_140 : .dword 0x0000000002000044 |
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//0000000000000000 xor_check_bits(RW) 0000000000000000 version(RD) 0000001000000000 txsr(RW) 0000000000110000 txsnr(RW) |
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MC1_DDR3_CTL_150 : .dword 0x0000000000027100 |
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//000_0000000000000000000000000000000000000 ecc_c_addr(RD) hXXXXXX tinit(RW) |
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MC1_DDR3_CTL_160 : .dword 0x0000000000000000 |
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//000000000000000000000000000_0000000000000000000000000000000000000 ecc_u_addr(RD) |
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MC1_DDR3_CTL_170 : .dword 0x0000000000000000 |
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//000000000000000000000000000_0000000000000000000000000000000000000 out_of_range_addr(RD) |
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MC1_DDR3_CTL_180 : .dword 0x0000000000000000 |
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//000000000000000000000000000_0000000000000000000000000000000000000 port_cmd_error_addr(RD) |
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MC1_DDR3_CTL_190 : .dword 0x0000000000000000 |
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//0000000000000000000000000000000000000000000000000000000000000000 ecc_c_data(RD) |
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MC1_DDR3_CTL_1a0 : .dword 0x0000000000000000 |
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//0000000000000000000000000000000000000000000000000000000000000000 ecc_u_data(RD) |
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MC1_DDR3_CTL_1b0 : .dword 0x0000000000000007 |
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//0000000000000000000000000000000000000000000000000000000000000_000 cke_delay(RW) |
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MC1_DDR3_CTL_1c0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_1d0 : .dword 0x02000b0000000001 |
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//0000_0010 tdfi_phy_wrlat_base(RW) 0000_0000 tdfi_phy_wrlat(RD) 000_00111 tdfi_phy_rdlat(RW) 0000_0100 tdfi_ctrlupd_min(RD) 000000000000_0000 dram_clk_disable(RW) 0000000_1 odt_alt_en(RW) 0000000_1 drive_dq_dqs(RW) |
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MC1_DDR3_CTL_1e0 : .dword 0x0000000000000200 |
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//00_00000000000000 tdfi_phyupd_type0(RD) 00_00000000000000 tdfi_phyupd_resp(RD) 00_00000000000000 tdfi_ctrlupd_max(RD) 000_00000 tdfi_rddata_en_base(RW) 000_00000 tdfi_rddata_en(RD) |
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//hXXXXXXXX dll_ctrl_reg_0_0(RW) h000000 hXX dft_ctrl_reg(RW) |
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MC1_DDR3_CTL_1f0 : .dword 0x0020008000000000 |
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MC1_DDR3_CTL_200 : .dword 0x0020008000200080 |
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MC1_DDR3_CTL_210 : .dword 0x0020008000200080 |
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MC1_DDR3_CTL_220 : .dword 0x0020008000200080 |
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MC1_DDR3_CTL_230 : .dword 0x0020008000200080 |
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MC1_DDR3_CTL_240 : .dword 0x0000200000002000 |
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MC1_DDR3_CTL_250 : .dword 0x0000200000002000 |
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MC1_DDR3_CTL_260 : .dword 0x0000200000002000 |
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MC1_DDR3_CTL_270 : .dword 0x0000200000002000 |
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MC1_DDR3_CTL_280 : .dword 0x0000000000002000 |
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//hXXXXXXX 00_00 dll_obs_reg_0_0(RW) 00000000000000000000111000000000 dll_ctrl_reg_1_8(RW) |
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MC1_DDR3_CTL_290 : .dword 0x0000000000000000 |
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//hXXXXXXX 00_00 dll_obs_reg_0_2(RW) hXXXXXXX 00_00 dll_obs_reg_0_1(RW) |
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MC1_DDR3_CTL_2a0 : .dword 0x0000000000000000 |
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//hXXXXXXX 00_00 dll_obs_reg_0_4(RW) hXXXXXXX 00_00 dll_obs_reg_0_3(RW) |
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MC1_DDR3_CTL_2b0 : .dword 0x0000000000000000 |
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//hXXXXXXX 00_00 dll_obs_reg_0_6(RW) hXXXXXXX 00_00 dll_obs_reg_0_5(RW) |
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MC1_DDR3_CTL_2c0 : .dword 0x0000000000000000 |
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//hXXXXXXX 00_00 dll_obs_reg_0_8(RW) hXXXXXXX 00_00 dll_obs_reg_0_7(RW) |
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//11110100000000000011101100100111 phy_ctrl_reg_0_0(RD) 000000_00000000000000000110011101 pad_ctrl_reg_0(RW) |
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MC1_DDR3_CTL_2d0 : .dword 0x04003733003c09b5 |
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MC1_DDR3_CTL_2e0 : .dword 0x0400373304003733 |
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MC1_DDR3_CTL_2f0 : .dword 0x0400373304003733 |
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MC1_DDR3_CTL_300 : .dword 0x0400373304003733 |
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MC1_DDR3_CTL_310 : .dword 0x0400373304003733 |
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MC1_DDR3_CTL_320 : .dword 0x26c0000126c00001 |
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MC1_DDR3_CTL_330 : .dword 0x26c0000126c00001 |
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MC1_DDR3_CTL_340 : .dword 0x26c0000126c00001 |
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MC1_DDR3_CTL_350 : .dword 0x26c0000126c00001 |
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MC1_DDR3_CTL_360 : .dword 0x0000c10026c00001 |
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//00000000000000001100000000000101 phy_ctrl_reg_2(RW) 00000111110000000000001100000001 phy_ctrl_reg_1_8(RW) |
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//-------------- |
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MC1_DDR3_CTL_370 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_380 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_390 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_3a0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_3b0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_3c0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_3d0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_3e0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_3f0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_400 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_410 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_420 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_430 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_440 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_450 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_460 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_470 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_480 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_490 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_4a0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_4b0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_4c0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_4d0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_4e0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_4f0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_500 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_510 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_520 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_530 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_540 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_550 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_560 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_570 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_580 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_590 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_5a0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_5b0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_5c0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_5d0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_5e0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_5f0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_600 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_610 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_620 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_630 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_640 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_650 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_660 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_670 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_680 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_690 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_6a0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_6b0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_6c0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_6d0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_6e0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_6f0 : .dword 0x0000000000000000 |
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MC1_DDR3_CTL_700 : .dword 0x0000000000000000 |
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//------------- |
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MC1_DDR3_CTL_710 : .dword 0x0000000000000000 |
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//bit 48 en_wr_leveling(RD)(replaced by wrlvl_en in LS3A3) |
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MC1_DDR3_CTL_720 : .dword 0x0000000000000000 |
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//0000000_0 rdlvl_gate_req(WR) 0000000_0 rdlvl_gate_preamble_check_en(RW) 0000000_0 rdlvl_gate_en(RW) 0000000_0 rdlvl_en(RW) 0000000_0 rdlvl_begin_delay_en(RW) 00000000 0000000_0 swlvl_op_done(RD) 00000000 |
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MC1_DDR3_CTL_730 : .dword 0x0000000000000000 |
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//0000000_0 rdlvl_offset_dir_7(RW) 0000000_0 rdlvl_offset_dir_6(RW) 0000000_0 rdlvl_offset_dir_5(RW)0000000_0 rdlvl_offset_dir_4(RW) 0000000_0 rdlvl_offset_dir_3(RW) 0000000_0 rdlvl_offset_dir_2(RW) 0000000_0 rdlvl_offset_dir_1(RW) 0000000_0 rdlvl_offset_dir_0(RW) |
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MC1_DDR3_CTL_740 : .dword 0x0100000000000000 |
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//000000_00 axi1_port_ordering(RW) 000000_00 axi0_port_ordering(RW) 0000000_0 wrlvl_req(WR) 0000000_0 wrlvl_interval_ct_en(RW) 0000000_0 weight_round_robin_weight_sharing(RW) 0000000_0 weight_round_robin_latency_control 0000000_0(RW) rdlvl_req 0000000_0(WR) rdlvl_offset_dir_8(RW) |
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MC1_DDR3_CTL_750 : .dword 0x0000000101020101 |
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//000000_01 wrlvl_cs(RW) 000000_00 sw_leveling_mode(RW) 000000_00 rdlvl_cs(RW) 000000_01 axi2_w_priority(RW) 000000_01 axi2_r_priority(RW) 000000_10 axi2_port_ordering(RW) 000000_01 axi1_w_priority(RW) 000000_01 axi1_r_priority(RW) |
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MC1_DDR3_CTL_760 : .dword 0x0303030a00030002 |
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//0000_0011 axi0_priority2_relative_priority(RW) 0000_0011 axi0_priority1_relative_priority(RW) 0000_0011 axi0_priority0_relative_priority(RW) 0000_0000 address_mirroring(RW) 00000_000 tdfi_dram_clk_disable(RW) 00000_010 bstlen(RW) 000000_00 zq_req(WR) 000000_01 zq_on_sref_exit(RW) |
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MC1_DDR3_CTL_770 : .dword 0x0101010202020203 |
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//0000_0001 axi2_priority2_relative_priority(RW) 0000_0001 axi2_priority1_relative_priority(RW) 0000_0001 axi2_priority0_relative_priority(RW) 0000_0010 axi1_priority3_relative_priority(RW) 0000_0010 axi1_priority2_relative_priority(RW) 0000_0010 axi1_priority1_relative_priority(RW) 0000_0010 axi1_priority0_relative_priority(RW) 0000_0011 axi0_priority3_relative_priority(RW) |
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MC1_DDR3_CTL_780 : .dword 0x0102020400060c01 |
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//0000_0001 tdfi_dram_clk_enable(RW) 0000_0010 tdfi_ctrl_delay(RW) 0000_0010 rdlvl_gate_dq_zero_count(RW) 0000_0100 rdlvl_dq_zero_count(RW) 0000_0000 lowpower_refresh_enable(RW) 0000_0110 dram_class(RW) 0000_1100 burst_on_fly_bit(RW) 0000_0001 axi2_priority3_relative_priority(RW) |
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MC1_DDR3_CTL_790 : .dword 0x2819000000000f0f |
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//00_101000 wlmrd(RW) 00_011001 wldqsen(RW) 000_00000 lowpower_control(RW) 000_00000 lowpower_auto_enable(RW) 0000_1111 zqcs_chip(RD) 0000_0000 wrr_param_value_err(RD) 0000_0011 tdfi_wrlvl_dll(RW) 0000_0011 tdfi_rdlvl_dll(RW) |
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MC1_DDR3_CTL_7a0 : .dword 0x00000000000000ff |
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//_00000000 swlvl_resp_6(RW) _00000000 swlvl_resp_5(RW) _00000000 swlvl_resp_4 _00000000 swlvl_resp_3(RW) _00000000 swlvl_resp_2(RW) _00000000 swlvl_resp_1(RW) _00000000 swlvl_resp_0(RW) _00000000 dfi_wrlvl_max_delay(RW) |
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MC1_DDR3_CTL_7b0 : .dword 0x0000000000000000 |
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//_00000000 rdlvl_begin_delay_5(RW) _00000000 rdlvl_begin_delay_4(RW) _00000000 rdlvl_begin_delay_3(RW) _00000000 rdlvl_begin_delay_2(RW) _00000000 rdlvl_begin_delay_1(RW) _00000000 rdlvl_begin_delay_0(RW) _00000000 swlvl_resp_8(RW) _00000000 swlvl_resp_7(RW) |
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MC1_DDR3_CTL_7c0 : .dword 0x0000000000000000 |
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//_00000000 rdlvl_end_delay_4(RW) _00000000 rdlvl_end_delay_3(RW) _00000000 rdlvl_end_delay_2(RW) _00000000 rdlvl_end_delay_1(RW) _00000000 rdlvl_end_delay_0(RW) _00000000 rdlvl_begin_delay_8(RW) _00000000 rdlvl_begin_delay_7(RW) _00000000 rdlvl_begin_delay_6(RW) |
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MC1_DDR3_CTL_7d0 : .dword 0x0000000000000000 |
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//_00000000 rdlvl_gate_clk_adjust_3(RW) _00000000 rdlvl_gate_clk_adjust_2(RW) _00000000 rdlvl_gate_clk_adjust_1(RW) _00000000 rdlvl_gate_clk_adjust_0(RW) _00000000 rdlvl_end_delay_8(RW) _00000000 rdlvl_end_delay_7(RW) _00000000 rdlvl_end_delay_6(RW) 00000000 rdlvl_end_delay_5(RW) |
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MC1_DDR3_CTL_7e0 : .dword 0x0000000000000000 |
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//00000000 rdlvl_gate_delay_2(RD) 00000000 rdlvl_gate_delay_1(RD) 00000000 rdlvl_gate_delay_0(RD) 00000000 rdlvl_gate_clk_adjust_8(RW) 00000000 rdlvl_gate_clk_adjust_7(RW) 00000000 rdlvl_gate_clk_adjust_6(RW) 00000000 rdlvl_gate_clk_adjust_5(RW) 00000000 rdlvl_gate_clk_adjust_4(RW) |
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MC1_DDR3_CTL_7f0 : .dword 0x0000000000000000 |
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//11111111 rdlvl_max_delay(RW) 00001000 rdlvl_gate_max_delay(RW) 00000000 rdlvl_gate_delay_8(RW) 00000000 rdlvl_gate_delay_7(RW) 00000000 rdlvl_gate_delay_6(RW) 00000000 rdlvl_gate_delay_5(RW) 00000000 rdlvl_gate_delay_4(RW) 00000000 rdlvl_gate_delay_3(RW) |
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MC1_DDR3_CTL_800 : .dword 0x0000000000000000 |
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//00000000 rdlvl_midpoint_delay_7(RD) 00000000 rdlvl_midpoint_delay_6(RD) 00000000 rdlvl_midpoint_delay_5(RD) 00000000 rdlvl_midpoint_delay_4(RD) 00000000 rdlvl_midpoint_delay_3(RD) 00000000 rdlvl_midpoint_delay_2(RD) 00000000 rdlvl_midpoint_delay_1(RD) 00000000 rdlvl_midpoint_delay_0(RD) |
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MC1_DDR3_CTL_810 : .dword 0x0000000000000000 |
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//00000000 rdlvl_offset_delay_6(RW) 00000000 rdlvl_offset_delay_5(RW) 00000000 rdlvl_offset_delay_4(RW) 00000000 rdlvl_offset_delay_3(RW) 00000000 rdlvl_offset_delay_2(RW) 00000000 rdlvl_offset_delay_1(RW) 00000000 rdlvl_offset_delay_0(RW) 00000000 rdlvl_midpoint_delay_8(RD) |
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MC1_DDR3_CTL_820 : .dword 0xee0000ee00400000 |
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//00000100 tdfi_wrlvl_resplat(RW) 00000000 tdfi_wrlvl_resp(RD) 00000000 tdfi_rdlvl_rr(RW) 00001100 tdfi_rdlvl_resplat(RW) 00000000 tdfi_rdlvl_resp(RD) 01000000 refresh_per_zq(RW) 00000000 rdlvl_offset_delay_8(RW) 00000000 rdlvl_offset_delay_7(RW) |
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MC1_DDR3_CTL_830 : .dword 0x0000000000000c00 |
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//00000000 wrlvl_delay_5(RD) 00000000 wrlvl_delay_4(RD) 00000000 wrlvl_delay_3(RD) 00000000 wrlvl_delay_2(RD) 00000000 wrlvl_delay_1(RD) 00000000 wrlvl_delay_0(RD) 00000010 tmod(RW) 00000000 tdfi_wrlvl_ww(RD) |
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MC1_DDR3_CTL_840 : .dword 0x0000640064000000 |
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//00000000000000_0001100100 axi1_priority_relax(RW) 000000_0001100100 axi0_priority_relax(RW) 00000000 wrlvl_delay_8(RD) 00000000 wrlvl_delay_7(RD) 00000000 wrlvl_delay_6(RD) |
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MC1_DDR3_CTL_850 : .dword 0x0000000000000064 |
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//000000_0000000000 out_of_range_source_id(RD) 000000_0000000000 ecc_u_id(RD) 000000_0000000000 ecc_c_id(RD) 000000_0000000000 axi2_priority_relax(RW) |
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MC1_DDR3_CTL_860 : .dword 0x0200004000000000 |
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//0000_000000000000 zqini(RW) 0000_000000000000 zqcs(RW) 000000_0000000000 port_data_error_id(RD) 000000_0000000000 port_cmd_error_id(RD) |
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MC1_DDR3_CTL_870 : .dword 0x0000000000000000 |
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//0_000000000000010 emrs1_data_3(RD) 0_000000000000010 emrs1_data_2(RD) 0_000000000000010 emrs1_data_1(RD) 0_000000000000010 emrs1_data_0(RD) |
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MC1_DDR3_CTL_880 : .dword 0x0000000000000000 |
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//0_000000000000010 emrs3_data_3(RW) 0_000000000000010 emrs3_data_2(RW) 0_000000000000010 emrs3_data_1(RW) 0_000000000000010 emrs3_data_0(RW) |
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MC1_DDR3_CTL_890 : .dword 0x0000000000000000 |
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//0_000010000010000 mrs_data_3(RD) 0_000010000010000 mrs_data_2(RD) 0_000010000010000 mrs_data_1(RD) 0_000010000010000 mrs_data_0(RD) |
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MC1_DDR3_CTL_8a0 : .dword 0x00000000001c001c |
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//hXXXX lowpower_internal_cnt(RW) hXXXX lowpower_external_cnt(RW) hXXXX axi2_en_size_lt_width_instr(RW) hXXXX axi1_en_size_lt_width_instr(RW) |
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MC1_DDR3_CTL_8b0 : .dword 0x0000000000000000 |
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//hXXXX refresh_per_rdlvl(RW) hXXXX lowpower_self_refresh_cnt(RW) hXXXX lowpower_refresh_hold(RW) hXXXX lowpower_power_down_cnt(RW) |
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MC1_DDR3_CTL_8c0 : .dword 0x0000000000000000 |
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//hXXXX wrlvl_interval(RW) hXXXX tdfi_wrlvl_max(RW) hXXXX tdfi_rdlvl_max(RW) hXXXX refresh_per_rdlvl_gate(RW) |
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MC1_DDR3_CTL_8d0 : .dword 0x0000030d40000000 |
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//h00_XXXXXXXX cke_inactive(RW) 000000_000000000000000000 wrlvl_status(RD) |
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MC1_DDR3_CTL_8e0 : .dword 0x0000000023c34600 |
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//h00000000_XXXXXXXX trst_pwron(RW) |
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MC1_DDR3_CTL_8f0 : .dword 0x0000000010101080 |
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//hXXXXXXX 000_0 XXXXXXXX dll_ctrl_reg_2(RW) |
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MC1_DDR3_CTL_900 : .dword 0x0000000000000000 |
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//h000000 00_00 X XXXXXXXX rdlvl_error_status(RW) |
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MC1_DDR3_CTL_910 : .dword 0x0000000000000000 |
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//hXXXXXXXX XXXXXXXX rdlvl_gate_resp_mask[63:0](RW) |
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MC1_DDR3_CTL_920 : .dword 0x0000000000000000 |
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//h00000000000000_XX rdlvl_gate_resp_mask[71:64](RW) |
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MC1_DDR3_CTL_930 : .dword 0x0000000000000000 |
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//hXXXXXXXX XXXXXXXX rdlvl_resp_mask[63:0](RW) |
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MC1_DDR3_CTL_940 : .dword 0xff07070000060600 |
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//0000_0000 tdfi_rdlvl_en(RW) 00000_000 w2r_samecs_delay(RW) 00000_000 w2r_diffcs_delay(RW) 00000_000 lvl_status(RD) 0000000_0 rdlvl_edge(RW) 0000_0000 cksrx(RW) 0000_0000 cksre(RW) _00000000 rdlvl_resp_mask[71:64](RW) |
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MC1_DDR3_CTL_950 : .dword 0x0000000000000d00 |
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//hXXXXX 00_00 XXXX mask_int[17:0](RW) hXXXX txpdll(RW) 0000_0000 tdfi_wrlvl_en(RW) |
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MC1_DDR3_CTL_960 : .dword 0x0705000000000000 |
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//000_00101 rdlat_adj(RW) 0000_0100 wrlat_adj(RW) 0000000_0 swlvl_start(WR) 0000000_0 swlvl_load(WR) 0000000_0 swlvl_exit(WR) 000000_000000000000000000 int_status(RD) |
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MC1_DDR3_CTL_970 : .dword 0x010000000003e825 |
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//h00000 000_0 concurrentap_wr_only XXXX int_ack[16:0](WR) hXXXX dll_rst_delay(RW) hXX dll_rst_adj_dly(RW) |
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MC1_DDR3_CTL_980 : .dword 0x0001010001000101 |
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//0000000_0 zq_in_progress(RD) 0000000_1 zqcs_rotate(RW) 0000000_0 wrlvl_reg_en(RW) 0000000_0 wrlvl_en(RW) 0000000_1 resync_dll_per_aref_en(RW) 0000000_0 resync_dll(WR) 0000000_0 rdlvl_reg_en(RW) 0000000_0 rdlvl_gate_reg_en(RW) |
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MC1_DDR3_CTL_990 : .dword 0x0707040707070700 |
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//00000_000 w2w_samecs_dly(RW) 00000_001 w2w_diffcs_dly(RW) 00000_010 tbst_int_interval(RW) 00000_010 r2w_samecs_dly(RW) 00000_010 r2w_diffcs_dly(RW) 00000_000 r2r_samecs_dly(RW) 00000_001 r2r_diffcs_dly(RW) 00000_000 axi_aligned_strobe_disable(RW) |
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MC1_DDR3_CTL_9a0 : .dword 0x0707040804080404 |
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//00000111 tdfi_wrlvl_load(RW) 00000111 tdfi_rdlvl_load(RW) 000_00011 tckesr(RW) 000_00010 tccd(RW) 000_00000 add_odt_clk_difftype_diffcs(RW) 0000_0110 trp_ab(RW) 0000_0001 add_odt_clk_sametype_diffcs(RW) 0000_0000 add_odt_clk_difftype_samecs(RW) |
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MC1_DDR3_CTL_9b0 : .dword 0x02000100000a000f |
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//0000_001000000000 zqinit(RW) 0000_000100000000 zqcl(RW) 000000_0000001010 tdfi_wrlvl_ww(RW) 000000_0000001111 tdfi_rdlvl_rr(RW) |
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MC1_DDR3_CTL_9c0 : .dword 0x04200c2d0c2d0c2d |
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//0_000101001010010 mr0_data_0(RW) 00_00110000101101 tdfi_phyupd_type3(RW) 00_00110000101101 tdfi_phyupd_type2(RW) 00_00110000101101 tdfi_phyupd_type1(RW) |
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MC1_DDR3_CTL_9d0 : .dword 0x0044042004200420 |
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//0_000000000000100 mr1_data_0(RW) 0_000101001010010 mr0_data_3(RW) 0_000101001010010 mr0_data_2(RW) 0_000101001010010 mr0_data_1(RW) |
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MC1_DDR3_CTL_9e0 : .dword 0x0000004400440044 |
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//0_000000000000000 mr2_data_0(RW) 0_000000000000100 mr1_data_3(RW) 0_000000000000100 mr1_data_2(RW) 0_000000000000100 mr1_data_1(RW) |
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MC1_DDR3_CTL_9f0 : .dword 0x0000000000000000 |
|||
//0_000000000000000 mr3_data_0(RW) 0_000000000000000 mr2_data_3(RW) 0_000000000000000 mr2_data_2(RW) 0_000000000000000 mr2_data_1(RW) |
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MC1_DDR3_CTL_a00 : .dword 0x007f000000000000 |
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//0000000011111111 dfi_wrlvl_max_delay(RW) 0_000000000000000 mr3_data_3(RW) 0_000000000000000 mr3_data_2(RW) 0_000000000000000 mr3_data_1(RW) |
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MC1_DDR3_CTL_a10 : .dword 0x0000000000000000 |
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//0000000000000000 rdlvl_begin_delay_3(RD) 0000000000000000 rdlvl_begin_delay_2(RD) 0000000000000000 rdlvl_begin_delay_1(RD) 0000000000000000 rdlvl_begin_delay_0(RD) |
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MC1_DDR3_CTL_a20 : .dword 0x0000000000000000 |
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//0000000000000000 rdlvl_begin_delay_7(RD) 0000000000000000 rdlvl_begin_delay_6(RD) 0000000000000000 rdlvl_begin_delay_5(RD) 0000000000000000 rdlvl_begin_delay_4(RD) |
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MC1_DDR3_CTL_a30 : .dword 0x0020002000200000 |
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//0000111000001110 rdlvl_delay_2(RW) 0000111000001110 rdlvl_delay_1(RW) 0000111000001110 rdlvl_delay_0(RW) 0000000000000000 rdlvl_begin_delay_8(RD) |
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MC1_DDR3_CTL_a40 : .dword 0x0020002000200020 |
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//0000111000001110 rdlvl_delay_6(RW) 0000111000001110 rdlvl_delay_5(RW) 0000111000001110 rdlvl_delay_4(RW) 0000111000001110 rdlvl_delay_3(RW) |
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MC1_DDR3_CTL_a50 : .dword 0x0000000000200020 |
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//0000000000000000 rdlvl_end_delay_1(RD) 0000000000000000 rdlvl_end_delay_0(RD) 0000111000001110 rdlvl_delay_8(RW) 0000111000001110 rdlvl_delay_7(RW) |
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MC1_DDR3_CTL_a60 : .dword 0x0000000000000000 |
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//0000000000000000 rdlvl_end_delay_5(RD) 0000000000000000 rdlvl_end_delay_4(RD) 0000000000000000 rdlvl_end_delay_3(RD) 0000000000000000 rdlvl_end_delay_2(RD) |
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MC1_DDR3_CTL_a70 : .dword 0x0019000000000000 |
|||
//0000000000000000 rdlvl_gate_delay_0(RW+) 0000000000000000 rdlvl_end_delay_8(RD) 0000000000000000 rdlvl_end_delay_7(RD) 0000000000000000 rdlvl_end_delay_6(RD) |
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MC1_DDR3_CTL_a80 : .dword 0x0019001900190019 |
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//0000000000000000 rdlvl_gate_delay_4(RW+) 0000000000000000 rdlvl_gate_delay_3(RW+) 0000000000000000 rdlvl_gate_delay_2(RW+) 0000000000000000 rdlvl_gate_delay_1(RW+) |
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MC1_DDR3_CTL_a90 : .dword 0x0019001900190019 |
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//0000000000000000 rdlvl_gate_delay_8(RW+) 0000000000000000 rdlvl_gate_delay_7(RW+) 0000000000000000 rdlvl_gate_delay_6(RW+) 0000000000000000 rdlvl_gate_delay_5(RW+) |
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MC1_DDR3_CTL_aa0 : .dword 0x0000ffff00000022 |
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//0000000000000000 rdlvl_midpoint_delay_0(RD) 1111111111111111 rdlvl_max_delay(RW) 0000000000000000 rdlvl_gate_refresh_interval(RW) 0000000000010000 rdlvl_gate_max_delay(RW) |
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MC1_DDR3_CTL_ab0 : .dword 0x0000000000000000 |
|||
//0000000000000000 rdlvl_midpoint_delay_4(RD) 0000000000000000 rdlvl_midpoint_delay_3(RD) 0000000000000000 rdlvl_midpoint_delay_2(RD) 0000000000000000 rdlvl_midpoint_delay_1(RD) |
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MC1_DDR3_CTL_ac0 : .dword 0x0000000000000000 |
|||
//0000000000000000 rdlvl_midpoint_delay_8(RD) 0000000000000000 rdlvl_midpoint_delay_7(RD) 0000000000000000 rdlvl_midpoint_delay_6(RD) 0000000000000000 rdlvl_midpoint_delay_5(RD) |
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MC1_DDR3_CTL_ad0 : .dword 0x0000000000000000 |
|||
//0000000000000000 rdlvl_offset_delay_3(RW) 0000000000000000 rdlvl_offset_delay_2(RW) 0000000000000000 rdlvl_offset_delay_1(RW) 0000000000000000 rdlvl_offset_delay_0(RW) |
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MC1_DDR3_CTL_ae0 : .dword 0x0000000000000000 |
|||
//0000000000000000 rdlvl_offset_delay_7(RW) 0000000000000000 rdlvl_offset_delay_6(RW) 0000000000000000 rdlvl_offset_delay_5(RW) 0000000000000000 rdlvl_offset_delay_4(RW) |
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MC1_DDR3_CTL_af0 : .dword 0x0020001800000000 |
|||
//0000000000000000 wrlvl_delay_1(RW+) 0000000000000000 wrlvl_delay_0(RW+) 0000000000000000 rdlvl_refresh_interval(RW) 0000000000000000 rdlvl_offset_delay_8(RW) |
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MC1_DDR3_CTL_b00 : .dword 0x0042003c00300028 |
|||
//0000000000000000 wrlvl_delay_5(RW+) 0000000000000000 wrlvl_delay_4(RW+) 0000000000000000 wrlvl_delay_3(RW+) 0000000000000000 wrlvl_delay_2(RW+) |
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MC1_DDR3_CTL_b10 : .dword 0x00000028004e0048 |
|||
//0000000000000000 wrlvl_refresh_interval(RW) 0000000000000000 wrlvl_delay_8(RW+) 0000000000000000 wrlvl_delay_7(RW+) 0000000000000000 wrlvl_delay_6(RW+) |
|||
MC1_DDR3_CTL_b20 : .dword 0x00000c2d00000c2d |
|||
//00000000000000000000110000101101 tdfi_rdlvl_resp(RW) 00000000000000000000110000101101 tdfi_rdlvl_max(RW) |
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MC1_DDR3_CTL_b30 : .dword 0x00000c2d00000c2d |
|||
//00000000000000000000110000101101 tdfi_wrlvl_resp(RW) 00000000000000000000000000000000 tdfi_wrlvl_max(RW) |
|||
#endif |
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|
|||
//param for RDIMM-------------------------------- |
|||
ddr3_RDIMM_reg_data: |
|||
ddr3_RDIMM_reg_data_mc1: |
|||
#ifdef DDR3_DIMM |
|||
MC0_DDR3_RDIMM_CTL_000 : .dword 0x0000010000000100 |
|||
//000000000000000_0 concurrentap(RW) 0000000_1 bank_split_en(RW) 0000000_0 auto_refresh_mode(RW) 0000000_0 arefresh(WR) 0000000_0 ap(RW) 0000000_1 addr_cmp_en(RW) 0000000_1 active_aging(RW) |
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MC0_DDR3_RDIMM_CTL_010 : .dword 0x0000000100010000 |
|||
//0000000_0 fwc(WR) 0000000_0 fast_write(RW) 0000000_1 enable_quick_srefresh(RW) 0000000_1 eight_bank_mode(RW) 0000000_0 ecc_disable_w_uc_err(RW) 0000000_1 dqs_n_en(RW) 0000000_0 dll_bypass_mode(RW) 0000000_0 dlllockreg(RD) |
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MC0_DDR3_RDIMM_CTL_020 : .dword 0x0100010000000000 |
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//0000000_1 priority_en(RW) 0000000_0 power_down(RW) 0000000_1 placement_en(RW) 0000000_0 odt_add_turn_clk_en(RD) 0000000_0 no_cmd_init(RW) 0000000_0 intrptwritea(RW) 0000000_0 intrptreada(RW) 0000000_0 intrptapburst(RW) |
|||
MC0_DDR3_RDIMM_CTL_030 : .dword 0x0001000001010000 |
|||
//0000000_1 swap_port_rw_same_en(RW) 0000000_1 swap_en(RW) 0000000_0 start(RW) 0000000_0 srefresh(RW+) 0000000_1 rw_same_en(RW) 0000000_0 reg_dimm_enable(RW) 0000000_0 reduc(RW) 0000000_0 pwrup_srefresh_exit(RW) |
|||
MC0_DDR3_RDIMM_CTL_040 : .dword 0x0002010100000101 |
|||
//000000_00 rtt_0(RD) 000000_11 ctrl_raw(RW) 000000_01 axi0_w_priority(RW) 000000_01 axi0_r_priority(RW) 0000000_0 write_modereg(WR) 0000000_1 writeinterp(RW) 0000000_1 tref_enable(RW) 0000000_1 tras_lockout(RW) |
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MC0_DDR3_RDIMM_CTL_050 : .dword 0x0700000004060100 |
|||
//00000_000 q_fullness(RW) 00000_000 port_data_error_type(RD) 000_00000 out_of_range_type(RD) 00000_000 max_cs_reg(RD) 00000_100 column_size(RW) 0000_0101 caslat(RW) 00000_010 addr_pins(RW) 00000000 |
|||
MC0_DDR3_RDIMM_CTL_060 : .dword 0x0a05050805050003 |
|||
//0000_1010 aprebit(RW) 0000_0101 wrlat(RW) 0000_0100 twtr(RW) 000_00110 twr_int(RW) 00000_011 trtp(RW) 00000_100 trrd(RW) 0000000000000_011 tcke(RW) |
|||
MC0_DDR3_RDIMM_CTL_070 : .dword 0x0000000000030c0c |
|||
//0000_1111 max_row_reg(RD) 0000_1110 max_col_reg(RD) 0000_0000 initaref(RW) 00000000000000000000_1111 cs_map(RW) 000_01010 caslat_lin_gate(RW) 000_01010 caslat_lin(RW) |
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MC0_DDR3_RDIMM_CTL_080 : .dword 0x0804020100000000 |
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//0000_0001 odt_wr_map_cs3(RW) 0000_0010 odt_wr_map_cs2(RW) 0000_0100 odt_wr_map_cs1(RW) 0000_1000 odt_wr_map_cs0(RW) 0000_0001 odt_rd_map_cs3(RW) 0000_0010 odt_rd_map_cs2(RW) 0000_0100 odt_rd_map_cs1(RW) 0000_1000 odt_rd_map_cs0(RW) |
|||
MC0_DDR3_RDIMM_CTL_090 : .dword 0x0000070f00000000 |
|||
//000_00000 ocd_adjust_pup_cs_0(RW) 000_00000 ocd_adjust_pdn_cs_0(RW) 0000_0101 trp(RW) 000_01011 tdal(RW) 000000000000_0000 port_cmd_error_type(RD) 0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_0a0 : .dword 0x0000001f3f140412 |
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//00000000000000000000000000_111111 command_age_count(RW) 00_111111 age_count(RW) 000_10100 trc(RW) 000_00110 tmrd(RW) 000_10010 tfaw(RW) |
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MC0_DDR3_RDIMM_CTL_0b0 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_0c0 : .dword 0x000040060f000000 |
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//000000000000000000101100 trfc(RW) 00000101 trcd_int(RW) 00001111 tras_min(RW) 00000000 out_of_range_length(RD) 00000000 ecc_u_synd(RD) 00000000 ecc_c_synd(RD) |
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MC0_DDR3_RDIMM_CTL_0d0 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_0e0 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_0f0 : .dword 0x0000000000000000 |
|||
//Bit 21:16 dll_lock(RD) |
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MC0_DDR3_RDIMM_CTL_100 : .dword 0x0000000000000000 |
|||
//MC0_DDR3_RDIMM_CTL_110 : .dword 0x00000000000005e0 #200M+ |
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MC0_DDR3_RDIMM_CTL_110 : .dword 0x0000000000000900 #300M+ |
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//MC0_DDR3_RDIMM_CTL_110 : .dword 0x0000000000000c00 #400M+ |
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//0_000000000000000 emrs2_data_1(RW) 0_000000000000000 emrs2_data_0(RW) 000000000000000000_00110000101101 tref(RW) |
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MC0_DDR3_RDIMM_CTL_120 : .dword 0x001c000000000000 |
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//0000000000011100 axi0_en_size_lt_width_instr(RW) hXXXX 0_000000000000000 emrs2_data_3(RW) 0_000000000000000 emrs2_data_2(RW) |
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//MC0_DDR3_RDIMM_CTL_130 : .dword 0x36800003020000c8 #200M+ |
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MC0_DDR3_RDIMM_CTL_130 : .dword 0x52100003020000c8 #300M--400M |
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//MC0_DDR3_RDIMM_CTL_130 : .dword 0x6d800004020010b #400M--533M |
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//0110110101010110 tras_max(RW) 0000000000000011 tpdex(RW) 0000001000000000 tdll(RW) 0000000000000000 tcpd(RW) |
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MC0_DDR3_RDIMM_CTL_140 : .dword 0x0000000002000044 |
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//0000000000000000 xor_check_bits(RW) 0000000000000000 version(RD) 0000001000000000 txsr(RW) 0000000000110000 txsnr(RW) |
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MC0_DDR3_RDIMM_CTL_150 : .dword 0x0000000000000100 |
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//000_0000000000000000000000000000000000000 ecc_c_addr(RD) hXXXXXX tinit(RW) |
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MC0_DDR3_RDIMM_CTL_160 : .dword 0x0000000000000000 |
|||
//000000000000000000000000000_0000000000000000000000000000000000000 ecc_u_addr(RD) |
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MC0_DDR3_RDIMM_CTL_170 : .dword 0x0000000000000000 |
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//000000000000000000000000000_0000000000000000000000000000000000000 out_of_range_addr(RD) |
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MC0_DDR3_RDIMM_CTL_180 : .dword 0x0000000000000000 |
|||
//000000000000000000000000000_0000000000000000000000000000000000000 port_cmd_error_addr(RD) |
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MC0_DDR3_RDIMM_CTL_190 : .dword 0x0000000000000000 |
|||
//0000000000000000000000000000000000000000000000000000000000000000 ecc_c_data(RD) |
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MC0_DDR3_RDIMM_CTL_1a0 : .dword 0x0000000000000000 |
|||
//0000000000000000000000000000000000000000000000000000000000000000 ecc_u_data(RD) |
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MC0_DDR3_RDIMM_CTL_1b0 : .dword 0x0000000000000007 |
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//0000000000000000000000000000000000000000000000000000000000000_000 cke_delay(RW) |
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MC0_DDR3_RDIMM_CTL_1c0 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_1d0 : .dword 0x02000b0000000001 |
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//0000_0010 tdfi_phy_wrlat_base(RW) 0000_0000 tdfi_phy_wrlat(RD) 000_00111 tdfi_phy_rdlat(RW) 0000_0100 tdfi_ctrlupd_min(RD) 000000000000_0000 dram_clk_disable(RW) 0000000_1 odt_alt_en(RW) 0000000_1 drive_dq_dqs(RW) |
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MC0_DDR3_RDIMM_CTL_1e0 : .dword 0x0000000000000200 |
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//00_00000000000000 tdfi_phyupd_type0(RD) 00_00000000000000 tdfi_phyupd_resp(RD) 00_00000000000000 tdfi_ctrlupd_max(RD) 000_00000 tdfi_rddata_en_base(RW) 000_00000 tdfi_rddata_en(RD) |
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|
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//hXXXXXXXX dll_ctrl_reg_0_0(RW) h000000 hXX dft_ctrl_reg(RW) |
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MC0_DDR3_RDIMM_CTL_1f0 : .dword 0x0020008000000000 |
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MC0_DDR3_RDIMM_CTL_200 : .dword 0x0020008000200080 |
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MC0_DDR3_RDIMM_CTL_210 : .dword 0x0020008000200080 |
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MC0_DDR3_RDIMM_CTL_220 : .dword 0x0020008000200080 |
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MC0_DDR3_RDIMM_CTL_230 : .dword 0x0020008000200080 |
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MC0_DDR3_RDIMM_CTL_240 : .dword 0x0000200000002000 |
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MC0_DDR3_RDIMM_CTL_250 : .dword 0x0000200000002000 |
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MC0_DDR3_RDIMM_CTL_260 : .dword 0x0000200000002000 |
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MC0_DDR3_RDIMM_CTL_270 : .dword 0x0000200000002000 |
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MC0_DDR3_RDIMM_CTL_280 : .dword 0x0000000000002000 |
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//hXXXXXXX 00_00 dll_obs_reg_0_0(RW) 00000000000000000000111000000000 dll_ctrl_reg_1_8(RW) |
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|
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MC0_DDR3_RDIMM_CTL_290 : .dword 0x0000000000000000 |
|||
//hXXXXXXX 00_00 dll_obs_reg_0_2(RW) hXXXXXXX 00_00 dll_obs_reg_0_1(RW) |
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MC0_DDR3_RDIMM_CTL_2a0 : .dword 0x0000000000000000 |
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//hXXXXXXX 00_00 dll_obs_reg_0_4(RW) hXXXXXXX 00_00 dll_obs_reg_0_3(RW) |
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MC0_DDR3_RDIMM_CTL_2b0 : .dword 0x0000000000000000 |
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//hXXXXXXX 00_00 dll_obs_reg_0_6(RW) hXXXXXXX 00_00 dll_obs_reg_0_5(RW) |
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MC0_DDR3_RDIMM_CTL_2c0 : .dword 0x0000000000000000 |
|||
//hXXXXXXX 00_00 dll_obs_reg_0_8(RW) hXXXXXXX 00_00 dll_obs_reg_0_7(RW) |
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//11110100000000000011101100100111 phy_ctrl_reg_0_0(RD) 000000_00000000000000000110011101 pad_ctrl_reg_0(RW) |
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MC0_DDR3_RDIMM_CTL_2d0 : .dword 0x04003733003c09b5 |
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MC0_DDR3_RDIMM_CTL_2e0 : .dword 0x0400373304003733 |
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MC0_DDR3_RDIMM_CTL_2f0 : .dword 0x0400373304003733 |
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MC0_DDR3_RDIMM_CTL_300 : .dword 0x0400373304003733 |
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MC0_DDR3_RDIMM_CTL_310 : .dword 0x0400373304003733 |
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MC0_DDR3_RDIMM_CTL_320 : .dword 0x26c0000126c00001 |
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MC0_DDR3_RDIMM_CTL_330 : .dword 0x26c0000126c00001 |
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MC0_DDR3_RDIMM_CTL_340 : .dword 0x26c0000126c00001 |
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MC0_DDR3_RDIMM_CTL_350 : .dword 0x26c0000126c00001 |
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MC0_DDR3_RDIMM_CTL_360 : .dword 0x0000c10026c00001 |
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//00000000000000001100000000000101 phy_ctrl_reg_2(RW) 00000111110000000000001100000001 phy_ctrl_reg_1_8(RW) |
|||
//-------------- |
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MC0_DDR3_RDIMM_CTL_370 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_380 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_390 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_3a0 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_3b0 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_3c0 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_3d0 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_3e0 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_3f0 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_400 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_410 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_420 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_430 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_440 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_450 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_460 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_470 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_480 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_490 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_4a0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_4b0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_4c0 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_4d0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_4e0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_4f0 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_500 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_510 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_520 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_530 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_540 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_550 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_560 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_570 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_580 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_590 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_5a0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_5b0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_5c0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_5d0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_5e0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_5f0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_600 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_610 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_620 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_630 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_640 : .dword 0x0000000000000000 |
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MC0_DDR3_RDIMM_CTL_650 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_660 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_670 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_680 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_690 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_6a0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_6b0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_6c0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_6d0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_6e0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_6f0 : .dword 0x0000000000000000 |
|||
MC0_DDR3_RDIMM_CTL_700 : .dword 0x0000000000000000 |
|||
//------------- |
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MC0_DDR3_RDIMM_CTL_710 : .dword 0x0000000000000000 |
|||
//bit 48 en_wr_leveling(RD)(replaced by wrlvl_en in LS3A3) |
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MC0_DDR3_RDIMM_CTL_720 : .dword 0x0000000000000000 |
|||
//0000000_0 rdlvl_gate_req(WR) 0000000_0 rdlvl_gate_preamble_check_en(RW) 0000000_0 rdlvl_gate_en(RW) 0000000_0 rdlvl_en(RW) 0000000_0 rdlvl_begin_delay_en(RW) 00000000 0000000_0 swlvl_op_done(RD) 00000000 |
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MC0_DDR3_RDIMM_CTL_730 : .dword 0x0000000000000000 |
|||
//0000000_0 rdlvl_offset_dir_7(RW) 0000000_0 rdlvl_offset_dir_6(RW) 0000000_0 rdlvl_offset_dir_5(RW)0000000_0 rdlvl_offset_dir_4(RW) 0000000_0 rdlvl_offset_dir_3(RW) 0000000_0 rdlvl_offset_dir_2(RW) 0000000_0 rdlvl_offset_dir_1(RW) 0000000_0 rdlvl_offset_dir_0(RW) |
|||
MC0_DDR3_RDIMM_CTL_740 : .dword 0x0100000000000000 |
|||
//000000_00 axi1_port_ordering(RW) 000000_00 axi0_port_ordering(RW) 0000000_0 wrlvl_req(WR) 0000000_0 wrlvl_interval_ct_en(RW) 0000000_0 weight_round_robin_weight_sharing(RW) 0000000_0 weight_round_robin_latency_control 0000000_0(RW) rdlvl_req 0000000_0(WR) rdlvl_offset_dir_8(RW) |
|||
MC0_DDR3_RDIMM_CTL_750 : .dword 0x0000000101020101 |
|||
//000000_01 wrlvl_cs(RW) 000000_00 sw_leveling_mode(RW) 000000_00 rdlvl_cs(RW) 000000_01 axi2_w_priority(RW) 000000_01 axi2_r_priority(RW) 000000_10 axi2_port_ordering(RW) 000000_01 axi1_w_priority(RW) 000000_01 axi1_r_priority(RW) |
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MC0_DDR3_RDIMM_CTL_760 : .dword 0x0303030000030002 |
|||
//0000_0011 axi0_priority2_relative_priority(RW) 0000_0011 axi0_priority1_relative_priority(RW) 0000_0011 axi0_priority0_relative_priority(RW) 0000_0000 address_mirroring(RW) 00000_000 tdfi_dram_clk_disable(RW) 00000_010 bstlen(RW) 000000_00 zq_req(WR) 000000_01 zq_on_sref_exit(RW) |
|||
MC0_DDR3_RDIMM_CTL_770 : .dword 0x0101010202020203 |
|||
//0000_0001 axi2_priority2_relative_priority(RW) 0000_0001 axi2_priority1_relative_priority(RW) 0000_0001 axi2_priority0_relative_priority(RW) 0000_0010 axi1_priority3_relative_priority(RW) 0000_0010 axi1_priority2_relative_priority(RW) 0000_0010 axi1_priority1_relative_priority(RW) 0000_0010 axi1_priority0_relative_priority(RW) 0000_0011 axi0_priority3_relative_priority(RW) |
|||
MC0_DDR3_RDIMM_CTL_780 : .dword 0x0102020400060c01 |
|||
//0000_0001 tdfi_dram_clk_enable(RW) 0000_0010 tdfi_ctrl_delay(RW) 0000_0010 rdlvl_gate_dq_zero_count(RW) 0000_0100 rdlvl_dq_zero_count(RW) 0000_0000 lowpower_refresh_enable(RW) 0000_0110 dram_class(RW) 0000_1100 burst_on_fly_bit(RW) 0000_0001 axi2_priority3_relative_priority(RW) |
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MC0_DDR3_RDIMM_CTL_790 : .dword 0x2819000000000f0f |
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//00_101000 wlmrd(RW) 00_011001 wldqsen(RW) 000_00000 lowpower_control(RW) 000_00000 lowpower_auto_enable(RW) 0000_1111 zqcs_chip(RD) 0000_0000 wrr_param_value_err(RD) 0000_0011 tdfi_wrlvl_dll(RW) 0000_0011 tdfi_rdlvl_dll(RW) |
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MC0_DDR3_RDIMM_CTL_7a0 : .dword 0x00000000000000ff |
|||
//_00000000 swlvl_resp_6(RW) _00000000 swlvl_resp_5(RW) _00000000 swlvl_resp_4 _00000000 swlvl_resp_3(RW) _00000000 swlvl_resp_2(RW) _00000000 swlvl_resp_1(RW) _00000000 swlvl_resp_0(RW) _00000000 dfi_wrlvl_max_delay(RW) |
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MC0_DDR3_RDIMM_CTL_7b0 : .dword 0x0000000000000000 |
|||
//_00000000 rdlvl_begin_delay_5(RW) _00000000 rdlvl_begin_delay_4(RW) _00000000 rdlvl_begin_delay_3(RW) _00000000 rdlvl_begin_delay_2(RW) _00000000 rdlvl_begin_delay_1(RW) _00000000 rdlvl_begin_delay_0(RW) _00000000 swlvl_resp_8(RW) _00000000 swlvl_resp_7(RW) |
|||
MC0_DDR3_RDIMM_CTL_7c0 : .dword 0x0000000000000000 |
|||
//_00000000 rdlvl_end_delay_4(RW) _00000000 rdlvl_end_delay_3(RW) _00000000 rdlvl_end_delay_2(RW) _00000000 rdlvl_end_delay_1(RW) _00000000 rdlvl_end_delay_0(RW) _00000000 rdlvl_begin_delay_8(RW) _00000000 rdlvl_begin_delay_7(RW) _00000000 rdlvl_begin_delay_6(RW) |
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MC0_DDR3_RDIMM_CTL_7d0 : .dword 0x0000000000000000 |
|||
//_00000000 rdlvl_gate_clk_adjust_3(RW) _00000000 rdlvl_gate_clk_adjust_2(RW) _00000000 rdlvl_gate_clk_adjust_1(RW) _00000000 rdlvl_gate_clk_adjust_0(RW) _00000000 rdlvl_end_delay_8(RW) _00000000 rdlvl_end_delay_7(RW) _00000000 rdlvl_end_delay_6(RW) 00000000 rdlvl_end_delay_5(RW) |
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MC0_DDR3_RDIMM_CTL_7e0 : .dword 0x0000000000000000 |
|||
//00000000 rdlvl_gate_delay_2(RD) 00000000 rdlvl_gate_delay_1(RD) 00000000 rdlvl_gate_delay_0(RD) 00000000 rdlvl_gate_clk_adjust_8(RW) 00000000 rdlvl_gate_clk_adjust_7(RW) 00000000 rdlvl_gate_clk_adjust_6(RW) 00000000 rdlvl_gate_clk_adjust_5(RW) 00000000 rdlvl_gate_clk_adjust_4(RW) |
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MC0_DDR3_RDIMM_CTL_7f0 : .dword 0x0000000000000000 |
|||
//11111111 rdlvl_max_delay(RW) 00001000 rdlvl_gate_max_delay(RW) 00000000 rdlvl_gate_delay_8(RW) 00000000 rdlvl_gate_delay_7(RW) 00000000 rdlvl_gate_delay_6(RW) 00000000 rdlvl_gate_delay_5(RW) 00000000 rdlvl_gate_delay_4(RW) 00000000 rdlvl_gate_delay_3(RW) |
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MC0_DDR3_RDIMM_CTL_800 : .dword 0x0000000000000000 |
|||
//00000000 rdlvl_midpoint_delay_7(RD) 00000000 rdlvl_midpoint_delay_6(RD) 00000000 rdlvl_midpoint_delay_5(RD) 00000000 rdlvl_midpoint_delay_4(RD) 00000000 rdlvl_midpoint_delay_3(RD) 00000000 rdlvl_midpoint_delay_2(RD) 00000000 rdlvl_midpoint_delay_1(RD) 00000000 rdlvl_midpoint_delay_0(RD) |
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MC0_DDR3_RDIMM_CTL_810 : .dword 0x0000000000000000 |
|||
//00000000 rdlvl_offset_delay_6(RW) 00000000 rdlvl_offset_delay_5(RW) 00000000 rdlvl_offset_delay_4(RW) 00000000 rdlvl_offset_delay_3(RW) 00000000 rdlvl_offset_delay_2(RW) 00000000 rdlvl_offset_delay_1(RW) 00000000 rdlvl_offset_delay_0(RW) 00000000 rdlvl_midpoint_delay_8(RD) |
|||
MC0_DDR3_RDIMM_CTL_820 : .dword 0xee0000ee00400000 |
|||
//00000100 tdfi_wrlvl_resplat(RW) 00000000 tdfi_wrlvl_resp(RD) 00000000 tdfi_rdlvl_rr(RW) 00001100 tdfi_rdlvl_resplat(RW) 00000000 tdfi_rdlvl_resp(RD) 01000000 refresh_per_zq(RW) 00000000 rdlvl_offset_delay_8(RW) 00000000 rdlvl_offset_delay_7(RW) |
|||
MC0_DDR3_RDIMM_CTL_830 : .dword 0x0000000000000c00 |
|||
//00000000 wrlvl_delay_5(RD) 00000000 wrlvl_delay_4(RD) 00000000 wrlvl_delay_3(RD) 00000000 wrlvl_delay_2(RD) 00000000 wrlvl_delay_1(RD) 00000000 wrlvl_delay_0(RD) 00000010 tmod(RW) 00000000 tdfi_wrlvl_ww(RD) |
|||
MC0_DDR3_RDIMM_CTL_840 : .dword 0x0000640064000000 |
|||
//00000000000000_0001100100 axi1_priority_relax(RW) 000000_0001100100 axi0_priority_relax(RW) 00000000 wrlvl_delay_8(RD) 00000000 wrlvl_delay_7(RD) 00000000 wrlvl_delay_6(RD) |
|||
MC0_DDR3_RDIMM_CTL_850 : .dword 0x0000000000000064 |
|||
//000000_0000000000 out_of_range_source_id(RD) 000000_0000000000 ecc_u_id(RD) 000000_0000000000 ecc_c_id(RD) 000000_0000000000 axi2_priority_relax(RW) |
|||
MC0_DDR3_RDIMM_CTL_860 : .dword 0x0200004000000000 |
|||
//0000_000000000000 zqini(RW) 0000_000000000000 zqcs(RW) 000000_0000000000 port_data_error_id(RD) 000000_0000000000 port_cmd_error_id(RD) |
|||
MC0_DDR3_RDIMM_CTL_870 : .dword 0x0000000000000000 |
|||
//0_000000000000010 emrs1_data_3(RD) 0_000000000000010 emrs1_data_2(RD) 0_000000000000010 emrs1_data_1(RD) 0_000000000000010 emrs1_data_0(RD) |
|||
MC0_DDR3_RDIMM_CTL_880 : .dword 0x0000000000000000 |
|||
//0_000000000000010 emrs3_data_3(RW) 0_000000000000010 emrs3_data_2(RW) 0_000000000000010 emrs3_data_1(RW) 0_000000000000010 emrs3_data_0(RW) |
|||
MC0_DDR3_RDIMM_CTL_890 : .dword 0x0000000000000000 |
|||
//0_000010000010000 mrs_data_3(RD) 0_000010000010000 mrs_data_2(RD) 0_000010000010000 mrs_data_1(RD) 0_000010000010000 mrs_data_0(RD) |
|||
MC0_DDR3_RDIMM_CTL_8a0 : .dword 0x00000000001c001c |
|||
//hXXXX lowpower_internal_cnt(RW) hXXXX lowpower_external_cnt(RW) hXXXX axi2_en_size_lt_width_instr(RW) hXXXX axi1_en_size_lt_width_instr(RW) |
|||
MC0_DDR3_RDIMM_CTL_8b0 : .dword 0x0000000000000000 |
|||
//hXXXX refresh_per_rdlvl(RW) hXXXX lowpower_self_refresh_cnt(RW) hXXXX lowpower_refresh_hold(RW) hXXXX lowpower_power_down_cnt(RW) |
|||
MC0_DDR3_RDIMM_CTL_8c0 : .dword 0x0000000000000000 |
|||
//hXXXX wrlvl_interval(RW) hXXXX tdfi_wrlvl_max(RW) hXXXX tdfi_rdlvl_max(RW) hXXXX refresh_per_rdlvl_gate(RW) |
|||
MC0_DDR3_RDIMM_CTL_8d0 : .dword 0x0000030d40000000 |
|||
//h00_XXXXXXXX cke_inactive(RW) 000000_000000000000000000 wrlvl_status(RD) |
|||
MC0_DDR3_RDIMM_CTL_8e0 : .dword 0x0000000023c34600 |
|||
//h00000000_XXXXXXXX trst_pwron(RW) |
|||
MC0_DDR3_RDIMM_CTL_8f0 : .dword 0x000000001a1a1a80 |
|||
//hXXXXXXX 000_0 XXXXXXXX dll_ctrl_reg_2(RW) |
|||
MC0_DDR3_RDIMM_CTL_900 : .dword 0x0000000000000000 |
|||
//h000000 00_00 X XXXXXXXX rdlvl_error_status(RW) |
|||
MC0_DDR3_RDIMM_CTL_910 : .dword 0x0000000000000000 |
|||
//hXXXXXXXX XXXXXXXX rdlvl_gate_resp_mask[63:0](RW) |
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MC0_DDR3_RDIMM_CTL_920 : .dword 0x0000000000000000 |
|||
//h00000000000000_XX rdlvl_gate_resp_mask[71:64](RW) |
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MC0_DDR3_RDIMM_CTL_930 : .dword 0x0000000000000000 |
|||
//hXXXXXXXX XXXXXXXX rdlvl_resp_mask[63:0](RW) |
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MC0_DDR3_RDIMM_CTL_940 : .dword 0xff07070000060600 |
|||
//0000_0000 tdfi_rdlvl_en(RW) 00000_000 w2r_samecs_delay(RW) 00000_000 w2r_diffcs_delay(RW) 00000_000 lvl_status(RD) 0000000_0 rdlvl_edge(RW) 0000_0000 cksrx(RW) 0000_0000 cksre(RW) _00000000 rdlvl_resp_mask[71:64](RW) |
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MC0_DDR3_RDIMM_CTL_950 : .dword 0x0000000000000d00 |
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//hXXXXX 00_00 XXXX mask_int[17:0](RW) hXXXX txpdll(RW) 0000_0000 tdfi_wrlvl_en(RW) |
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MC0_DDR3_RDIMM_CTL_960 : .dword 0x0705000000000000 |
|||
//000_00101 rdlat_adj(RW) 0000_0100 wrlat_adj(RW) 0000000_0 swlvl_start(WR) 0000000_0 swlvl_load(WR) 0000000_0 swlvl_exit(WR) 000000_000000000000000000 int_status(RD) |
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MC0_DDR3_RDIMM_CTL_970 : .dword 0x0100000000008020 |
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//h00000 000_0 XXXX int_ack[16:0](WR) hXXXX dll_rst_delay(RW) hXX dll_rst_adj_dly(RW) |
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MC0_DDR3_RDIMM_CTL_980 : .dword 0x0001010001000101 |
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//0000000_0 zq_in_progress(RD) 0000000_1 zqcs_rotate(RW) 0000000_0 wrlvl_reg_en(RW) 0000000_0 wrlvl_en(RW) 0000000_1 resync_dll_per_aref_en(RW) 0000000_0 resync_dll(WR) 0000000_0 rdlvl_reg_en(RW) 0000000_0 rdlvl_gate_reg_en(RW) |
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MC0_DDR3_RDIMM_CTL_990 : .dword 0x0707040707070700 |
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//00000_000 w2w_samecs_dly(RW) 00000_001 w2w_diffcs_dly(RW) 00000_010 tbst_int_interval(RW) 00000_010 r2w_samecs_dly(RW) 00000_010 r2w_diffcs_dly(RW) 00000_000 r2r_samecs_dly(RW) 00000_001 r2r_diffcs_dly(RW) 00000_000 axi_aligned_strobe_disable(RW) |
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MC0_DDR3_RDIMM_CTL_9a0 : .dword 0x0707040804080404 |
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//00000111 tdfi_wrlvl_load(RW) 00000111 tdfi_rdlvl_load(RW) 000_00011 tckesr(RW) 000_00010 tccd(RW) 000_00000 add_odt_clk_difftype_diffcs(RW) 0000_0110 trp_ab(RW) 0000_0001 add_odt_clk_sametype_diffcs(RW) 0000_0000 add_odt_clk_difftype_samecs(RW) |
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MC0_DDR3_RDIMM_CTL_9b0 : .dword 0x02000100000a000f |
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//0000_001000000000 zqinit(RD) 0000_000100000000 zqcl(RW) 000000_0000001010 tdfi_wrlvl_ww(RW) 000000_0000001111 tdfi_rdlvl_rr(RW) |
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MC0_DDR3_RDIMM_CTL_9c0 : .dword 0x04200c2d0c2d0c2d |
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//0_000101001010010 mr0_data_0(RW) 00_00110000101101 tdfi_phyupd_type3(RW) 00_00110000101101 tdfi_phyupd_type2(RW) 00_00110000101101 tdfi_phyupd_type1(RW) |
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MC0_DDR3_RDIMM_CTL_9d0 : .dword 0x0044042004200420 |
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//0_000000000000100 mr1_data_0(RW) 0_000101001010010 mr0_data_3(RW) 0_000101001010010 mr0_data_2(RW) 0_000101001010010 mr0_data_1(RW) |
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MC0_DDR3_RDIMM_CTL_9e0 : .dword 0x0000004400440044 |
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//0_000000000000000 mr2_data_0(RW) 0_000000000000100 mr1_data_3(RW) 0_000000000000100 mr1_data_2(RW) 0_000000000000100 mr1_data_1(RW) |
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MC0_DDR3_RDIMM_CTL_9f0 : .dword 0x0000000000000000 |
|||
//0_000000000000000 mr3_data_0(RW) 0_000000000000000 mr2_data_3(RW) 0_000000000000000 mr2_data_2(RW) 0_000000000000000 mr2_data_1(RW) |
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MC0_DDR3_RDIMM_CTL_a00 : .dword 0x007f000000000000 |
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//0000000011111111 dfi_wrlvl_max_delay(RW) 0_000000000000000 mr3_data_3(RW) 0_000000000000000 mr3_data_2(RW) 0_000000000000000 mr3_data_1(RW) |
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MC0_DDR3_RDIMM_CTL_a10 : .dword 0x0000000000000000 |
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//0000000000000000 rdlvl_begin_delay_3(RD) 0000000000000000 rdlvl_begin_delay_2(RD) 0000000000000000 rdlvl_begin_delay_1(RD) 0000000000000000 rdlvl_begin_delay_0(RD) |
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MC0_DDR3_RDIMM_CTL_a20 : .dword 0x0000000000000000 |
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//0000000000000000 rdlvl_begin_delay_7(RD) 0000000000000000 rdlvl_begin_delay_6(RD) 0000000000000000 rdlvl_begin_delay_5(RD) 0000000000000000 rdlvl_begin_delay_4(RD) |
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MC0_DDR3_RDIMM_CTL_a30 : .dword 0x0020002000200000 |
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//0000111000001110 rdlvl_delay_2(RW) 0000111000001110 rdlvl_delay_1(RW) 0000111000001110 rdlvl_delay_0(RW) 0000000000000000 rdlvl_begin_delay_8(RD) |
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MC0_DDR3_RDIMM_CTL_a40 : .dword 0x0020002000200020 |
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//0000111000001110 rdlvl_delay_6(RW) 0000111000001110 rdlvl_delay_5(RW) 0000111000001110 rdlvl_delay_4(RW) 0000111000001110 rdlvl_delay_3(RW) |
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MC0_DDR3_RDIMM_CTL_a50 : .dword 0x0000000000200020 |
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//0000000000000000 rdlvl_end_delay_1(RD) 0000000000000000 rdlvl_end_delay_0(RD) 0000111000001110 rdlvl_delay_8(RW) 0000111000001110 rdlvl_delay_7(RW) |
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MC0_DDR3_RDIMM_CTL_a60 : .dword 0x0000000000000000 |
|||
//0000000000000000 rdlvl_end_delay_5(RD) 0000000000000000 rdlvl_end_delay_4(RD) 0000000000000000 rdlvl_end_delay_3(RD) 0000000000000000 rdlvl_end_delay_2(RD) |
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MC0_DDR3_RDIMM_CTL_a70 : .dword 0x0019000000000000 |
|||
//0000000000000000 rdlvl_gate_delay_0(RW+) 0000000000000000 rdlvl_end_delay_8(RD) 0000000000000000 rdlvl_end_delay_7(RD) 0000000000000000 rdlvl_end_delay_6(RD) |
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MC0_DDR3_RDIMM_CTL_a80 : .dword 0x0019001900190019 |
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//0000000000000000 rdlvl_gate_delay_4(RW+) 0000000000000000 rdlvl_gate_delay_3(RW+) 0000000000000000 rdlvl_gate_delay_2(RW+) 0000000000000000 rdlvl_gate_delay_1(RW+) |
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MC0_DDR3_RDIMM_CTL_a90 : .dword 0x0019001900190019 |
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//0000000000000000 rdlvl_gate_delay_8(RW+) 0000000000000000 rdlvl_gate_delay_7(RW+) 0000000000000000 rdlvl_gate_delay_6(RW+) 0000000000000000 rdlvl_gate_delay_5(RW+) |
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MC0_DDR3_RDIMM_CTL_aa0 : .dword 0x0000ffff00000022 |
|||
//0000000000000000 rdlvl_midpoint_delay_0(RD) 1111111111111111 rdlvl_max_delay(RW) 0000000000000000 rdlvl_gate_refresh_interval(RW) 0000000000010000 rdlvl_gate_max_delay(RW) |
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MC0_DDR3_RDIMM_CTL_ab0 : .dword 0x0000000000000000 |
|||
//0000000000000000 rdlvl_midpoint_delay_4(RD) 0000000000000000 rdlvl_midpoint_delay_3(RD) 0000000000000000 rdlvl_midpoint_delay_2(RD) 0000000000000000 rdlvl_midpoint_delay_1(RD) |
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MC0_DDR3_RDIMM_CTL_ac0 : .dword 0x0000000000000000 |
|||
//0000000000000000 rdlvl_midpoint_delay_8(RD) 0000000000000000 rdlvl_midpoint_delay_7(RD) 0000000000000000 rdlvl_midpoint_delay_6(RD) 0000000000000000 rdlvl_midpoint_delay_5(RD) |
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MC0_DDR3_RDIMM_CTL_ad0 : .dword 0x0000000000000000 |
|||
//0000000000000000 rdlvl_offset_delay_3(RW) 0000000000000000 rdlvl_offset_delay_2(RW) 0000000000000000 rdlvl_offset_delay_1(RW) 0000000000000000 rdlvl_offset_delay_0(RW) |
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MC0_DDR3_RDIMM_CTL_ae0 : .dword 0x0000000000000000 |
|||
//0000000000000000 rdlvl_offset_delay_7(RW) 0000000000000000 rdlvl_offset_delay_6(RW) 0000000000000000 rdlvl_offset_delay_5(RW) 0000000000000000 rdlvl_offset_delay_4(RW) |
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MC0_DDR3_RDIMM_CTL_af0 : .dword 0x0012001a00000000 |
|||
//0000000000000000 wrlvl_delay_1(RW+) 0000000000000000 wrlvl_delay_0(RW+) 0000000000000000 rdlvl_refresh_interval(RW) 0000000000000000 rdlvl_offset_delay_8(RW) |
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MC0_DDR3_RDIMM_CTL_b00 : .dword 0x000600000006000c |
|||
//0000000000000000 wrlvl_delay_5(RW+) 0000000000000000 wrlvl_delay_4(RW+) 0000000000000000 wrlvl_delay_3(RW+) 0000000000000000 wrlvl_delay_2(RW+) |
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MC0_DDR3_RDIMM_CTL_b10 : .dword 0x000000000012000c |
|||
//0000000000000000 wrlvl_refresh_interval(RW) 0000000000000000 wrlvl_delay_8(RW+) 0000000000000000 wrlvl_delay_7(RW+) 0000000000000000 wrlvl_delay_6(RW+) |
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MC0_DDR3_RDIMM_CTL_b20 : .dword 0x00000c2d00000c2d |
|||
//00000000000000000000110000101101 tdfi_rdlvl_resp(RW) 00000000000000000000110000101101 tdfi_rdlvl_max(RW) |
|||
MC0_DDR3_RDIMM_CTL_b30 : .dword 0x00000c2d00000c2d |
|||
//00000000000000000000110000101101 tdfi_wrlvl_resp(RW) 00000000000000000000000000000000 tdfi_wrlvl_max(RW) |
|||
#endif |
|||
File diff suppressed because it is too large
@ -0,0 +1,191 @@ |
|||
#define DEBUG_LOCORE |
|||
|
|||
|
|||
|
|||
#ifdef DEBUG_LOCORE |
|||
#define TTYDBG(x) \ |
|||
.rdata;98: .asciz x; .text; la a0, 98b; bal stringserial; nop |
|||
#define TTYDBG_COM1(x) \ |
|||
.rdata;98: .asciz x; .text; la a0, 98b; bal stringserial_COM1; nop |
|||
#else |
|||
#define TTYDBG(x) |
|||
#endif |
|||
|
|||
#define PRINTSTR(x) \ |
|||
.rdata;98: .asciz x; .text; la a0, 98b; bal stringserial; nop |
|||
|
|||
#ifdef DEVBD2F_SM502 |
|||
#define GPIOLED_DIR 0xe |
|||
#else |
|||
#define GPIOLED_DIR 0xf |
|||
#endif |
|||
|
|||
#undef USE_GPIO_SERIAL |
|||
#ifndef USE_GPIO_SERIAL |
|||
#define GPIOLED_SET(x) \ |
|||
li v0,0xbfe0011c; \ |
|||
lw v1,4(v0); \ |
|||
or v1,0xf; \ |
|||
xor v1,GPIOLED_DIR; \ |
|||
sw v1,4(v0); \ |
|||
li v1,(~x)&0xf;\ |
|||
sw v1,0(v0);\ |
|||
li v1,0x1000;\ |
|||
78: \ |
|||
subu v1,1;\ |
|||
bnez v1,78b;\ |
|||
nop; |
|||
#else |
|||
#define GPIOLED_SET(x) |
|||
#endif |
|||
|
|||
|
|||
/* set GPIO as output
|
|||
* x : 0x1<<offset |
|||
*/ |
|||
#define GPIO_SET_OUTPUT(x) \ |
|||
li v0, 0xbfe0011c; \ |
|||
lw v1, 0(v0); \ |
|||
or v1, x&0xffff; \ |
|||
xor v1, 0x0; \ |
|||
sw v1, 0(v0); \ |
|||
lw v1, 4(v0); \ |
|||
or v1, x&0xffff; \ |
|||
xor v1, x; \ |
|||
sw v1, 4(v0); \ |
|||
nop; \ |
|||
nop; |
|||
|
|||
/* clear GPIO as output
|
|||
* x : 0x1 <<offsest |
|||
*/ |
|||
#define GPIO_CLEAR_OUTPUT(x) \ |
|||
li v0, 0xbfe0011c; \ |
|||
lw v1, 0(v0); \ |
|||
or v1, x&0xffff; \ |
|||
xor v1, x; \ |
|||
sw v1, 0(v0); \ |
|||
lw v1, 4(v0); \ |
|||
or v1, x&0xffff; \ |
|||
xor v1, x; \ |
|||
sw v1, 4(v0); \ |
|||
nop; \ |
|||
nop; |
|||
|
|||
/* WatchDog Close for chip MAX6369*/ |
|||
#define WatchDog_Close \ |
|||
GPIO_CLEAR_OUTPUT(0x1<<5); \ |
|||
GPIO_SET_OUTPUT(0x1<<3|0x1<<4); \ |
|||
GPIO_CLEAR_OUTPUT(0x1<<13); \ |
|||
|
|||
/* WatchDog Enable for chip MAX6369*/ |
|||
#define WatchDog_Enable \ |
|||
GPIO_CLEAR_OUTPUT(0x1<<13); \ |
|||
GPIO_SET_OUTPUT(0x1<<14); \ |
|||
GPIO_SET_OUTPUT(0x1<<5); \ |
|||
GPIO_CLEAR_OUTPUT(0x1<<4); \ |
|||
GPIO_SET_OUTPUT(0x1<<3); \ |
|||
GPIO_CLEAR_OUTPUT(0x1<<14); \ |
|||
li v1,0x100;\ |
|||
78:; \ |
|||
subu v1,1; \ |
|||
bnez v1,78b; \ |
|||
nop; \ |
|||
GPIO_SET_OUTPUT(0x1<<13); |
|||
|
|||
#define w83627write(x,y,z) \ |
|||
li v0, 0xb800002e; \ |
|||
li v1, 0x87; \ |
|||
sb v1, 0(v0); \ |
|||
sb v1, 0(v0); \ |
|||
li v1, 0x7; \ |
|||
sb v1, 0(v0); \ |
|||
li v1, x; \ |
|||
sb v1, 1(v0); \ |
|||
li v1, y; \ |
|||
sb v1, 0(v0); \ |
|||
li v1, z; \ |
|||
sb v1, 1(v0); \ |
|||
li v1, 0xaa; \ |
|||
sb v1, 0(v0); \ |
|||
sb v1, 0(v0); \ |
|||
nop; \ |
|||
nop |
|||
|
|||
#define CONFIG_CACHE_64K_4WAY 1 |
|||
|
|||
#define tmpsize s1 |
|||
#define msize s2 |
|||
#define bonito s4 |
|||
#define dbg s5 |
|||
#define sdCfg s6 |
|||
|
|||
|
|||
/*
|
|||
* Coprocessor 0 register names |
|||
*/ |
|||
#define CP0_INDEX $0 |
|||
#define CP0_RANDOM $1 |
|||
#define CP0_ENTRYLO0 $2 |
|||
#define CP0_ENTRYLO1 $3 |
|||
#define CP0_CONF $3 |
|||
#define CP0_CONTEXT $4 |
|||
#define CP0_PAGEMASK $5 |
|||
#define CP0_WIRED $6 |
|||
#define CP0_INFO $7 |
|||
#define CP0_BADVADDR $8 |
|||
#define CP0_COUNT $9 |
|||
#define CP0_ENTRYHI $10 |
|||
#define CP0_COMPARE $11 |
|||
#define CP0_STATUS $12 |
|||
#define CP0_CAUSE $13 |
|||
#define CP0_EPC $14 |
|||
#define CP0_PRID $15 |
|||
#define CP0_CONFIG $16 |
|||
#define CP0_LLADDR $17 |
|||
#define CP0_WATCHLO $18 |
|||
#define CP0_WATCHHI $19 |
|||
#define CP0_XCONTEXT $20 |
|||
#define CP0_FRAMEMASK $21 |
|||
#define CP0_DIAGNOSTIC $22 |
|||
#define CP0_PERFORMANCE $25 |
|||
#define CP0_ECC $26 |
|||
#define CP0_CACHEERR $27 |
|||
#define CP0_TAGLO $28 |
|||
#define CP0_TAGHI $29 |
|||
#define CP0_ERROREPC $30 |
|||
|
|||
#define CP0_DEBUG $23 |
|||
#define CP0_DEPC $24 |
|||
#define CP0_DESAVE $31 |
|||
|
|||
#define NODE0_CORE0_BUF0 0x900000003ff01000 |
|||
#define NODE1_CORE0_BUF0 0x900010003ff01000 |
|||
#define NODE2_CORE0_BUF0 0x900020003ff01000 |
|||
#define NODE3_CORE0_BUF0 0x900030003ff01000 |
|||
|
|||
#define HT_REMOTE_NODE 0x900010003ff01000 |
|||
|
|||
|
|||
#define Index_Store_Tag_I 0x08 |
|||
#define Index_Store_Tag_D 0x09 |
|||
#define Index_Store_Tag_V 0x0a |
|||
#define Index_Invalidate_I 0x00 |
|||
#define Index_Writeback_Inv_D 0x01 |
|||
#define Index_Store_Tag_S 0x0b |
|||
#define Index_Writeback_Inv_S 0x03 |
|||
|
|||
#define FN_OFF 0x020 |
|||
#define SP_OFF 0x028 |
|||
#define GP_OFF 0x030 |
|||
#define A1_OFF 0x038 |
|||
|
|||
|
|||
#define L2_CACHE_OK 0x1111 |
|||
#define L2_CACHE_DONE 0x2222 |
|||
#define TEST_HT 0x3333 |
|||
#define NODE_MEM_INIT_DONE 0x4444 |
|||
#define ALL_CORE0_INIT_DONE 0x5555 |
|||
#define NODE_SCACHE_ENABLED 0x6666 |
|||
#define SYSTEM_INIT_OK 0x5a5a |
|||
|
|||
@ -0,0 +1,74 @@ |
|||
/*whd : loongson3_fixup.S |
|||
used to fix up the potential addressing miss |
|||
caused by speculated execution |
|||
*/ |
|||
|
|||
dli t2, 0x900000003ff02000 |
|||
dli t1, 0x900000003ff02800 |
|||
TTYDBG("Fix L1xbar illegal access at NODE 0\r\n") |
|||
1: |
|||
|
|||
####### Unused HT0 port ######################### |
|||
dli t0, 0x00000c0000000000 |
|||
sd t0, 0x28(t2) |
|||
dli t0, 0x00000c0000000000 |
|||
sd t0, 0x68(t2) |
|||
dli t0, 0x00000c00000000f7 |
|||
sd t0, 0xa8(t2) |
|||
|
|||
dli t0, 0x0000200000000000 |
|||
sd t0, 0x30(t2) |
|||
dli t0, 0x0000200000000000 |
|||
sd t0, 0x70(t2) |
|||
dli t0, 0x00002000000000f7 |
|||
sd t0, 0xb0(t2) |
|||
|
|||
dli t0, 0x000000fdfe000000 |
|||
sd t0, 0x38(t2) |
|||
dli t0, 0x000000fffe000000 |
|||
sd t0, 0x78(t2) |
|||
dli t0, 0x000000fdfe0000f7 |
|||
sd t0, 0xb8(t2) |
|||
|
|||
####### address space to other nodes ############ |
|||
dli t0, 0x0000200000000000 |
|||
sd t0, 0x30(t2) |
|||
dli t0, 0x0000200000000000 |
|||
sd t0, 0x70(t2) |
|||
dli t0, 0x00002000000000f7 |
|||
sd t0, 0xb0(t2) |
|||
|
|||
dli t0, 0x0000100000000000 |
|||
sd t0, 0x38(t2) |
|||
dli t0, 0x0000300000000000 |
|||
sd t0, 0x78(t2) |
|||
dli t0, 0x00001000000000f7 |
|||
sd t0, 0xb8(t2) |
|||
|
|||
daddiu t2, t2, 0x100 |
|||
bne t2, t1, 1b |
|||
nop |
|||
|
|||
############ |
|||
TTYDBG("Fix L2xbar in NODE 0\r\n") |
|||
//order cann't be changed. |
|||
dli t2, 0x900000003ff00000 |
|||
|
|||
dli t0, 0xfffffffffff00000 |
|||
sd t0, 0x40(t2) |
|||
|
|||
dli t0, 0x000000001fc000f2 |
|||
sd t0, 0x80(t2) |
|||
|
|||
dli t0, 0x000000001fc00000 |
|||
sd t0, 0x0(t2) |
|||
|
|||
############ 0x10000000 Set to not allow Cache access ####### |
|||
dli t0, 0x0000000010000000 |
|||
sd t0, 0x08(t2) |
|||
dli t0, 0xfffffffff0000000 |
|||
sd t0, 0x48(t2) |
|||
dli t0, 0x0000000010000082 |
|||
sd t0, 0x88(t2) |
|||
|
|||
sd $0, 0x90(t2) |
|||
@ -0,0 +1,678 @@ |
|||
//DDR2 param |
|||
.align 5 |
|||
ddr2_reg_data: |
|||
|
|||
ddr2_reg_data_mc1: |
|||
|
|||
MC0_DDR2_CTRL_0x000: .dword 0x0000000000000000 |
|||
//XXXX pm_dll_value_0(RD) XXXX pm_dll_value_ck(RD) XXXX pm_dll_init_done(RD) XXXX pm_version(RD) |
|||
MC0_DDR2_CTRL_0x008: .dword 0x0000000000000000 |
|||
//XXXX pm_dll_value_4(RD) XXXX pm_dll_value_3 (RD) XXXX pm_dll_value_2(RD) XXXX pm_dll_value_1(RD) |
|||
MC0_DDR2_CTRL_0x010: .dword 0x0000000000000000 |
|||
//XXXX pm_dll_value_8(RD) XXXX pm_dll_value_7 (RD) XXXX pm_dll_value_6(RD) XXXX pm_dll_value_5(RD) |
|||
MC0_DDR2_CTRL_0x018: .dword 0x0000000004100100 |
|||
//_00000000 pm_dll_ck_3 _00000000 pm_dll_ck_2 _00000000 pm_dll_ck_1 _00000000 pm_dll_ck_0 _00000000 pm_dll_increment _00000000 pm_dll_start_point _0000000_0 pm_dll_bypass _0000000_0 pm_init_start |
|||
MC0_DDR2_CTRL_0x020: .dword 0x0202000001000100 |
|||
//0000_0000 pm_dq_oe_end_0 0000_0000 pm_dq_oe_begin_0 000000_00 pm_dq_stop_edge_0 000000_00 pm_dq_start_edge_0 0000000_0 pm_rddata_delay_0 0000000_0 pm_rddqs_lt_half_0 0000000_0 pm_wrdqs_lt_half_0 0000000_0 pm_wrdq_lt_half_0 |
|||
MC0_DDR2_CTRL_0x028: .dword 0x0000030302010101 |
|||
//0000_0000 pm_rd_oe_end_0 0000_0000 pm_rd_oe_begin_0 000000_00 pm_rd_stop_edge_0 000000_00 pm_rd_start_edge_0 0000_0000 pm_dqs_oe_end_0 0000_0000 pm_dqs_oe_begin_0 000000_00 pm_dqs_stop_edge_0 000000_00 pm_dqs_start_edge_0 |
|||
MC0_DDR2_CTRL_0x030: .dword 0x0000000002010000 |
|||
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_0 0000_0000 pm_odt_oe_end_0 0000_0000 pm_odt_oe_begin_0 000000_00 pm_odt_stop_edge_0 000000_00 pm_odt_start_edge_0 |
|||
MC0_DDR2_CTRL_0x038: .dword 0x0000002020056500 |
|||
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_0 _00000000 pm_dll_rddqs_p_0 _00000000 pm_dll_wrdqs_0 _00000000 pm_dll_wrdata_0 _00000000 pm_dll_gate_0 |
|||
MC0_DDR2_CTRL_0x040: .dword 0x0202000001000100 |
|||
//0000_0000 pm_dq_oe_end_1 0000_0000 pm_dq_oe_begin_1 000000_00 pm_dq_stop_edge_1 000000_00 pm_dq_start_edge_1 0000000_0 pm_rddata_delay_1 0000000_0 pm_rddqs_lt_half_1 0000000_0 pm_wrdqs_lt_half_1 0000000_0 pm_wrdq_lt_half_1 |
|||
MC0_DDR2_CTRL_0x048: .dword 0x0000030302010101 |
|||
//0000_0000 pm_rd_oe_end_1 0000_0000 pm_rd_oe_begin_1 000000_00 pm_rd_stop_edge_1 000000_00 pm_rd_start_edge_1 0000_0000 pm_dqs_oe_end_1 0000_0000 pm_dqs_oe_begin_1 000000_00 pm_dqs_stop_edge_1 000000_00 pm_dqs_start_edge_1 |
|||
MC0_DDR2_CTRL_0x050: .dword 0x0000000002010000 |
|||
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_1 0000_0000 pm_odt_oe_end_1 0000_0000 pm_odt_oe_begin_1 000000_00 pm_odt_stop_edge_1 000000_00 pm_odt_start_edge_1 |
|||
MC0_DDR2_CTRL_0x058: .dword 0x0000002020056500 |
|||
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_1 _00000000 pm_dll_rddqs_p_1 _00000000 pm_dll_wrdqs_1 _00000000 pm_dll_wrdata_1 _00000000 pm_dll_gate_1 |
|||
MC0_DDR2_CTRL_0x060: .dword 0x0202000001000100 |
|||
//0000_0000 pm_dq_oe_end_2 0000_0000 pm_dq_oe_begin_2 000000_00 pm_dq_stop_edge_2 000000_00 pm_dq_start_edge_2 0000000_0 pm_rddata_delay_2 0000000_0 pm_rddqs_lt_half_2 0000000_0 pm_wrdqs_lt_half_2 0000000_0 pm_wrdq_lt_half_2 |
|||
MC0_DDR2_CTRL_0x068: .dword 0x0000030302010101 |
|||
//0000_0000 pm_rd_oe_end_2 0000_0000 pm_rd_oe_begin_2 000000_00 pm_rd_stop_edge_2 000000_00 pm_rd_start_edge_2 0000_0000 pm_dqs_oe_end_2 0000_0000 pm_dqs_oe_begin_2 000000_00 pm_dqs_stop_edge_2 000000_00 pm_dqs_start_edge_2 |
|||
MC0_DDR2_CTRL_0x070: .dword 0x0000000002010000 |
|||
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_2 0000_0000 pm_odt_oe_end_2 0000_0000 pm_odt_oe_begin_2 000000_00 pm_odt_stop_edge_2 000000_00 pm_odt_start_edge_2 |
|||
MC0_DDR2_CTRL_0x078: .dword 0x0000002020056500 |
|||
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_2 _00000000 pm_dll_rddqs_p_2 _00000000 pm_dll_wrdqs_2 _00000000 pm_dll_wrdata_2 _00000000 pm_dll_gate_2 |
|||
MC0_DDR2_CTRL_0x080: .dword 0x0202000001000100 |
|||
//0000_0000 pm_dq_oe_end_3 0000_0000 pm_dq_oe_begin_3 000000_00 pm_dq_stop_edge_3 000000_00 pm_dq_start_edge_3 0000000_0 pm_rddata_delay_3 0000000_0 pm_rddqs_lt_half_3 0000000_0 pm_wrdqs_lt_half_3 0000000_0 pm_wrdq_lt_half_3 |
|||
MC0_DDR2_CTRL_0x088: .dword 0x0000030302010101 |
|||
//0000_0000 pm_rd_oe_end_3 0000_0000 pm_rd_oe_begin_3 000000_00 pm_rd_stop_edge_3 000000_00 pm_rd_start_edge_3 0000_0000 pm_dqs_oe_end_3 0000_0000 pm_dqs_oe_begin_3 000000_00 pm_dqs_stop_edge_3 000000_00 pm_dqs_start_edge_3 |
|||
MC0_DDR2_CTRL_0x090: .dword 0x0000000002010000 |
|||
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_3 0000_0000 pm_odt_oe_end_3 0000_0000 pm_odt_oe_begin_3 000000_00 pm_odt_stop_edge_3 000000_00 pm_odt_start_edge_3 |
|||
MC0_DDR2_CTRL_0x098: .dword 0x0000002020056500 |
|||
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_3 _00000000 pm_dll_rddqs_p_3 _00000000 pm_dll_wrdqs_3 _00000000 pm_dll_wrdata_3 _00000000 pm_dll_gate_3 |
|||
MC0_DDR2_CTRL_0x0a0: .dword 0x0202000001000100 |
|||
//0000_0000 pm_dq_oe_end_4 0000_0000 pm_dq_oe_begin_4 000000_00 pm_dq_stop_edge_4 000000_00 pm_dq_start_edge_4 0000000_0 pm_rddata_delay_4 0000000_0 pm_rddqs_lt_half_4 0000000_0 pm_wrdqs_lt_half_4 0000000_0 pm_wrdq_lt_half_4 |
|||
MC0_DDR2_CTRL_0x0a8: .dword 0x0000030302010101 |
|||
//0000_0000 pm_rd_oe_end_4 0000_0000 pm_rd_oe_begin_4 000000_00 pm_rd_stop_edge_4 000000_00 pm_rd_start_edge_4 0000_0000 pm_dqs_oe_end_4 0000_0000 pm_dqs_oe_begin_4 000000_00 pm_dqs_stop_edge_4 000000_00 pm_dqs_start_edge_4 |
|||
MC0_DDR2_CTRL_0x0b0: .dword 0x0000000002010000 |
|||
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_4 0000_0000 pm_odt_oe_end_4 0000_0000 pm_odt_oe_begin_4 000000_00 pm_odt_stop_edge_4 000000_00 pm_odt_start_edge_4 |
|||
MC0_DDR2_CTRL_0x0b8: .dword 0x0000002020056500 |
|||
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_4 _00000000 pm_dll_rddqs_p_4 _00000000 pm_dll_wrdqs_4 _00000000 pm_dll_wrdata_4 _00000000 pm_dll_gate_4 |
|||
MC0_DDR2_CTRL_0x0c0: .dword 0x0202000001000100 |
|||
//0000_0000 pm_dq_oe_end_5 0000_0000 pm_dq_oe_begin_5 000000_00 pm_dq_stop_edge_5 000000_00 pm_dq_start_edge_5 0000000_0 pm_rddata_delay_5 0000000_0 pm_rddqs_lt_half_5 0000000_0 pm_wrdqs_lt_half_5 0000000_0 pm_wrdq_lt_half_5 |
|||
MC0_DDR2_CTRL_0x0c8: .dword 0x0000030302010101 |
|||
//0000_0000 pm_rd_oe_end_5 0000_0000 pm_rd_oe_begin_5 000000_00 pm_rd_stop_edge_5 000000_00 pm_rd_start_edge_5 0000_0000 pm_dqs_oe_end_5 0000_0000 pm_dqs_oe_begin_5 000000_00 pm_dqs_stop_edge_5 000000_00 pm_dqs_start_edge_5 |
|||
MC0_DDR2_CTRL_0x0d0: .dword 0x0000000002010000 |
|||
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_5 0000_0000 pm_odt_oe_end_5 0000_0000 pm_odt_oe_begin_5 000000_00 pm_odt_stop_edge_5 000000_00 pm_odt_start_edge_5 |
|||
MC0_DDR2_CTRL_0x0d8: .dword 0x0000002020056500 |
|||
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_5 _00000000 pm_dll_rddqs_p_5 _00000000 pm_dll_wrdqs_5 _00000000 pm_dll_wrdata_5 _00000000 pm_dll_gate_5 |
|||
MC0_DDR2_CTRL_0x0e0: .dword 0x0202000001000100 |
|||
//0000_0000 pm_dq_oe_end_6 0000_0000 pm_dq_oe_begin_6 000000_00 pm_dq_stop_edge_6 000000_00 pm_dq_start_edge_6 0000000_0 pm_rddata_delay_6 0000000_0 pm_rddqs_lt_half_6 0000000_0 pm_wrdqs_lt_half_6 0000000_0 pm_wrdq_lt_half_6 |
|||
MC0_DDR2_CTRL_0x0e8: .dword 0x0000020202010101 |
|||
//0000_0000 pm_rd_oe_end_6 0000_0000 pm_rd_oe_begin_6 000000_00 pm_rd_stop_edge_6 000000_00 pm_rd_start_edge_6 0000_0000 pm_dqs_oe_end_6 0000_0000 pm_dqs_oe_begin_6 000000_00 pm_dqs_stop_edge_6 000000_00 pm_dqs_start_edge_6 |
|||
MC0_DDR2_CTRL_0x0f0: .dword 0x0000000002010000 |
|||
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_6 0000_0000 pm_odt_oe_end_6 0000_0000 pm_odt_oe_begin_6 000000_00 pm_odt_stop_edge_6 000000_00 pm_odt_start_edge_6 |
|||
MC0_DDR2_CTRL_0x0f8: .dword 0x0000002020056500 |
|||
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_6 _00000000 pm_dll_rddqs_p_6 _00000000 pm_dll_wrdqs_6 _00000000 pm_dll_wrdata_6 _00000000 pm_dll_gate_6 |
|||
MC0_DDR2_CTRL_0x100: .dword 0x0202000001000100 |
|||
//0000_0000 pm_dq_oe_end_7 0000_0000 pm_dq_oe_begin_7 000000_00 pm_dq_stop_edge_7 000000_00 pm_dq_start_edge_7 0000000_0 pm_rddata_delay_7 0000000_0 pm_rddqs_lt_half_7 0000000_0 pm_wrdqs_lt_half_7 0000000_0 pm_wrdq_lt_half_7 |
|||
MC0_DDR2_CTRL_0x108: .dword 0x0000020202010101 |
|||
//0000_0000 pm_rd_oe_end_7 0000_0000 pm_rd_oe_begin_7 000000_00 pm_rd_stop_edge_7 000000_00 pm_rd_start_edge_7 0000_0000 pm_dqs_oe_end_7 0000_0000 pm_dqs_oe_begin_7 000000_00 pm_dqs_stop_edge_7 000000_00 pm_dqs_start_edge_7 |
|||
MC0_DDR2_CTRL_0x110: .dword 0x0000000002010000 |
|||
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_7 0000_0000 pm_odt_oe_end_7 0000_0000 pm_odt_oe_begin_7 000000_00 pm_odt_stop_edge_7 000000_00 pm_odt_start_edge_7 |
|||
MC0_DDR2_CTRL_0x118: .dword 0x0000002020056500 |
|||
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_7 _00000000 pm_dll_rddqs_p_7 _00000000 pm_dll_wrdqs_7 _00000000 pm_dll_wrdata_7 _00000000 pm_dll_gate_7 |
|||
MC0_DDR2_CTRL_0x120: .dword 0x0202000001000000 |
|||
//0000_0000 pm_dq_oe_end_8 0000_0000 pm_dq_oe_begin_8 000000_00 pm_dq_stop_edge_8 000000_00 pm_dq_start_edge_8 0000000_0 pm_rddata_delay_8 0000000_0 pm_rddqs_lt_half_8 0000000_0 pm_wrdqs_lt_half_8 0000000_0 pm_wrdq_lt_half_8 |
|||
MC0_DDR2_CTRL_0x128: .dword 0x0101000002010101 |
|||
//0000_0000 pm_rd_oe_end_8 0000_0000 pm_rd_oe_begin_8 000000_00 pm_rd_stop_edge_8 000000_00 pm_rd_start_edge_8 0000_0000 pm_dqs_oe_end_8 0000_0000 pm_dqs_oe_begin_8 000000_00 pm_dqs_stop_edge_8 000000_00 pm_dqs_start_edge_8 |
|||
MC0_DDR2_CTRL_0x130: .dword 0x0000000002010000 |
|||
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_8 0000_0000 pm_odt_oe_end_8 0000_0000 pm_odt_oe_begin_8 000000_00 pm_odt_stop_edge_8 000000_00 pm_odt_start_edge_8 |
|||
MC0_DDR2_CTRL_0x138: .dword 0x00000020207f6000 |
|||
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_8 _00000000 pm_dll_rddqs_p_8 _00000000 pm_dll_wrdqs_8 _00000000 pm_dll_wrdata_8 _00000000 pm_dll_gate_8 |
|||
MC0_DDR2_CTRL_0x140: .dword 0x0000000001ff01ff |
|||
//00000_000 pm_pad_ocd_clk 00000_000 pm_pad_ocd_ctl 0000000_0 pm_pad_ocd_dqs 0000000_0 pm_pad_ocd_dq 0000000_0_00000000 pm_pad_enzi 0000000_0 pm_pad_en_ctl _00000000 pm_pad_en_clk |
|||
MC0_DDR2_CTRL_0x148: .dword 0x0000000000000000 |
|||
//_0000 pm_pad_adj_ncode_dq _0000 pm_pad_adj_pcode_dq 00000 _0 pm_pad_outodt_dq _0 pm_pad_slewrate_dq _0 pm_pad_code_dq _0000 pm_pad_adj_ncode_dq _0000 pm_pad_adj_pcode_dq 00000 _0 pm_pad_outodt_dq _0 pm_pad_slewrate_dq _0 00000000 0000000_0 pm_pad_vref_internal 0000000_0 pm_pad_odt_se 0000000_0 pm_pad_modezi1v8 |
|||
MC0_DDR2_CTRL_0x150: .dword 0x0000000000000000 |
|||
//hXXXX _0000 pm_pad_adj_ncode_clk _0000 pm_pad_adj_pcode_clk 00000 _0 pm_pad_outodt_clk _0 pm_pad_slewrate_clk _0 pm_pad_code_clk _0000 pm_pad_adj_ncode_cmd _0000 pm_pad_adj_pcode_cmd 00000 _0 pm_pad_outodt_cmd _0 pm_pad_slewrate_cmd _0 pm_pad_code_cmd _0000 pm_pad_adj_ncode_addr _0000 pm_pad_adj_pcode_addr 00000 _0 pm_pad_outodt_addr _0 pm_pad_slewrate_addr _0 pm_pad_code_addr |
|||
MC0_DDR2_CTRL_0x158: .dword 0x00000000f0000001 |
|||
//hXXXXXXXX (RD) _0000 pm_pad_comp_ncode_i _0000 pm_pad_comp_pcode_i 0000000_0 pm_pad_comp_mode 0000000_0 pm_pad_comp_tm 0000000_0 pm_pad_comp_pd |
|||
MC0_DDR2_CTRL_0x160: .dword 0x0000000000010000 |
|||
//0000000_0_00000000 pm_rdfifo_empty(RD) 0000000_0_00000000 pm_overflow(RD) 0000_0000 pm_dram_init(RD) 0000000_0 pm_rdfifo_valid 000000_00 pm_cmd_timing 0000000_0 pm_ddr3_mode |
|||
MC0_DDR2_CTRL_0x168: .dword 0x0000020303000101 |
|||
//hXXXX (RD) 000000_00 pm_cmd_delay _00000000 pm_burst_length 00000_000 pm_bank 0000_0000 pm_cs_zq 0000_0000 pm_cs_mrs 0000_0000 pm_cs_enable |
|||
MC0_DDR2_CTRL_0x170: .dword 0x8421020184210201 |
|||
//_00000000_00000000 pm_odt_wr_cs_map 0000_0000 pm_odt_wr_length 0000_0000 pm_odt_wr_delay _00000000_00000000 pm_odt_rd_cs_map 0000_0000 pm_odt_rd_length 0000_0000 pm_odt_rd_delay |
|||
MC0_DDR2_CTRL_0x178: .dword 0x0000000000000000 |
|||
//hXXXXXXXXXXXXXXXX (RD) |
|||
MC0_DDR2_CTRL_0x180: .dword 0x0000000001100000 |
|||
//_00000000 pm_lvl_resp_0(RD) 0000000_0 pm_lvl_done(RD) 0000000_0 pm_lvl_ready(RD) 00000000 0000_0000 pm_lvl_cs _00000000 pm_tLVL_DELAY 0000000_0 pm_leveling_req(WR) 000000_00 pm_leveling_mode |
|||
MC0_DDR2_CTRL_0x188: .dword 0x0000000000000000 |
|||
//_00000000 pm_lvl_resp_8(RD) _00000000 pm_lvl_resp_7(RD) _00000000 _pm_lvl_resp_6(RD) _00000000 pm_lvl_resp_5(RD) _00000000 pm_lvl_resp_4(RD) _00000000 pm_lvl_resp_3(RD) _00000000 pm_lvl_resp_2(RD) _00000000 pm_lvl_resp_1(RD) |
|||
|
|||
//CMD CONFIG |
|||
MC0_DDR2_CTRL_0x190: .dword 0x0000000000000000 |
|||
//_00000000_00000000 pm_cmd_a 00000_000 pm_cmd_ba 00000_000 pm_cmd_cmd 0000_0000 pm_cmd_cs 0000000_0 pm_status_cmd(RD) 0000000_0 pm_cmd_req(WR) 0000000_0 pm_command |
|||
MC0_DDR2_CTRL_0x198: .dword 0x0000000000000000 |
|||
//00000000 00000000 0000_0000 pm_status_sref(RD) 0000_0000 pm_srefresh_req 0000000_0 pm_pre_all_done(RD) 0000000_0 pm_pre_all_req(WR) 0000000_0 pm_mrs_done(RD) 0000000_0 pm_mrs_req(WR) |
|||
MC0_DDR2_CTRL_0x1a0: .dword 0x0000000000040952 |
|||
//_00000000_00000000 pm_mr_3_cs_0 _00000000_00000000 pm_mr_2_cs_0 _00000000_00000000 pm_mr_1_cs_0 _00000000_00000000 pm_mr_0_cs_0 |
|||
MC0_DDR2_CTRL_0x1a8: .dword 0x0000000000040952 |
|||
//_00000000_00000000 pm_mr_3_cs_1 _00000000_00000000 pm_mr_2_cs_1 _00000000_00000000 pm_mr_1_cs_1 _00000000_00000000 pm_mr_0_cs_1 |
|||
MC0_DDR2_CTRL_0x1b0: .dword 0x0000000000040952 |
|||
//_00000000_00000000 pm_mr_3_cs_2 _00000000_00000000 pm_mr_2_cs_2 _00000000_00000000 pm_mr_1_cs_2 _00000000_00000000 pm_mr_0_cs_2 |
|||
MC0_DDR2_CTRL_0x1b8: .dword 0x0000000000040952 |
|||
//_00000000_00000000 pm_mr_3_cs_3 _00000000_00000000 pm_mr_2_cs_3 _00000000_00000000 pm_mr_1_cs_3 _00000000_00000000 pm_mr_0_cs_3 |
|||
MC0_DDR2_CTRL_0x1c0: .dword 0x0001c80c03032004 |
|||
//_00000000 pm_tRESET _00000000 pm_tCKE _00000000 pm_tXPR _00000000 pm_tMOD _00000000 pm_tZQCL _00000000 pm_tZQ_CMD _00000000 pm_tWLDQSEN 000_00000 pm_tRDDATA |
|||
MC0_DDR2_CTRL_0x1c8: .dword 0x1606060620400004 |
|||
//00_000000 pm_tFAW 0000_0000 pm_tRRD 0000_0000 pm_tRCD _00000000 pm_tRP _00000000 pm_tREF _00000000 pm_tRFC _00000000 pm_tZQCS _00000000 pm_tZQperiod |
|||
MC0_DDR2_CTRL_0x1d0: .dword 0x0a0205020200001c |
|||
//0000_0000 pm_tODTL _00000000 pm_tXSRD 0000_0000 pm_tPHY_RDLAT 000_00000 pm_tPHY_WRLAT 000000_00_00000000_00000000 pm_tRAS_max 00_000000 pm_tRAS_min |
|||
MC0_DDR2_CTRL_0x1d8: .dword 0x1405060605040206 |
|||
//_00000000 pm_tXPDLL _00000000 pm_tXP 000_00000 pm_tWR 0000_0000 pm_tRTP 0000_0000 pm_tRL 0000_0000 pm_tWL 0000_0000 pm_tCCD 0000_0000 pm_tWTR |
|||
MC0_DDR2_CTRL_0x1e0: .dword 0x0401000000000000 |
|||
//00_000000 pm_tW2R_diffcs_dly 00_000000 pm_tW2W_diffcs_adj_dly 00_000000 pm_tR2P_sameba_adj_dly 00_000000 pm_tW2P_sameba_adj_dly 00_000000 pm_tR2R_sameba_adj_dly 00_000000 pm_tR2W_sameba_adj_dly 00_000000 pm_tW2R_sameba_adj_dly 00_000000 pm_tW2W_sameba_adj_dly |
|||
MC0_DDR2_CTRL_0x1e8: .dword 0x0104000000000000 |
|||
//00_000000 pm_tR2R_diffcs_adj_dly 00_000000 pm_tR2W_diffcs_dly 00_000000 pm_tR2P_samecs_dly 00_000000 pm_tW2P_samecs_dly 00_000000 pm_tR2R_samecs_adj_dly 00_000000 pm_tR2W_samecs_adj_dly 00_000000 pm_tW2R_samecs_adj_dly 00_000000 pm_tW2W_samecs_adj_dly |
|||
MC0_DDR2_CTRL_0x1f0: .dword 0x000801e4ff000101 |
|||
//0000_0000 pm_power_up _00000000 pm_age_step _00000000 pm_tCPDED _00000000 pm_cs_map _00000000 pm_bs_config 00000_000 pm_channel_32 pm_channel_16 pm_nc 0000_0000 pm_pr_r2w 0000000_0 pm_placement_en |
|||
MC0_DDR2_CTRL_0x1f8: .dword 0x0000000004081001 |
|||
//0000_0000 pm_hardware_pd_3 0000_0000 pm_hardware_pd_2 0000_0000 pm_hardware_pd_1 0000_0000 pm_hardware_pd_0 00_000000 pm_credit_16 00_000000 pm_credit_32 00_000000 pm_credit_64 0000000_0 pm_selection_en |
|||
MC0_DDR2_CTRL_0x200: .dword 0x0c000c000c00070c |
|||
//0000_0000_00000000 pm_cmdq_age_16 0000_0000_00000000 pm_cmdq_age_32 0000_0000_00000000 pm_cmdq_age_64 _00000000 pm_tCKESR _00000000 pm_tRDPDEN |
|||
MC0_DDR2_CTRL_0x208: .dword 0x0c000c0000000000 |
|||
//0000_0000_00000000 pm_wrfifo_age 0000_0000_00000000 pm_rdfifo_age 0000_0000 pm_power_status_3 0000_0000 pm_power_status_2 0000_0000 pm_power_status_1 0000_0000 pm_power_status_0 |
|||
MC0_DDR2_CTRL_0x210: .dword 0x0008000b00030106 |
|||
//_00000000_00000000 pm_active_age 0000000_0 pm_cs_place_0 0000_0000 pm_addr_win_0 000000_00 pm_cs_diff_0 00000_000 pm_row_diff_0 000000_00 pm_ba_diff_0 00000_000 pm_col_diff_0 |
|||
MC0_DDR2_CTRL_0x218: .dword 0x0008000b00030106 |
|||
//_00000000_00000000 pm_fastpd_age 0000000_0 pm_cs_place_1 0000_0000 pm_addr_win_1 000000_00 pm_cs_diff_1 00000_000 pm_row_diff_1 000000_00 pm_ba_diff_1 00000_000 pm_col_diff_1 |
|||
MC0_DDR2_CTRL_0x220: .dword 0x0008000b00030106 |
|||
//_00000000_00000000 pm_slowpd_age 0000000_0 pm_cs_place_2 0000_0000 pm_addr_win_2 000000_00 pm_cs_diff_2 00000_000 pm_row_diff_2 000000_00 pm_ba_diff_2 00000_000 pm_col_diff_2 |
|||
MC0_DDR2_CTRL_0x228: .dword 0x0008000b00030106 |
|||
//_00000000_00000000 pm_selfref_age 0000000_0 pm_cs_place_3 0000_0000 pm_addr_win_3 000000_00 pm_cs_diff_3 00000_000 pm_row_diff_3 000000_00 pm_ba_diff_3 00000_000 pm_col_diff_3 |
|||
MC0_DDR2_CTRL_0x230: .dword 0x0ffffe0000000000 |
|||
//0000_0000_00000000_00000000_00000000 pm_addr_mask_0 0000_0000_00000000_00000000_00000000 pm_addr_base_0 |
|||
MC0_DDR2_CTRL_0x238: .dword 0x0ffffe000000ff00 |
|||
//0000_0000_00000000_00000000_00000000 pm_addr_mask_1 0000_0000_00000000_00000000_00000000 pm_addr_base_1 |
|||
MC0_DDR2_CTRL_0x240: .dword 0x0ffffe000000ff00 |
|||
//0000_0000_00000000_00000000_00000000 pm_addr_mask_2 0000_0000_00000000_00000000_00000000 pm_addr_base_2 |
|||
MC0_DDR2_CTRL_0x248: .dword 0x0ffffe000000ff00 |
|||
//0000_0000_00000000_00000000_00000000 pm_addr_mask_3 0000_0000_00000000_00000000_00000000 pm_addr_base_3 |
|||
MC0_DDR2_CTRL_0x250: .dword 0x0000000000000000 |
|||
//00000000 _00_00_00_00 pm_cmd_monitor_3_2_1_0 000000_00_00000000 pm_axi_monitor _00000000 pm_ecc_code(RD) 0000_0_000 pm_int_trigger pm_ecc_enable 000000_00 pm_int_vector 000000_00 pm_int_enable |
|||
MC0_DDR2_CTRL_0x258: .dword 0x0000000000000000 |
|||
//XXXXXXXXXXXXXXXX (RD) |
|||
MC0_DDR2_CTRL_0x260: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_ecc_addr(RD) |
|||
MC0_DDR2_CTRL_0x268: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_ecc_data(RD) |
|||
MC0_DDR2_CTRL_0x270: .dword 0x0000001000000000 |
|||
//000000_00 pm_lpbk_ecc_mask(RD) 0_0000000_00000000_00000000 pm_prbs_init 0000000_0 pm_lpbk_error(RD) 0000000_0 pm_prbs_23 0000000_0 pm_lpbk_start 0000000_0 pm_lpbk_en |
|||
MC0_DDR2_CTRL_0x278: .dword 0x0000000000000000 |
|||
//_00000000_00000000 pm_lpbk_ecc(RD) _00000000_00000000 pm_lpbk_data_mask(RD) _00000000_00000000 pm_lpbk_correct(RD) _00000000_00000000 pm_lpbk_counter(RD) |
|||
MC0_DDR2_CTRL_0x280: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_lpbk_data[ 63: 0](RD) |
|||
MC0_DDR2_CTRL_0x288: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_lpbk_data[127:64](RD) |
|||
|
|||
//Monitor fbck |
|||
MC0_DDR2_CTRL_0x290: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi0_fbck[ 63: 0](RD) |
|||
MC0_DDR2_CTRL_0x298: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi0_fbck[127:64](RD) |
|||
MC0_DDR2_CTRL_0x2a0: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi1_fbck[ 63: 0](RD) |
|||
MC0_DDR2_CTRL_0x2a8: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi1_fbck[127:64](RD) |
|||
MC0_DDR2_CTRL_0x2b0: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi2_fbck[ 63: 0](RD) |
|||
MC0_DDR2_CTRL_0x2b8: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi2_fbck[127:64](RD) |
|||
MC0_DDR2_CTRL_0x2c0: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi3_fbck[ 63: 0](RD) |
|||
MC0_DDR2_CTRL_0x2c8: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi3_fbck[127:64](RD) |
|||
MC0_DDR2_CTRL_0x2d0: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi4_fbck[ 63: 0](RD) |
|||
MC0_DDR2_CTRL_0x2d8: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi4_fbck[127:64](RD) |
|||
MC0_DDR2_CTRL_0x2e0: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_cmd_fbck0[ 63: 0](RD) |
|||
MC0_DDR2_CTRL_0x2e8: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_cmd_fbck0[127:64](RD) |
|||
MC0_DDR2_CTRL_0x2f0: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_cmd_fbck1[ 63: 0](RD) |
|||
MC0_DDR2_CTRL_0x2f8: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_cmd_fbck1[127:64](RD) |
|||
MC0_DDR2_CTRL_0x300: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_cmd_fbck2[ 63: 0](RD) |
|||
MC0_DDR2_CTRL_0x308: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_cmd_fbck2[127:64](RD) |
|||
MC0_DDR2_CTRL_0x310: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_cmd_fbck3[ 63: 0](RD) |
|||
MC0_DDR2_CTRL_0x318: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_cmd_fbck3[127:64](RD) |
|||
|
|||
ddr2_RDIMM_reg_data: |
|||
ddr2_RDIMM_reg_data_mc1: |
|||
|
|||
//DDR3 param |
|||
.rdata |
|||
.align 5 |
|||
ddr3_reg_data: |
|||
ddr3_reg_data_mc1: |
|||
|
|||
MC0_DDR3_CTRL_0x000: .dword 0x0000000000000000 |
|||
//XXXX pm_dll_value_0(RD) XXXX pm_dll_value_ck(RD) XXXX pm_dll_init_done(RD) XXXX pm_version(RD) |
|||
MC0_DDR3_CTRL_0x008: .dword 0x0000000000000000 |
|||
//XXXX pm_dll_value_4(RD) XXXX pm_dll_value_3 (RD) XXXX pm_dll_value_2(RD) XXXX pm_dll_value_1(RD) |
|||
MC0_DDR3_CTRL_0x010: .dword 0x0000000000000000 |
|||
//XXXX pm_dll_value_8(RD) XXXX pm_dll_value_7 (RD) XXXX pm_dll_value_6(RD) XXXX pm_dll_value_5(RD) |
|||
//MC0_DDR3_CTRL_0x018: .dword 0x5252525216100000 |
|||
//MC0_DDR3_CTRL_0x018: .dword 0x4040404016100000 |
|||
//MC0_DDR3_CTRL_0x018: .dword 0x3030303016100000 |
|||
MC0_DDR3_CTRL_0x018: .dword 0x2525252516100000 |
|||
//_00000000 pm_dll_ck_3 _00000000 pm_dll_ck_2 _00000000 pm_dll_ck_1 _00000000 pm_dll_ck_0 _00000000 pm_dll_increment _00000000 pm_dll_start_point _0000000_0 pm_dll_bypass _0000000_0 pm_init_start |
|||
MC0_DDR3_CTRL_0x020: .dword 0x0201000301000000 |
|||
//0000_0000 pm_dq_oe_end_0 0000_0000 pm_dq_oe_begin_0 000000_00 pm_dq_stop_edge_0 000000_00 pm_dq_start_edge_0 0000000_0 pm_rddata_delay_0 0000000_0 pm_rddqs_lt_half_0 0000000_0 pm_wrdqs_lt_half_0 0000000_0 pm_wrdq_lt_half_0 |
|||
MC0_DDR3_CTRL_0x028: .dword 0x0303020202010101 |
|||
//0000_0000 pm_rd_oe_end_0 0000_0000 pm_rd_oe_begin_0 000000_00 pm_rd_stop_edge_0 000000_00 pm_rd_start_edge_0 0000_0000 pm_dqs_oe_end_0 0000_0000 pm_dqs_oe_begin_0 000000_00 pm_dqs_stop_edge_0 000000_00 pm_dqs_start_edge_0 |
|||
MC0_DDR3_CTRL_0x030: .dword 0x0000000004030000 |
|||
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_0 0000_0000 pm_odt_oe_end_0 0000_0000 pm_odt_oe_begin_0 000000_00 pm_odt_stop_edge_0 000000_00 pm_odt_start_edge_0 |
|||
MC0_DDR3_CTRL_0x038: .dword 0x0000002020056500 |
|||
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_0 _00000000 pm_dll_rddqs_p_0 _00000000 pm_dll_wrdqs_0 _00000000 pm_dll_wrdata_0 _00000000 pm_dll_gate_0 |
|||
MC0_DDR3_CTRL_0x040: .dword 0x0201000301000000 |
|||
//0000_0000 pm_dq_oe_end_1 0000_0000 pm_dq_oe_begin_1 000000_00 pm_dq_stop_edge_1 000000_00 pm_dq_start_edge_1 0000000_0 pm_rddata_delay_1 0000000_0 pm_rddqs_lt_half_1 0000000_0 pm_wrdqs_lt_half_1 0000000_0 pm_wrdq_lt_half_1 |
|||
MC0_DDR3_CTRL_0x048: .dword 0x0303020202010101 |
|||
//0000_0000 pm_rd_oe_end_1 0000_0000 pm_rd_oe_begin_1 000000_00 pm_rd_stop_edge_1 000000_00 pm_rd_start_edge_1 0000_0000 pm_dqs_oe_end_1 0000_0000 pm_dqs_oe_begin_1 000000_00 pm_dqs_stop_edge_1 000000_00 pm_dqs_start_edge_1 |
|||
MC0_DDR3_CTRL_0x050: .dword 0x0000000004030000 |
|||
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_1 0000_0000 pm_odt_oe_end_1 0000_0000 pm_odt_oe_begin_1 000000_00 pm_odt_stop_edge_1 000000_00 pm_odt_start_edge_1 |
|||
MC0_DDR3_CTRL_0x058: .dword 0x0000002020056500 |
|||
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_1 _00000000 pm_dll_rddqs_p_1 _00000000 pm_dll_wrdqs_1 _00000000 pm_dll_wrdata_1 _00000000 pm_dll_gate_1 |
|||
MC0_DDR3_CTRL_0x060: .dword 0x0201000301000000 |
|||
//0000_0000 pm_dq_oe_end_2 0000_0000 pm_dq_oe_begin_2 000000_00 pm_dq_stop_edge_2 000000_00 pm_dq_start_edge_2 0000000_0 pm_rddata_delay_2 0000000_0 pm_rddqs_lt_half_2 0000000_0 pm_wrdqs_lt_half_2 0000000_0 pm_wrdq_lt_half_2 |
|||
MC0_DDR3_CTRL_0x068: .dword 0x0303020202010101 |
|||
//0000_0000 pm_rd_oe_end_2 0000_0000 pm_rd_oe_begin_2 000000_00 pm_rd_stop_edge_2 000000_00 pm_rd_start_edge_2 0000_0000 pm_dqs_oe_end_2 0000_0000 pm_dqs_oe_begin_2 000000_00 pm_dqs_stop_edge_2 000000_00 pm_dqs_start_edge_2 |
|||
MC0_DDR3_CTRL_0x070: .dword 0x0000000004030000 |
|||
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_2 0000_0000 pm_odt_oe_end_2 0000_0000 pm_odt_oe_begin_2 000000_00 pm_odt_stop_edge_2 000000_00 pm_odt_start_edge_2 |
|||
MC0_DDR3_CTRL_0x078: .dword 0x0000002020056500 |
|||
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_2 _00000000 pm_dll_rddqs_p_2 _00000000 pm_dll_wrdqs_2 _00000000 pm_dll_wrdata_2 _00000000 pm_dll_gate_2 |
|||
MC0_DDR3_CTRL_0x080: .dword 0x0201000301000000 |
|||
//0000_0000 pm_dq_oe_end_3 0000_0000 pm_dq_oe_begin_3 000000_00 pm_dq_stop_edge_3 000000_00 pm_dq_start_edge_3 0000000_0 pm_rddata_delay_3 0000000_0 pm_rddqs_lt_half_3 0000000_0 pm_wrdqs_lt_half_3 0000000_0 pm_wrdq_lt_half_3 |
|||
MC0_DDR3_CTRL_0x088: .dword 0x0303020202010101 |
|||
//0000_0000 pm_rd_oe_end_3 0000_0000 pm_rd_oe_begin_3 000000_00 pm_rd_stop_edge_3 000000_00 pm_rd_start_edge_3 0000_0000 pm_dqs_oe_end_3 0000_0000 pm_dqs_oe_begin_3 000000_00 pm_dqs_stop_edge_3 000000_00 pm_dqs_start_edge_3 |
|||
MC0_DDR3_CTRL_0x090: .dword 0x0000000004030000 |
|||
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_3 0000_0000 pm_odt_oe_end_3 0000_0000 pm_odt_oe_begin_3 000000_00 pm_odt_stop_edge_3 000000_00 pm_odt_start_edge_3 |
|||
MC0_DDR3_CTRL_0x098: .dword 0x0000002020056500 |
|||
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_3 _00000000 pm_dll_rddqs_p_3 _00000000 pm_dll_wrdqs_3 _00000000 pm_dll_wrdata_3 _00000000 pm_dll_gate_3 |
|||
MC0_DDR3_CTRL_0x0a0: .dword 0x0201000301000000 |
|||
//0000_0000 pm_dq_oe_end_4 0000_0000 pm_dq_oe_begin_4 000000_00 pm_dq_stop_edge_4 000000_00 pm_dq_start_edge_4 0000000_0 pm_rddata_delay_4 0000000_0 pm_rddqs_lt_half_4 0000000_0 pm_wrdqs_lt_half_4 0000000_0 pm_wrdq_lt_half_4 |
|||
MC0_DDR3_CTRL_0x0a8: .dword 0x0303020202010101 |
|||
//0000_0000 pm_rd_oe_end_4 0000_0000 pm_rd_oe_begin_4 000000_00 pm_rd_stop_edge_4 000000_00 pm_rd_start_edge_4 0000_0000 pm_dqs_oe_end_4 0000_0000 pm_dqs_oe_begin_4 000000_00 pm_dqs_stop_edge_4 000000_00 pm_dqs_start_edge_4 |
|||
MC0_DDR3_CTRL_0x0b0: .dword 0x0000000004030000 |
|||
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_4 0000_0000 pm_odt_oe_end_4 0000_0000 pm_odt_oe_begin_4 000000_00 pm_odt_stop_edge_4 000000_00 pm_odt_start_edge_4 |
|||
MC0_DDR3_CTRL_0x0b8: .dword 0x0000002020056500 |
|||
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_4 _00000000 pm_dll_rddqs_p_4 _00000000 pm_dll_wrdqs_4 _00000000 pm_dll_wrdata_4 _00000000 pm_dll_gate_4 |
|||
MC0_DDR3_CTRL_0x0c0: .dword 0x0201000301000000 |
|||
//0000_0000 pm_dq_oe_end_5 0000_0000 pm_dq_oe_begin_5 000000_00 pm_dq_stop_edge_5 000000_00 pm_dq_start_edge_5 0000000_0 pm_rddata_delay_5 0000000_0 pm_rddqs_lt_half_5 0000000_0 pm_wrdqs_lt_half_5 0000000_0 pm_wrdq_lt_half_5 |
|||
MC0_DDR3_CTRL_0x0c8: .dword 0x0303020202010101 |
|||
//0000_0000 pm_rd_oe_end_5 0000_0000 pm_rd_oe_begin_5 000000_00 pm_rd_stop_edge_5 000000_00 pm_rd_start_edge_5 0000_0000 pm_dqs_oe_end_5 0000_0000 pm_dqs_oe_begin_5 000000_00 pm_dqs_stop_edge_5 000000_00 pm_dqs_start_edge_5 |
|||
MC0_DDR3_CTRL_0x0d0: .dword 0x0000000004030000 |
|||
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_5 0000_0000 pm_odt_oe_end_5 0000_0000 pm_odt_oe_begin_5 000000_00 pm_odt_stop_edge_5 000000_00 pm_odt_start_edge_5 |
|||
MC0_DDR3_CTRL_0x0d8: .dword 0x0000002020056500 |
|||
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_5 _00000000 pm_dll_rddqs_p_5 _00000000 pm_dll_wrdqs_5 _00000000 pm_dll_wrdata_5 _00000000 pm_dll_gate_5 |
|||
MC0_DDR3_CTRL_0x0e0: .dword 0x0201000301000000 |
|||
//0000_0000 pm_dq_oe_end_6 0000_0000 pm_dq_oe_begin_6 000000_00 pm_dq_stop_edge_6 000000_00 pm_dq_start_edge_6 0000000_0 pm_rddata_delay_6 0000000_0 pm_rddqs_lt_half_6 0000000_0 pm_wrdqs_lt_half_6 0000000_0 pm_wrdq_lt_half_6 |
|||
MC0_DDR3_CTRL_0x0e8: .dword 0x0303020202010101 |
|||
//0000_0000 pm_rd_oe_end_6 0000_0000 pm_rd_oe_begin_6 000000_00 pm_rd_stop_edge_6 000000_00 pm_rd_start_edge_6 0000_0000 pm_dqs_oe_end_6 0000_0000 pm_dqs_oe_begin_6 000000_00 pm_dqs_stop_edge_6 000000_00 pm_dqs_start_edge_6 |
|||
MC0_DDR3_CTRL_0x0f0: .dword 0x0000000004030000 |
|||
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_6 0000_0000 pm_odt_oe_end_6 0000_0000 pm_odt_oe_begin_6 000000_00 pm_odt_stop_edge_6 000000_00 pm_odt_start_edge_6 |
|||
MC0_DDR3_CTRL_0x0f8: .dword 0x0000002020056500 |
|||
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_6 _00000000 pm_dll_rddqs_p_6 _00000000 pm_dll_wrdqs_6 _00000000 pm_dll_wrdata_6 _00000000 pm_dll_gate_6 |
|||
MC0_DDR3_CTRL_0x100: .dword 0x0201000301000000 |
|||
//0000_0000 pm_dq_oe_end_7 0000_0000 pm_dq_oe_begin_7 000000_00 pm_dq_stop_edge_7 000000_00 pm_dq_start_edge_7 0000000_0 pm_rddata_delay_7 0000000_0 pm_rddqs_lt_half_7 0000000_0 pm_wrdqs_lt_half_7 0000000_0 pm_wrdq_lt_half_7 |
|||
MC0_DDR3_CTRL_0x108: .dword 0x0303020202010101 |
|||
//0000_0000 pm_rd_oe_end_7 0000_0000 pm_rd_oe_begin_7 000000_00 pm_rd_stop_edge_7 000000_00 pm_rd_start_edge_7 0000_0000 pm_dqs_oe_end_7 0000_0000 pm_dqs_oe_begin_7 000000_00 pm_dqs_stop_edge_7 000000_00 pm_dqs_start_edge_7 |
|||
MC0_DDR3_CTRL_0x110: .dword 0x0000000004030000 |
|||
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_7 0000_0000 pm_odt_oe_end_7 0000_0000 pm_odt_oe_begin_7 000000_00 pm_odt_stop_edge_7 000000_00 pm_odt_start_edge_7 |
|||
MC0_DDR3_CTRL_0x118: .dword 0x0000002020056500 |
|||
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_7 _00000000 pm_dll_rddqs_p_7 _00000000 pm_dll_wrdqs_7 _00000000 pm_dll_wrdata_7 _00000000 pm_dll_gate_7 |
|||
MC0_DDR3_CTRL_0x120: .dword 0x0201000301000000 |
|||
//0000_0000 pm_dq_oe_end_8 0000_0000 pm_dq_oe_begin_8 000000_00 pm_dq_stop_edge_8 000000_00 pm_dq_start_edge_8 0000000_0 pm_rddata_delay_8 0000000_0 pm_rddqs_lt_half_8 0000000_0 pm_wrdqs_lt_half_8 0000000_0 pm_wrdq_lt_half_8 |
|||
MC0_DDR3_CTRL_0x128: .dword 0x0303020202010101 |
|||
//0000_0000 pm_rd_oe_end_8 0000_0000 pm_rd_oe_begin_8 000000_00 pm_rd_stop_edge_8 000000_00 pm_rd_start_edge_8 0000_0000 pm_dqs_oe_end_8 0000_0000 pm_dqs_oe_begin_8 000000_00 pm_dqs_stop_edge_8 000000_00 pm_dqs_start_edge_8 |
|||
MC0_DDR3_CTRL_0x130: .dword 0x0000000004030000 |
|||
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_8 0000_0000 pm_odt_oe_end_8 0000_0000 pm_odt_oe_begin_8 000000_00 pm_odt_stop_edge_8 000000_00 pm_odt_start_edge_8 |
|||
MC0_DDR3_CTRL_0x138: .dword 0x00000020207f6000 |
|||
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_8 _00000000 pm_dll_rddqs_p_8 _00000000 pm_dll_wrdqs_8 _00000000 pm_dll_wrdata_8 _00000000 pm_dll_gate_8 |
|||
MC0_DDR3_CTRL_0x140: .dword 0x0403000001ff01ff |
|||
//00000_000 pm_pad_ocd_clk 00000_000 pm_pad_ocd_ctl 0000000_0 pm_pad_ocd_dqs 0000000_0 pm_pad_ocd_dq 0000000_0_00000000 pm_pad_enzi 0000000_0 pm_pad_en_ctl _00000000 pm_pad_en_clk |
|||
MC0_DDR3_CTRL_0x148: .dword 0x0000000000010100 |
|||
//_0000 pm_pad_adj_ncode_dq _0000 pm_pad_adj_pcode_dq 00000 _0 pm_pad_outodt_dq _0 pm_pad_slewrate_dq _0 pm_pad_code_dq _0000 pm_pad_adj_ncode_dq _0000 pm_pad_adj_pcode_dq 00000 _0 pm_pad_outodt_dq _0 pm_pad_slewrate_dq _0 00000000 0000000_0 pm_pad_vref_internal 0000000_0 pm_pad_odt_se 0000000_0 pm_pad_modezi1v8 |
|||
MC0_DDR3_CTRL_0x150: .dword 0x00000000f0020000 |
|||
//hXXXX _0000 pm_pad_adj_ncode_clk _0000 pm_pad_adj_pcode_clk 00000 _0 pm_pad_outodt_clk _0 pm_pad_slewrate_clk _0 pm_pad_code_clk _0000 pm_pad_adj_ncode_cmd _0000 pm_pad_adj_pcode_cmd 00000 _0 pm_pad_outodt_cmd _0 pm_pad_slewrate_cmd _0 pm_pad_code_cmd _0000 pm_pad_adj_ncode_addr _0000 pm_pad_adj_pcode_addr 00000 _0 pm_pad_outodt_addr _0 pm_pad_slewrate_addr _0 pm_pad_code_addr |
|||
MC0_DDR3_CTRL_0x158: .dword 0x00000000f0000000 |
|||
//hXXXXXXXX (RD) _0000 pm_pad_comp_ncode_i _0000 pm_pad_comp_pcode_i 0000000_0 pm_pad_comp_mode 0000000_0 pm_pad_comp_tm 0000000_0 pm_pad_comp_pd |
|||
MC0_DDR3_CTRL_0x160: .dword 0x0000000000010101 |
|||
//MC0_DDR3_CTRL_0x160: .dword 0x0000000000000001 |
|||
//0000000_0_00000000 pm_rdfifo_empty(RD) 0000000_0_00000000 pm_overflow(RD) 0000_0000 pm_dram_init(RD) 0000000_0 pm_rdfifo_valid 000000_00 pm_cmd_timing 0000000_0 pm_ddr3_mode |
|||
MC0_DDR3_CTRL_0x168: .dword 0x140a000707030101 |
|||
//hXX (RD) 0000_0000 pm_addr_mirror 000000_00 pm_cmd_delay _00000000 pm_burst_length 00000_000 pm_bank 0000_0000 pm_cs_zq 0000_0000 pm_cs_mrs 0000_0000 pm_cs_enable |
|||
//MC0_DDR3_CTRL_0x170: .dword 0x0000000001ff01ff |
|||
MC0_DDR3_CTRL_0x170: .dword 0x8421050084120501 |
|||
//_00000000_00000000 pm_odt_wr_cs_map 0000_0000 pm_odt_wr_length 0000_0000 pm_odt_wr_delay _00000000_00000000 pm_odt_rd_cs_map 0000_0000 pm_odt_rd_length 0000_0000 pm_odt_rd_delay |
|||
MC0_DDR3_CTRL_0x178: .dword 0x0000000000000000 |
|||
//hXXXXXXXXXXXXXXXX (RD) |
|||
MC0_DDR3_CTRL_0x180: .dword 0x0000000001100000 |
|||
//_00000000 pm_lvl_resp_0(RD) 0000000_0 pm_lvl_done(RD) 0000000_0 pm_lvl_ready(RD) 00000000 0000_0000 pm_lvl_cs _00000000 pm_tLVL_DELAY 0000000_0 pm_leveling_req(WR) 000000_00 pm_leveling_mode |
|||
MC0_DDR3_CTRL_0x188: .dword 0x0000000000000000 |
|||
//_00000000 pm_lvl_resp_8(RD) _00000000 pm_lvl_resp_7(RD) _00000000 _pm_lvl_resp_6(RD) _00000000 pm_lvl_resp_5(RD) _00000000 pm_lvl_resp_4(RD) _00000000 pm_lvl_resp_3(RD) _00000000 pm_lvl_resp_2(RD) _00000000 pm_lvl_resp_1(RD) |
|||
|
|||
//CMD CONFIG |
|||
MC0_DDR3_CTRL_0x190: .dword 0x0000000000000000 |
|||
//_00000000_00000000 pm_cmd_a 00000_000 pm_cmd_ba 00000_000 pm_cmd_cmd 0000_0000 pm_cmd_cs 0000000_0 pm_status_cmd(RD) 0000000_0 pm_cmd_req(WR) 0000000_0 pm_command |
|||
MC0_DDR3_CTRL_0x198: .dword 0x0000000000000000 |
|||
//00000000 00000000 0000_0000 pm_status_sref(RD) 0000_0000 pm_srefresh_req 0000000_0 pm_pre_all_done(RD) 0000000_0 pm_pre_all_req(WR) 0000000_0 pm_mrs_done(RD) 0000000_0 pm_mrs_req(WR) |
|||
MC0_DDR3_CTRL_0x1a0: .dword 0x0000000800060940 |
|||
//_00000000_00000000 pm_mr_3_cs_0 _00000000_00000000 pm_mr_2_cs_0 _00000000_00000000 pm_mr_1_cs_0 _00000000_00000000 pm_mr_0_cs_0 |
|||
MC0_DDR3_CTRL_0x1a8: .dword 0x0000000800060940 |
|||
//_00000000_00000000 pm_mr_3_cs_1 _00000000_00000000 pm_mr_2_cs_1 _00000000_00000000 pm_mr_1_cs_1 _00000000_00000000 pm_mr_0_cs_1 |
|||
MC0_DDR3_CTRL_0x1b0: .dword 0x0000000800060940 |
|||
//_00000000_00000000 pm_mr_3_cs_2 _00000000_00000000 pm_mr_2_cs_2 _00000000_00000000 pm_mr_1_cs_2 _00000000_00000000 pm_mr_0_cs_2 |
|||
MC0_DDR3_CTRL_0x1b8: .dword 0x0000000800060940 |
|||
//_00000000_00000000 pm_mr_3_cs_3 _00000000_00000000 pm_mr_2_cs_3 _00000000_00000000 pm_mr_1_cs_3 _00000000_00000000 pm_mr_0_cs_3 |
|||
MC0_DDR3_CTRL_0x1c0: .dword 0x1b425b0802041905 |
|||
//_00000000 pm_tRESET _00000000 pm_tCKE _00000000 pm_tXPR _00000000 pm_tMOD _00000000 pm_tZQCL _00000000 pm_tZQ_CMD _00000000 pm_tWLDQSEN 000_00000 pm_tRDDATA |
|||
MC0_DDR3_CTRL_0x1c8: .dword 0x10040808103a4080 |
|||
//00_000000 pm_tFAW 0000_0000 pm_tRRD 0000_0000 pm_tRCD _00000000 pm_tRP _00000000 pm_tREF _00000000 pm_tRFC _00000000 pm_tZQCS _00000000 pm_tZQperiod |
|||
MC0_DDR3_CTRL_0x1d0: .dword 0x0802090302000014 |
|||
//0000_0000 pm_tODTL _00000000 pm_tXSRD 0000_0000 pm_tPHY_RDLAT 000_00000 pm_tPHY_WRLAT 000000_00_00000000_00000000 pm_tRAS_max 00_000000 pm_tRAS_min |
|||
MC0_DDR3_CTRL_0x1d8: .dword 0x0d04080408060404 |
|||
//_00000000 pm_tXPDLL _00000000 pm_tXP 000_00000 pm_tWR 0000_0000 pm_tRTP 0000_0000 pm_tRL 0000_0000 pm_tWL 0000_0000 pm_tCCD 0000_0000 pm_tWTR |
|||
MC0_DDR3_CTRL_0x1e0: .dword 0x0503000000000000 |
|||
//00_000000 pm_tW2R_diffcs_dly 00_000000 pm_tW2W_diffcs_adj_dly 00_000000 pm_tR2P_sameba_adj_dly 00_000000 pm_tW2P_sameba_adj_dly 00_000000 pm_tR2R_sameba_adj_dly 00_000000 pm_tR2W_sameba_adj_dly 00_000000 pm_tW2R_sameba_adj_dly 00_000000 pm_tW2W_sameba_adj_dly |
|||
MC0_DDR3_CTRL_0x1e8: .dword 0x0309000000000000 |
|||
//00_000000 pm_tR2R_diffcs_adj_dly 00_000000 pm_tR2W_diffcs_dly 00_000000 pm_tR2P_samecs_dly 00_000000 pm_tW2P_samecs_dly 00_000000 pm_tR2R_samecs_adj_dly 00_000000 pm_tR2W_samecs_adj_dly 00_000000 pm_tW2R_samecs_adj_dly 00_000000 pm_tW2W_samecs_adj_dly |
|||
MC0_DDR3_CTRL_0x1f0: .dword 0x000801e4ff000101 |
|||
//0000_0000 pm_power_up _00000000 pm_age_step _00000000 pm_tCPDED _00000000 pm_cs_map _00000000 pm_bs_config 00000_000 pm_channel_32 pm_channel_16 pm_nc 0000_0000 pm_pr_r2w 0000000_0 pm_placement_en |
|||
MC0_DDR3_CTRL_0x1f8: .dword 0x0000000004081001 |
|||
//0000_0000 pm_hardware_pd_3 0000_0000 pm_hardware_pd_2 0000_0000 pm_hardware_pd_1 0000_0000 pm_hardware_pd_0 00_000000 pm_credit_16 00_000000 pm_credit_32 00_000000 pm_credit_64 0000000_0 pm_selection_en |
|||
MC0_DDR3_CTRL_0x200: .dword 0x0c000c000c000c00 |
|||
//0000_0000_00000000 pm_cmdq_age_16 0000_0000_00000000 pm_cmdq_age_32 0000_0000_00000000 pm_cmdq_age_64 _00000000 pm_tCKESR _00000000 pm_tRDPDEN |
|||
MC0_DDR3_CTRL_0x208: .dword 0x0c000c0000000000 |
|||
//0000_0000_00000000 pm_wrfifo_age 0000_0000_00000000 pm_rdfifo_age 0000_0000 pm_power_status_3 0000_0000 pm_power_status_2 0000_0000 pm_power_status_1 0000_0000 pm_power_status_0 |
|||
MC0_DDR3_CTRL_0x210: .dword 0x0008010f00030006 |
|||
//_00000000_00000000 pm_active_age 0000000_0 pm_cs_place_0 0000_0000 pm_addr_win_0 000000_00 pm_cs_diff_0 00000_000 pm_row_diff_0 000000_00 pm_ba_diff_0 00000_000 pm_col_diff_0 |
|||
MC0_DDR3_CTRL_0x218: .dword 0x0008000b00030106 |
|||
//_00000000_00000000 pm_fastpd_age 0000000_0 pm_cs_place_1 0000_0000 pm_addr_win_1 000000_00 pm_cs_diff_1 00000_000 pm_row_diff_1 000000_00 pm_ba_diff_1 00000_000 pm_col_diff_1 |
|||
MC0_DDR3_CTRL_0x220: .dword 0x0008000b00030106 |
|||
//_00000000_00000000 pm_slowpd_age 0000000_0 pm_cs_place_2 0000_0000 pm_addr_win_2 000000_00 pm_cs_diff_2 00000_000 pm_row_diff_2 000000_00 pm_ba_diff_2 00000_000 pm_col_diff_2 |
|||
MC0_DDR3_CTRL_0x228: .dword 0x0008000b00030106 |
|||
//_00000000_00000000 pm_selfref_age 0000000_0 pm_cs_place_3 0000_0000 pm_addr_win_3 000000_00 pm_cs_diff_3 00000_000 pm_row_diff_3 000000_00 pm_ba_diff_3 00000_000 pm_col_diff_3 |
|||
MC0_DDR3_CTRL_0x230: .dword 0x0fff000000000000 |
|||
//0000_0000_00000000_00000000_00000000 pm_addr_mask_0 0000_0000_00000000_00000000_00000000 pm_addr_base_0 |
|||
MC0_DDR3_CTRL_0x238: .dword 0x0ffffe000000ff00 |
|||
//0000_0000_00000000_00000000_00000000 pm_addr_mask_1 0000_0000_00000000_00000000_00000000 pm_addr_base_1 |
|||
MC0_DDR3_CTRL_0x240: .dword 0x0ffffe000000ff00 |
|||
//0000_0000_00000000_00000000_00000000 pm_addr_mask_2 0000_0000_00000000_00000000_00000000 pm_addr_base_2 |
|||
MC0_DDR3_CTRL_0x248: .dword 0x0ffffe000000ff00 |
|||
//0000_0000_00000000_00000000_00000000 pm_addr_mask_3 0000_0000_00000000_00000000_00000000 pm_addr_base_3 |
|||
MC0_DDR3_CTRL_0x250: .dword 0x0000000000000000 |
|||
//00000000 _00_00_00_00 pm_cmd_monitor_3_2_1_0 000000_00_00000000 pm_axi_monitor _00000000 pm_ecc_code(RD) 0000_0_000 pm_int_trigger pm_ecc_enable 000000_00 pm_int_vector 000000_00 pm_int_enable |
|||
MC0_DDR3_CTRL_0x258: .dword 0x0000000000000000 |
|||
//XXXXXXXXXXXXXXXX (RD) |
|||
MC0_DDR3_CTRL_0x260: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_ecc_addr(RD) |
|||
MC0_DDR3_CTRL_0x268: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_ecc_data(RD) |
|||
MC0_DDR3_CTRL_0x270: .dword 0x0000001000000000 |
|||
//000000_00 pm_lpbk_ecc_mask(RD) 0_0000000_00000000_00000000 pm_prbs_init 0000000_0 pm_lpbk_error(RD) 0000000_0 pm_prbs_23 0000000_0 pm_lpbk_start 0000000_0 pm_lpbk_en |
|||
MC0_DDR3_CTRL_0x278: .dword 0x0000000000000000 |
|||
//_00000000_00000000 pm_lpbk_ecc(RD) _00000000_00000000 pm_lpbk_data_mask(RD) _00000000_00000000 pm_lpbk_correct(RD) _00000000_00000000 pm_lpbk_counter(RD) |
|||
MC0_DDR3_CTRL_0x280: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_lpbk_data[ 63: 0](RD) |
|||
MC0_DDR3_CTRL_0x288: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_lpbk_data[127:64](RD) |
|||
|
|||
//Monitor fbck |
|||
MC0_DDR3_CTRL_0x290: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi0_fbck[ 63: 0](RD) |
|||
MC0_DDR3_CTRL_0x298: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi0_fbck[127:64](RD) |
|||
MC0_DDR3_CTRL_0x2a0: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi1_fbck[ 63: 0](RD) |
|||
MC0_DDR3_CTRL_0x2a8: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi1_fbck[127:64](RD) |
|||
MC0_DDR3_CTRL_0x2b0: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi2_fbck[ 63: 0](RD) |
|||
MC0_DDR3_CTRL_0x2b8: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi2_fbck[127:64](RD) |
|||
MC0_DDR3_CTRL_0x2c0: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi3_fbck[ 63: 0](RD) |
|||
MC0_DDR3_CTRL_0x2c8: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi3_fbck[127:64](RD) |
|||
MC0_DDR3_CTRL_0x2d0: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi4_fbck[ 63: 0](RD) |
|||
MC0_DDR3_CTRL_0x2d8: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi4_fbck[127:64](RD) |
|||
MC0_DDR3_CTRL_0x2e0: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_cmd_fbck0[ 63: 0](RD) |
|||
MC0_DDR3_CTRL_0x2e8: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_cmd_fbck0[127:64](RD) |
|||
MC0_DDR3_CTRL_0x2f0: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_cmd_fbck1[ 63: 0](RD) |
|||
MC0_DDR3_CTRL_0x2f8: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_cmd_fbck1[127:64](RD) |
|||
MC0_DDR3_CTRL_0x300: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_cmd_fbck2[ 63: 0](RD) |
|||
MC0_DDR3_CTRL_0x308: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_cmd_fbck2[127:64](RD) |
|||
MC0_DDR3_CTRL_0x310: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_cmd_fbck3[ 63: 0](RD) |
|||
MC0_DDR3_CTRL_0x318: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_cmd_fbck3[127:64](RD) |
|||
MC0_DDR3_CTRL_0x320: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX 0000_0000 pm_REF_low |
|||
MC0_DDR3_CTRL_0x328: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX (RD) |
|||
MC0_DDR3_CTRL_0x330: .dword 0x0000001000010400 |
|||
//0000000_0 pm_stat_en 0_0000000 pm_rdbuffer_max(RD) 0000000_0 pm_retry 00_000000 pm_wr_pkg_num 0000000_0 pm_rwq_rb 0000000_0 pm_stb_en 000_00000 pm_addr_new 0000_0000 pm_tRDQidle |
|||
MC0_DDR3_CTRL_0x338: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX 0000_0000 pm_fifo_depth 00000000_00000000_00000000_00000000 pm_retry_cnt(RD) |
|||
MC0_DDR3_CTRL_0x340: .dword 0x0030d40000070f01 |
|||
//00000000_00000000_00000000_00000000 pm_tREFretention 0000_0000 pm_ref_num 00000000 pm_tREF_IDLE 0000000_0 pm_ref_sch_en |
|||
MC0_DDR3_CTRL_0x348: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX |
|||
MC0_DDR3_CTRL_0x350: .dword 0xffffffffffffffff |
|||
//_XXXXXXXXXXXXXXXX pm_lpbk_data_en |
|||
MC0_DDR3_CTRL_0x358: .dword 0x000000000001ffff |
|||
//0000000_0 pm_lpbk_ecc_mask_en 00000000 pm_lpbk_ecc_en 00000000 pm_lpbk_data_mask_en |
|||
MC0_DDR3_CTRL_0x360: .dword 0x0000000000000000 |
|||
//00000000 pm_ecc_int_cnt_fatal 00000000 pm_ecc_int_cnt_error 00000000 pm_ecc_cnt_cs_3 00000000 pm_ecc_cnt_cs_2 00000000 pm_ecc_cnt_cs_1 00000000 pm_ecc_cnt_cs_0 |
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MC0_DDR3_CTRL_0x368: .dword 0x0000000000000000 |
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//_XXXXXXXXXXXXXXXX |
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|
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ddr3_RDIMM_reg_data: |
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ddr3_RDIMM_reg_data_mc1: |
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MC0_DDR3_RDIMM_CTRL_0x000: .dword 0x0000000000000000 |
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//XXXX pm_dll_value_0(RD) XXXX pm_dll_value_ck(RD) XXXX pm_dll_init_done(RD) XXXX pm_version(RD) |
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MC0_DDR3_RDIMM_CTRL_0x008: .dword 0x0000000000000000 |
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//XXXX pm_dll_value_4(RD) XXXX pm_dll_value_3 (RD) XXXX pm_dll_value_2(RD) XXXX pm_dll_value_1(RD) |
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MC0_DDR3_RDIMM_CTRL_0x010: .dword 0x0000000000000000 |
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//XXXX pm_dll_value_8(RD) XXXX pm_dll_value_7 (RD) XXXX pm_dll_value_6(RD) XXXX pm_dll_value_5(RD) |
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MC0_DDR3_RDIMM_CTRL_0x018: .dword 0x5252525216100000 |
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//_00000000 pm_dll_ck_3 _00000000 pm_dll_ck_2 _00000000 pm_dll_ck_1 _00000000 pm_dll_ck_0 _00000000 pm_dll_increment _00000000 pm_dll_start_point _0000000_0 pm_dll_bypass _0000000_0 pm_init_start |
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MC0_DDR3_RDIMM_CTRL_0x020: .dword 0x0201000301000000 |
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//0000_0000 pm_dq_oe_end_0 0000_0000 pm_dq_oe_begin_0 000000_00 pm_dq_stop_edge_0 000000_00 pm_dq_start_edge_0 0000000_0 pm_rddata_delay_0 0000000_0 pm_rddqs_lt_half_0 0000000_0 pm_wrdqs_lt_half_0 0000000_0 pm_wrdq_lt_half_0 |
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MC0_DDR3_RDIMM_CTRL_0x028: .dword 0x0303020202010101 |
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//0000_0000 pm_rd_oe_end_0 0000_0000 pm_rd_oe_begin_0 000000_00 pm_rd_stop_edge_0 000000_00 pm_rd_start_edge_0 0000_0000 pm_dqs_oe_end_0 0000_0000 pm_dqs_oe_begin_0 000000_00 pm_dqs_stop_edge_0 000000_00 pm_dqs_start_edge_0 |
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MC0_DDR3_RDIMM_CTRL_0x030: .dword 0x0000000004030000 |
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//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_0 0000_0000 pm_odt_oe_end_0 0000_0000 pm_odt_oe_begin_0 000000_00 pm_odt_stop_edge_0 000000_00 pm_odt_start_edge_0 |
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MC0_DDR3_RDIMM_CTRL_0x038: .dword 0x0000002020056500 |
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//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_0 _00000000 pm_dll_rddqs_p_0 _00000000 pm_dll_wrdqs_0 _00000000 pm_dll_wrdata_0 _00000000 pm_dll_gate_0 |
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MC0_DDR3_RDIMM_CTRL_0x040: .dword 0x0201000301000000 |
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//0000_0000 pm_dq_oe_end_1 0000_0000 pm_dq_oe_begin_1 000000_00 pm_dq_stop_edge_1 000000_00 pm_dq_start_edge_1 0000000_0 pm_rddata_delay_1 0000000_0 pm_rddqs_lt_half_1 0000000_0 pm_wrdqs_lt_half_1 0000000_0 pm_wrdq_lt_half_1 |
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MC0_DDR3_RDIMM_CTRL_0x048: .dword 0x0303020202010101 |
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//0000_0000 pm_rd_oe_end_1 0000_0000 pm_rd_oe_begin_1 000000_00 pm_rd_stop_edge_1 000000_00 pm_rd_start_edge_1 0000_0000 pm_dqs_oe_end_1 0000_0000 pm_dqs_oe_begin_1 000000_00 pm_dqs_stop_edge_1 000000_00 pm_dqs_start_edge_1 |
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MC0_DDR3_RDIMM_CTRL_0x050: .dword 0x0000000004030000 |
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//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_1 0000_0000 pm_odt_oe_end_1 0000_0000 pm_odt_oe_begin_1 000000_00 pm_odt_stop_edge_1 000000_00 pm_odt_start_edge_1 |
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MC0_DDR3_RDIMM_CTRL_0x058: .dword 0x0000002020056500 |
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//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_1 _00000000 pm_dll_rddqs_p_1 _00000000 pm_dll_wrdqs_1 _00000000 pm_dll_wrdata_1 _00000000 pm_dll_gate_1 |
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MC0_DDR3_RDIMM_CTRL_0x060: .dword 0x0201000301000000 |
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//0000_0000 pm_dq_oe_end_2 0000_0000 pm_dq_oe_begin_2 000000_00 pm_dq_stop_edge_2 000000_00 pm_dq_start_edge_2 0000000_0 pm_rddata_delay_2 0000000_0 pm_rddqs_lt_half_2 0000000_0 pm_wrdqs_lt_half_2 0000000_0 pm_wrdq_lt_half_2 |
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MC0_DDR3_RDIMM_CTRL_0x068: .dword 0x0303020202010101 |
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//0000_0000 pm_rd_oe_end_2 0000_0000 pm_rd_oe_begin_2 000000_00 pm_rd_stop_edge_2 000000_00 pm_rd_start_edge_2 0000_0000 pm_dqs_oe_end_2 0000_0000 pm_dqs_oe_begin_2 000000_00 pm_dqs_stop_edge_2 000000_00 pm_dqs_start_edge_2 |
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MC0_DDR3_RDIMM_CTRL_0x070: .dword 0x0000000004030000 |
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//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_2 0000_0000 pm_odt_oe_end_2 0000_0000 pm_odt_oe_begin_2 000000_00 pm_odt_stop_edge_2 000000_00 pm_odt_start_edge_2 |
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MC0_DDR3_RDIMM_CTRL_0x078: .dword 0x0000002020056500 |
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//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_2 _00000000 pm_dll_rddqs_p_2 _00000000 pm_dll_wrdqs_2 _00000000 pm_dll_wrdata_2 _00000000 pm_dll_gate_2 |
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MC0_DDR3_RDIMM_CTRL_0x080: .dword 0x0201000301000000 |
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//0000_0000 pm_dq_oe_end_3 0000_0000 pm_dq_oe_begin_3 000000_00 pm_dq_stop_edge_3 000000_00 pm_dq_start_edge_3 0000000_0 pm_rddata_delay_3 0000000_0 pm_rddqs_lt_half_3 0000000_0 pm_wrdqs_lt_half_3 0000000_0 pm_wrdq_lt_half_3 |
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MC0_DDR3_RDIMM_CTRL_0x088: .dword 0x0303020202010101 |
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//0000_0000 pm_rd_oe_end_3 0000_0000 pm_rd_oe_begin_3 000000_00 pm_rd_stop_edge_3 000000_00 pm_rd_start_edge_3 0000_0000 pm_dqs_oe_end_3 0000_0000 pm_dqs_oe_begin_3 000000_00 pm_dqs_stop_edge_3 000000_00 pm_dqs_start_edge_3 |
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MC0_DDR3_RDIMM_CTRL_0x090: .dword 0x0000000004030000 |
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//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_3 0000_0000 pm_odt_oe_end_3 0000_0000 pm_odt_oe_begin_3 000000_00 pm_odt_stop_edge_3 000000_00 pm_odt_start_edge_3 |
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MC0_DDR3_RDIMM_CTRL_0x098: .dword 0x0000002020056500 |
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//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_3 _00000000 pm_dll_rddqs_p_3 _00000000 pm_dll_wrdqs_3 _00000000 pm_dll_wrdata_3 _00000000 pm_dll_gate_3 |
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MC0_DDR3_RDIMM_CTRL_0x0a0: .dword 0x0201000301000000 |
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//0000_0000 pm_dq_oe_end_4 0000_0000 pm_dq_oe_begin_4 000000_00 pm_dq_stop_edge_4 000000_00 pm_dq_start_edge_4 0000000_0 pm_rddata_delay_4 0000000_0 pm_rddqs_lt_half_4 0000000_0 pm_wrdqs_lt_half_4 0000000_0 pm_wrdq_lt_half_4 |
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MC0_DDR3_RDIMM_CTRL_0x0a8: .dword 0x0303020202010101 |
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//0000_0000 pm_rd_oe_end_4 0000_0000 pm_rd_oe_begin_4 000000_00 pm_rd_stop_edge_4 000000_00 pm_rd_start_edge_4 0000_0000 pm_dqs_oe_end_4 0000_0000 pm_dqs_oe_begin_4 000000_00 pm_dqs_stop_edge_4 000000_00 pm_dqs_start_edge_4 |
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MC0_DDR3_RDIMM_CTRL_0x0b0: .dword 0x0000000004030000 |
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//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_4 0000_0000 pm_odt_oe_end_4 0000_0000 pm_odt_oe_begin_4 000000_00 pm_odt_stop_edge_4 000000_00 pm_odt_start_edge_4 |
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MC0_DDR3_RDIMM_CTRL_0x0b8: .dword 0x0000002020056500 |
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//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_4 _00000000 pm_dll_rddqs_p_4 _00000000 pm_dll_wrdqs_4 _00000000 pm_dll_wrdata_4 _00000000 pm_dll_gate_4 |
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MC0_DDR3_RDIMM_CTRL_0x0c0: .dword 0x0201000301000000 |
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//0000_0000 pm_dq_oe_end_5 0000_0000 pm_dq_oe_begin_5 000000_00 pm_dq_stop_edge_5 000000_00 pm_dq_start_edge_5 0000000_0 pm_rddata_delay_5 0000000_0 pm_rddqs_lt_half_5 0000000_0 pm_wrdqs_lt_half_5 0000000_0 pm_wrdq_lt_half_5 |
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MC0_DDR3_RDIMM_CTRL_0x0c8: .dword 0x0303020202010101 |
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//0000_0000 pm_rd_oe_end_5 0000_0000 pm_rd_oe_begin_5 000000_00 pm_rd_stop_edge_5 000000_00 pm_rd_start_edge_5 0000_0000 pm_dqs_oe_end_5 0000_0000 pm_dqs_oe_begin_5 000000_00 pm_dqs_stop_edge_5 000000_00 pm_dqs_start_edge_5 |
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MC0_DDR3_RDIMM_CTRL_0x0d0: .dword 0x0000000004030000 |
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//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_5 0000_0000 pm_odt_oe_end_5 0000_0000 pm_odt_oe_begin_5 000000_00 pm_odt_stop_edge_5 000000_00 pm_odt_start_edge_5 |
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MC0_DDR3_RDIMM_CTRL_0x0d8: .dword 0x0000002020056500 |
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//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_5 _00000000 pm_dll_rddqs_p_5 _00000000 pm_dll_wrdqs_5 _00000000 pm_dll_wrdata_5 _00000000 pm_dll_gate_5 |
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MC0_DDR3_RDIMM_CTRL_0x0e0: .dword 0x0201000301000000 |
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//0000_0000 pm_dq_oe_end_6 0000_0000 pm_dq_oe_begin_6 000000_00 pm_dq_stop_edge_6 000000_00 pm_dq_start_edge_6 0000000_0 pm_rddata_delay_6 0000000_0 pm_rddqs_lt_half_6 0000000_0 pm_wrdqs_lt_half_6 0000000_0 pm_wrdq_lt_half_6 |
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MC0_DDR3_RDIMM_CTRL_0x0e8: .dword 0x0303020202010101 |
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//0000_0000 pm_rd_oe_end_6 0000_0000 pm_rd_oe_begin_6 000000_00 pm_rd_stop_edge_6 000000_00 pm_rd_start_edge_6 0000_0000 pm_dqs_oe_end_6 0000_0000 pm_dqs_oe_begin_6 000000_00 pm_dqs_stop_edge_6 000000_00 pm_dqs_start_edge_6 |
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MC0_DDR3_RDIMM_CTRL_0x0f0: .dword 0x0000000004030000 |
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//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_6 0000_0000 pm_odt_oe_end_6 0000_0000 pm_odt_oe_begin_6 000000_00 pm_odt_stop_edge_6 000000_00 pm_odt_start_edge_6 |
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MC0_DDR3_RDIMM_CTRL_0x0f8: .dword 0x0000002020056500 |
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//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_6 _00000000 pm_dll_rddqs_p_6 _00000000 pm_dll_wrdqs_6 _00000000 pm_dll_wrdata_6 _00000000 pm_dll_gate_6 |
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MC0_DDR3_RDIMM_CTRL_0x100: .dword 0x0201000301000000 |
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//0000_0000 pm_dq_oe_end_7 0000_0000 pm_dq_oe_begin_7 000000_00 pm_dq_stop_edge_7 000000_00 pm_dq_start_edge_7 0000000_0 pm_rddata_delay_7 0000000_0 pm_rddqs_lt_half_7 0000000_0 pm_wrdqs_lt_half_7 0000000_0 pm_wrdq_lt_half_7 |
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MC0_DDR3_RDIMM_CTRL_0x108: .dword 0x0303020202010101 |
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//0000_0000 pm_rd_oe_end_7 0000_0000 pm_rd_oe_begin_7 000000_00 pm_rd_stop_edge_7 000000_00 pm_rd_start_edge_7 0000_0000 pm_dqs_oe_end_7 0000_0000 pm_dqs_oe_begin_7 000000_00 pm_dqs_stop_edge_7 000000_00 pm_dqs_start_edge_7 |
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MC0_DDR3_RDIMM_CTRL_0x110: .dword 0x0000000004030000 |
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//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_7 0000_0000 pm_odt_oe_end_7 0000_0000 pm_odt_oe_begin_7 000000_00 pm_odt_stop_edge_7 000000_00 pm_odt_start_edge_7 |
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MC0_DDR3_RDIMM_CTRL_0x118: .dword 0x0000002020056500 |
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//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_7 _00000000 pm_dll_rddqs_p_7 _00000000 pm_dll_wrdqs_7 _00000000 pm_dll_wrdata_7 _00000000 pm_dll_gate_7 |
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MC0_DDR3_RDIMM_CTRL_0x120: .dword 0x0201000301000000 |
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//0000_0000 pm_dq_oe_end_8 0000_0000 pm_dq_oe_begin_8 000000_00 pm_dq_stop_edge_8 000000_00 pm_dq_start_edge_8 0000000_0 pm_rddata_delay_8 0000000_0 pm_rddqs_lt_half_8 0000000_0 pm_wrdqs_lt_half_8 0000000_0 pm_wrdq_lt_half_8 |
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MC0_DDR3_RDIMM_CTRL_0x128: .dword 0x0303020202010101 |
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//0000_0000 pm_rd_oe_end_8 0000_0000 pm_rd_oe_begin_8 000000_00 pm_rd_stop_edge_8 000000_00 pm_rd_start_edge_8 0000_0000 pm_dqs_oe_end_8 0000_0000 pm_dqs_oe_begin_8 000000_00 pm_dqs_stop_edge_8 000000_00 pm_dqs_start_edge_8 |
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MC0_DDR3_RDIMM_CTRL_0x130: .dword 0x0000000004030000 |
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//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_8 0000_0000 pm_odt_oe_end_8 0000_0000 pm_odt_oe_begin_8 000000_00 pm_odt_stop_edge_8 000000_00 pm_odt_start_edge_8 |
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MC0_DDR3_RDIMM_CTRL_0x138: .dword 0x00000020207f6000 |
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//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_8 _00000000 pm_dll_rddqs_p_8 _00000000 pm_dll_wrdqs_8 _00000000 pm_dll_wrdata_8 _00000000 pm_dll_gate_8 |
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MC0_DDR3_RDIMM_CTRL_0x140: .dword 0x0403000001ff01ff |
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//00000_000 pm_pad_ocd_clk 00000_000 pm_pad_ocd_ctl 0000000_0 pm_pad_ocd_dqs 0000000_0 pm_pad_ocd_dq 0000000_0_00000000 pm_pad_enzi 0000000_0 pm_pad_en_ctl _00000000 pm_pad_en_clk |
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MC0_DDR3_RDIMM_CTRL_0x148: .dword 0x0000000000010100 |
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//_0000 pm_pad_adj_ncode_dq _0000 pm_pad_adj_pcode_dq 00000 _0 pm_pad_outodt_dq _0 pm_pad_slewrate_dq _0 pm_pad_code_dq _0000 pm_pad_adj_ncode_dq _0000 pm_pad_adj_pcode_dq 00000 _0 pm_pad_outodt_dq _0 pm_pad_slewrate_dq _0 00000000 0000000_0 pm_pad_vref_internal 0000000_0 pm_pad_odt_se 0000000_0 pm_pad_modezi1v8 |
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MC0_DDR3_RDIMM_CTRL_0x150: .dword 0x00000000f0020000 |
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//hXXXX _0000 pm_pad_adj_ncode_clk _0000 pm_pad_adj_pcode_clk 00000 _0 pm_pad_outodt_clk _0 pm_pad_slewrate_clk _0 pm_pad_code_clk _0000 pm_pad_adj_ncode_cmd _0000 pm_pad_adj_pcode_cmd 00000 _0 pm_pad_outodt_cmd _0 pm_pad_slewrate_cmd _0 pm_pad_code_cmd _0000 pm_pad_adj_ncode_addr _0000 pm_pad_adj_pcode_addr 00000 _0 pm_pad_outodt_addr _0 pm_pad_slewrate_addr _0 pm_pad_code_addr |
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MC0_DDR3_RDIMM_CTRL_0x158: .dword 0x00000000f0000000 |
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//hXXXXXXXX (RD) _0000 pm_pad_comp_ncode_i _0000 pm_pad_comp_pcode_i 0000000_0 pm_pad_comp_mode 0000000_0 pm_pad_comp_tm 0000000_0 pm_pad_comp_pd |
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MC0_DDR3_RDIMM_CTRL_0x160: .dword 0x0000000000010001 |
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//MC0_DDR3_RDIMM_CTRL_0x160: .dword 0x0000000000000001 |
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//0000000_0_00000000 pm_rdfifo_empty(RD) 0000000_0_00000000 pm_overflow(RD) 0000_0000 pm_dram_init(RD) 0000000_0 pm_rdfifo_valid 000000_00 pm_cmd_timing 0000000_0 pm_ddr3_mode |
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MC0_DDR3_RDIMM_CTRL_0x168: .dword 0x000a000707030101 |
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//hXX (RD) 0000_0000 pm_addr_mirror 000000_00 pm_cmd_delay _00000000 pm_burst_length 00000_000 pm_bank 0000_0000 pm_cs_zq 0000_0000 pm_cs_mrs 0000_0000 pm_cs_enable |
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//MC0_DDR3_RDIMM_CTRL_0x170: .dword 0x0000000001ff01ff |
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MC0_DDR3_RDIMM_CTRL_0x170: .dword 0x8421050084120501 |
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//_00000000_00000000 pm_odt_wr_cs_map 0000_0000 pm_odt_wr_length 0000_0000 pm_odt_wr_delay _00000000_00000000 pm_odt_rd_cs_map 0000_0000 pm_odt_rd_length 0000_0000 pm_odt_rd_delay |
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MC0_DDR3_RDIMM_CTRL_0x178: .dword 0x0000000000000000 |
|||
//hXXXXXXXXXXXXXXXX (RD) |
|||
MC0_DDR3_RDIMM_CTRL_0x180: .dword 0x0000000001100000 |
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//_00000000 pm_lvl_resp_0(RD) 0000000_0 pm_lvl_done(RD) 0000000_0 pm_lvl_ready(RD) 00000000 0000_0000 pm_lvl_cs _00000000 pm_tLVL_DELAY 0000000_0 pm_leveling_req(WR) 000000_00 pm_leveling_mode |
|||
MC0_DDR3_RDIMM_CTRL_0x188: .dword 0x0000000000000000 |
|||
//_00000000 pm_lvl_resp_8(RD) _00000000 pm_lvl_resp_7(RD) _00000000 _pm_lvl_resp_6(RD) _00000000 pm_lvl_resp_5(RD) _00000000 pm_lvl_resp_4(RD) _00000000 pm_lvl_resp_3(RD) _00000000 pm_lvl_resp_2(RD) _00000000 pm_lvl_resp_1(RD) |
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|
|||
//CMD CONFIG |
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MC0_DDR3_RDIMM_CTRL_0x190: .dword 0x0000000000000000 |
|||
//_00000000_00000000 pm_cmd_a 00000_000 pm_cmd_ba 00000_000 pm_cmd_cmd 0000_0000 pm_cmd_cs 0000000_0 pm_status_cmd(RD) 0000000_0 pm_cmd_req(WR) 0000000_0 pm_command |
|||
MC0_DDR3_RDIMM_CTRL_0x198: .dword 0x0000000000000000 |
|||
//00000000 00000000 0000_0000 pm_status_sref(RD) 0000_0000 pm_srefresh_req 0000000_0 pm_pre_all_done(RD) 0000000_0 pm_pre_all_req(WR) 0000000_0 pm_mrs_done(RD) 0000000_0 pm_mrs_req(WR) |
|||
MC0_DDR3_RDIMM_CTRL_0x1a0: .dword 0x0000001800060d60 |
|||
//_00000000_00000000 pm_mr_3_cs_0 _00000000_00000000 pm_mr_2_cs_0 _00000000_00000000 pm_mr_1_cs_0 _00000000_00000000 pm_mr_0_cs_0 |
|||
MC0_DDR3_RDIMM_CTRL_0x1a8: .dword 0x0000001800060d60 |
|||
//_00000000_00000000 pm_mr_3_cs_1 _00000000_00000000 pm_mr_2_cs_1 _00000000_00000000 pm_mr_1_cs_1 _00000000_00000000 pm_mr_0_cs_1 |
|||
MC0_DDR3_RDIMM_CTRL_0x1b0: .dword 0x0000001800060d60 |
|||
//_00000000_00000000 pm_mr_3_cs_2 _00000000_00000000 pm_mr_2_cs_2 _00000000_00000000 pm_mr_1_cs_2 _00000000_00000000 pm_mr_0_cs_2 |
|||
MC0_DDR3_RDIMM_CTRL_0x1b8: .dword 0x0000001800060d60 |
|||
//_00000000_00000000 pm_mr_3_cs_3 _00000000_00000000 pm_mr_2_cs_3 _00000000_00000000 pm_mr_1_cs_3 _00000000_00000000 pm_mr_0_cs_3 |
|||
MC0_DDR3_RDIMM_CTRL_0x1c0: .dword 0x3030c80c03032006 |
|||
//_00000000 pm_tRESET _00000000 pm_tCKE _00000000 pm_tXPR _00000000 pm_tMOD _00000000 pm_tZQCL _00000000 pm_tZQ_CMD _00000000 pm_tWLDQSEN 000_00000 pm_tRDDATA |
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MC0_DDR3_RDIMM_CTRL_0x1c8: .dword 0x1f06090903854004 |
|||
//00_000000 pm_tFAW 0000_0000 pm_tRRD 0000_0000 pm_tRCD _00000000 pm_tRP _00000000 pm_tREF _00000000 pm_tRFC _00000000 pm_tZQCS _00000000 pm_tZQperiod |
|||
MC0_DDR3_RDIMM_CTRL_0x1d0: .dword 0x0a0208050200001c |
|||
//0000_0000 pm_tODTL _00000000 pm_tXSRD 0000_0000 pm_tPHY_RDLAT 000_00000 pm_tPHY_WRLAT 000000_00_00000000_00000000 pm_tRAS_max 00_000000 pm_tRAS_min |
|||
MC0_DDR3_RDIMM_CTRL_0x1d8: .dword 0x14050c060a080406 |
|||
//_00000000 pm_tXPDLL _00000000 pm_tXP 000_00000 pm_tWR 0000_0000 pm_tRTP 0000_0000 pm_tRL 0000_0000 pm_tWL 0000_0000 pm_tCCD 0000_0000 pm_tWTR |
|||
MC0_DDR3_RDIMM_CTRL_0x1e0: .dword 0x0303000000000000 |
|||
//00_000000 pm_tW2R_diffcs_dly 00_000000 pm_tW2W_diffcs_adj_dly 00_000000 pm_tR2P_sameba_adj_dly 00_000000 pm_tW2P_sameba_adj_dly 00_000000 pm_tR2R_sameba_adj_dly 00_000000 pm_tR2W_sameba_adj_dly 00_000000 pm_tW2R_sameba_adj_dly 00_000000 pm_tW2W_sameba_adj_dly |
|||
MC0_DDR3_RDIMM_CTRL_0x1e8: .dword 0x0307000000000000 |
|||
//00_000000 pm_tR2R_diffcs_adj_dly 00_000000 pm_tR2W_diffcs_dly 00_000000 pm_tR2P_samecs_dly 00_000000 pm_tW2P_samecs_dly 00_000000 pm_tR2R_samecs_adj_dly 00_000000 pm_tR2W_samecs_adj_dly 00_000000 pm_tW2R_samecs_adj_dly 00_000000 pm_tW2W_samecs_adj_dly |
|||
MC0_DDR3_RDIMM_CTRL_0x1f0: .dword 0x000801e4ff000101 |
|||
//0000_0000 pm_power_up _00000000 pm_age_step _00000000 pm_tCPDED _00000000 pm_cs_map _00000000 pm_bs_config 00000_000 pm_channel_32 pm_channel_16 pm_nc 0000_0000 pm_pr_r2w 0000000_0 pm_placement_en |
|||
MC0_DDR3_RDIMM_CTRL_0x1f8: .dword 0x0000000004081001 |
|||
//0000_0000 pm_hardware_pd_3 0000_0000 pm_hardware_pd_2 0000_0000 pm_hardware_pd_1 0000_0000 pm_hardware_pd_0 00_000000 pm_credit_16 00_000000 pm_credit_32 00_000000 pm_credit_64 0000000_0 pm_selection_en |
|||
MC0_DDR3_RDIMM_CTRL_0x200: .dword 0x0c000c000c000c00 |
|||
//0000_0000_00000000 pm_cmdq_age_16 0000_0000_00000000 pm_cmdq_age_32 0000_0000_00000000 pm_cmdq_age_64 _00000000 pm_tCKESR _00000000 pm_tRDPDEN |
|||
MC0_DDR3_RDIMM_CTRL_0x208: .dword 0x0c000c0000000000 |
|||
//0000_0000_00000000 pm_wrfifo_age 0000_0000_00000000 pm_rdfifo_age 0000_0000 pm_power_status_3 0000_0000 pm_power_status_2 0000_0000 pm_power_status_1 0000_0000 pm_power_status_0 |
|||
MC0_DDR3_RDIMM_CTRL_0x210: .dword 0x0008010f00030006 |
|||
//_00000000_00000000 pm_active_age 0000000_0 pm_cs_place_0 0000_0000 pm_addr_win_0 000000_00 pm_cs_diff_0 00000_000 pm_row_diff_0 000000_00 pm_ba_diff_0 00000_000 pm_col_diff_0 |
|||
MC0_DDR3_RDIMM_CTRL_0x218: .dword 0x0008000b00030106 |
|||
//_00000000_00000000 pm_fastpd_age 0000000_0 pm_cs_place_1 0000_0000 pm_addr_win_1 000000_00 pm_cs_diff_1 00000_000 pm_row_diff_1 000000_00 pm_ba_diff_1 00000_000 pm_col_diff_1 |
|||
MC0_DDR3_RDIMM_CTRL_0x220: .dword 0x0008000b00030106 |
|||
//_00000000_00000000 pm_slowpd_age 0000000_0 pm_cs_place_2 0000_0000 pm_addr_win_2 000000_00 pm_cs_diff_2 00000_000 pm_row_diff_2 000000_00 pm_ba_diff_2 00000_000 pm_col_diff_2 |
|||
MC0_DDR3_RDIMM_CTRL_0x228: .dword 0x0008000b00030106 |
|||
//_00000000_00000000 pm_selfref_age 0000000_0 pm_cs_place_3 0000_0000 pm_addr_win_3 000000_00 pm_cs_diff_3 00000_000 pm_row_diff_3 000000_00 pm_ba_diff_3 00000_000 pm_col_diff_3 |
|||
MC0_DDR3_RDIMM_CTRL_0x230: .dword 0x0fff000000000000 |
|||
//0000_0000_00000000_00000000_00000000 pm_addr_mask_0 0000_0000_00000000_00000000_00000000 pm_addr_base_0 |
|||
MC0_DDR3_RDIMM_CTRL_0x238: .dword 0x0ffffe000000ff00 |
|||
//0000_0000_00000000_00000000_00000000 pm_addr_mask_1 0000_0000_00000000_00000000_00000000 pm_addr_base_1 |
|||
MC0_DDR3_RDIMM_CTRL_0x240: .dword 0x0ffffe000000ff00 |
|||
//0000_0000_00000000_00000000_00000000 pm_addr_mask_2 0000_0000_00000000_00000000_00000000 pm_addr_base_2 |
|||
MC0_DDR3_RDIMM_CTRL_0x248: .dword 0x0ffffe000000ff00 |
|||
//0000_0000_00000000_00000000_00000000 pm_addr_mask_3 0000_0000_00000000_00000000_00000000 pm_addr_base_3 |
|||
MC0_DDR3_RDIMM_CTRL_0x250: .dword 0x0000000000000000 |
|||
//00000000 _00_00_00_00 pm_cmd_monitor_3_2_1_0 000000_00_00000000 pm_axi_monitor _00000000 pm_ecc_code(RD) 0000_0_000 pm_int_trigger pm_ecc_enable 000000_00 pm_int_vector 000000_00 pm_int_enable |
|||
MC0_DDR3_RDIMM_CTRL_0x258: .dword 0x0000000000000000 |
|||
//XXXXXXXXXXXXXXXX (RD) |
|||
MC0_DDR3_RDIMM_CTRL_0x260: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_ecc_addr(RD) |
|||
MC0_DDR3_RDIMM_CTRL_0x268: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_ecc_data(RD) |
|||
MC0_DDR3_RDIMM_CTRL_0x270: .dword 0x0000001000000000 |
|||
//000000_00 pm_lpbk_ecc_mask(RD) 0_0000000_00000000_00000000 pm_prbs_init 0000000_0 pm_lpbk_error(RD) 0000000_0 pm_prbs_23 0000000_0 pm_lpbk_start 0000000_0 pm_lpbk_en |
|||
MC0_DDR3_RDIMM_CTRL_0x278: .dword 0x0000000000000000 |
|||
//_00000000_00000000 pm_lpbk_ecc(RD) _00000000_00000000 pm_lpbk_data_mask(RD) _00000000_00000000 pm_lpbk_correct(RD) _00000000_00000000 pm_lpbk_counter(RD) |
|||
MC0_DDR3_RDIMM_CTRL_0x280: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_lpbk_data[ 63: 0](RD) |
|||
MC0_DDR3_RDIMM_CTRL_0x288: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_lpbk_data[127:64](RD) |
|||
|
|||
//Monitor fbck |
|||
MC0_DDR3_RDIMM_CTRL_0x290: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi0_fbck[ 63: 0](RD) |
|||
MC0_DDR3_RDIMM_CTRL_0x298: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi0_fbck[127:64](RD) |
|||
MC0_DDR3_RDIMM_CTRL_0x2a0: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi1_fbck[ 63: 0](RD) |
|||
MC0_DDR3_RDIMM_CTRL_0x2a8: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi1_fbck[127:64](RD) |
|||
MC0_DDR3_RDIMM_CTRL_0x2b0: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi2_fbck[ 63: 0](RD) |
|||
MC0_DDR3_RDIMM_CTRL_0x2b8: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi2_fbck[127:64](RD) |
|||
MC0_DDR3_RDIMM_CTRL_0x2c0: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi3_fbck[ 63: 0](RD) |
|||
MC0_DDR3_RDIMM_CTRL_0x2c8: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi3_fbck[127:64](RD) |
|||
MC0_DDR3_RDIMM_CTRL_0x2d0: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi4_fbck[ 63: 0](RD) |
|||
MC0_DDR3_RDIMM_CTRL_0x2d8: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_axi4_fbck[127:64](RD) |
|||
MC0_DDR3_RDIMM_CTRL_0x2e0: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_cmd_fbck0[ 63: 0](RD) |
|||
MC0_DDR3_RDIMM_CTRL_0x2e8: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_cmd_fbck0[127:64](RD) |
|||
MC0_DDR3_RDIMM_CTRL_0x2f0: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_cmd_fbck1[ 63: 0](RD) |
|||
MC0_DDR3_RDIMM_CTRL_0x2f8: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_cmd_fbck1[127:64](RD) |
|||
MC0_DDR3_RDIMM_CTRL_0x300: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_cmd_fbck2[ 63: 0](RD) |
|||
MC0_DDR3_RDIMM_CTRL_0x308: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_cmd_fbck2[127:64](RD) |
|||
MC0_DDR3_RDIMM_CTRL_0x310: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_cmd_fbck3[ 63: 0](RD) |
|||
MC0_DDR3_RDIMM_CTRL_0x318: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX pm_cmd_fbck3[127:64](RD) |
|||
MC0_DDR3_RDIMM_CTRL_0x320: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX 0000_0000 pm_REF_low |
|||
MC0_DDR3_RDIMM_CTRL_0x328: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX (RD) |
|||
MC0_DDR3_RDIMM_CTRL_0x330: .dword 0x000000100000040a |
|||
//0000000_0 pm_stat_en 0_0000000 pm_rdbuffer_max(RD) 0000000_0 pm_retry 00_000000 pm_wr_pkg_num 0000000_0 pm_rwq_rb 0000000_0 pm_stb_en 000_00000 pm_addr_new 0000_0000 pm_tRDQidle |
|||
MC0_DDR3_RDIMM_CTRL_0x338: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX 0000_0000 pm_fifo_depth 00000000_00000000_00000000_00000000 pm_retry_cnt(RD) |
|||
MC0_DDR3_RDIMM_CTRL_0x340: .dword 0x0030d40000070f00 |
|||
//00000000_00000000_00000000_00000000 pm_tREFretention 0000_0000 pm_ref_num 00000000 pm_tREF_IDLE 0000000_0 pm_ref_sch_en |
|||
MC0_DDR3_RDIMM_CTRL_0x348: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX |
|||
MC0_DDR3_RDIMM_CTRL_0x350: .dword 0xffffffffffffffff |
|||
//_XXXXXXXXXXXXXXXX pm_lpbk_data_en |
|||
MC0_DDR3_RDIMM_CTRL_0x358: .dword 0x000000000001ffff |
|||
//0000000_0 pm_lpbk_ecc_mask_en 00000000 pm_lpbk_ecc_en 00000000 pm_lpbk_data_mask_en |
|||
MC0_DDR3_RDIMM_CTRL_0x360: .dword 0x0000000000000000 |
|||
//00000000 pm_ecc_int_cnt_fatal 00000000 pm_ecc_int_cnt_error 00000000 pm_ecc_cnt_cs_3 00000000 pm_ecc_cnt_cs_2 00000000 pm_ecc_cnt_cs_1 00000000 pm_ecc_cnt_cs_0 |
|||
MC0_DDR3_RDIMM_CTRL_0x368: .dword 0x0000000000000000 |
|||
//_XXXXXXXXXXXXXXXX |
|||
@ -0,0 +1,499 @@ |
|||
#include "time.h" |
|||
#define nr_printf printf |
|||
#define nr_gets gets |
|||
#define nr_strtol strtoul |
|||
//-------------------------------------------PNP------------------------------------------
|
|||
// MB PnP configuration register
|
|||
|
|||
//#define PNP_KEY_ADDR (0xbfd00000+0x3f0)
|
|||
//#define PNP_DATA_ADDR (0xbfd00000+0x3f1)
|
|||
|
|||
#define PNP_KEY_ADDR (BONITO_PCIIO_BASE_VA+0x3f0) |
|||
#define PNP_DATA_ADDR (BONITO_PCIIO_BASE_VA+0x3f1) |
|||
|
|||
|
|||
static unsigned char slave_addr; |
|||
|
|||
void PNPSetConfig(char Index, char data); |
|||
char PNPGetConfig(char Index); |
|||
|
|||
#define SUPERIO_CFG_REG 0x85 |
|||
|
|||
void EnterMBPnP(void) |
|||
{ |
|||
pcitag_t tag; |
|||
char confval; |
|||
tag=_pci_make_tag(VTSB_BUS,VTSB_DEV, VTSB_ISA_FUNC); |
|||
confval=_pci_conf_readn(tag,SUPERIO_CFG_REG,1); |
|||
_pci_conf_writen(tag,SUPERIO_CFG_REG,confval|2,1); |
|||
} |
|||
|
|||
void ExitMBPnP(void) |
|||
{ |
|||
pcitag_t tag; |
|||
char confval,val; |
|||
tag=_pci_make_tag(VTSB_BUS,VTSB_DEV, VTSB_ISA_FUNC); |
|||
confval=_pci_conf_readn(tag,SUPERIO_CFG_REG,1); |
|||
_pci_conf_writen(tag,SUPERIO_CFG_REG,confval&~2,1); |
|||
} |
|||
|
|||
void PNPSetConfig(char Index, char data) |
|||
{ |
|||
EnterMBPnP(); // Enter IT8712 MB PnP mode
|
|||
outb(PNP_KEY_ADDR,Index); |
|||
outb(PNP_DATA_ADDR,data); |
|||
ExitMBPnP(); |
|||
} |
|||
|
|||
char PNPGetConfig(char Index) |
|||
{ |
|||
char rtn; |
|||
|
|||
EnterMBPnP(); // Enter IT8712 MB PnP mode
|
|||
outb(PNP_KEY_ADDR,Index); |
|||
rtn = inb(PNP_DATA_ADDR); |
|||
ExitMBPnP(); |
|||
return rtn; |
|||
} |
|||
|
|||
|
|||
|
|||
int dumpsis(int argc,char **argv) |
|||
{ |
|||
int i; |
|||
//volatile unsigned char *p=0xbfd003c4;
|
|||
volatile unsigned char *p=(BONITO_PCIIO_BASE_VA + 0x3c4); |
|||
unsigned char c; |
|||
for(i=0;i<0x15;i++) |
|||
{ |
|||
p[0]=i; |
|||
c=p[1]; |
|||
printf("sr%x=0x%02x\n",i,c); |
|||
} |
|||
p[0]=5; |
|||
p[1]=0x86; |
|||
printf("after set 0x86 to sr5\n"); |
|||
for(i=0;i<0x15;i++) |
|||
{ |
|||
p[0]=i; |
|||
c=p[1]; |
|||
printf("sr%x=0x%02x\n",i,c); |
|||
} |
|||
return 0; |
|||
} |
|||
|
|||
unsigned char i2cread(char slot,char offset); |
|||
|
|||
|
|||
union commondata{ |
|||
unsigned char data1; |
|||
unsigned short data2; |
|||
unsigned int data4; |
|||
unsigned int data8[2]; |
|||
unsigned char c[8]; |
|||
}; |
|||
extern unsigned int syscall_addrtype; |
|||
extern int (*syscall1)(int type,long long addr,union commondata *mydata); |
|||
extern int (*syscall2)(int type,long long addr,union commondata *mydata); |
|||
|
|||
static int PnpRead(int type,long long addr,union commondata *mydata) |
|||
{ |
|||
switch(type) |
|||
{ |
|||
case 1:mydata->data1=PNPGetConfig(addr);break; |
|||
default: return -1;break; |
|||
} |
|||
return 0; |
|||
} |
|||
|
|||
static int PnpWrite(int type,long long addr,union commondata *mydata) |
|||
{ |
|||
switch(type) |
|||
{ |
|||
case 1:PNPSetConfig(addr,mydata->data1);break; |
|||
default: return -1;break; |
|||
} |
|||
return 0; |
|||
} |
|||
|
|||
#if PCI_IDSEL_CS5536 != 0 |
|||
|
|||
static int logicdev=0; |
|||
static int PnpRead_w83627(int type,long long addr,union commondata *mydata) |
|||
{ |
|||
switch(type) |
|||
{ |
|||
case 1: |
|||
mydata->data1=w83627_read(logicdev,addr); |
|||
break; |
|||
default: return -1;break; |
|||
} |
|||
return 0; |
|||
} |
|||
|
|||
static int PnpWrite_w83627(int type,long long addr,union commondata *mydata) |
|||
{ |
|||
switch(type) |
|||
{ |
|||
case 1: |
|||
w83627_write(logicdev,addr,mydata->data1); |
|||
break; |
|||
default: return -1;break; |
|||
} |
|||
return 0; |
|||
} |
|||
|
|||
#endif |
|||
|
|||
|
|||
static int pnps(int argc,char **argv) |
|||
{ |
|||
#if PCI_IDSEL_CS5536 != 0 |
|||
logicdev=strtoul(argv[1],0,0); |
|||
syscall1=(void*)PnpRead_w83627; |
|||
syscall2=(void*)PnpWrite_w83627; |
|||
#else |
|||
syscall1=(void*)PnpRead; |
|||
syscall2=(void*)PnpWrite; |
|||
#endif |
|||
syscall_addrtype=0; |
|||
return 0; |
|||
} |
|||
|
|||
#include "target/via686b.h" |
|||
static int i2cslot=0; |
|||
|
|||
|
|||
static int DimmRead(int type,long long addr,union commondata *mydata) |
|||
{ |
|||
char i2caddr[]={(i2cslot<<1)+0xa0}; |
|||
switch(type) |
|||
{ |
|||
case 1: |
|||
tgt_i2cread(I2C_SINGLE,i2caddr,1,addr,&mydata->data1,1); |
|||
break; |
|||
|
|||
default: return -1;break; |
|||
} |
|||
return 0; |
|||
} |
|||
|
|||
static int DimmWrite(int type,long long addr,union commondata *mydata) |
|||
{ |
|||
return -1; |
|||
} |
|||
|
|||
|
|||
static int Ics950220Read(int type,long long addr,union commondata *mydata) |
|||
{ |
|||
char c; |
|||
char i2caddr[]={0xd2}; |
|||
switch(type) |
|||
{ |
|||
case 1: |
|||
tgt_i2cread(I2C_SMB_BLOCK,i2caddr,1,addr,&mydata->data1,1); |
|||
|
|||
break; |
|||
|
|||
default: return -1;break; |
|||
} |
|||
return 0; |
|||
} |
|||
|
|||
static int Ics950220Write(int type,long long addr,union commondata *mydata) |
|||
{ |
|||
char c; |
|||
char i2caddr[]={0xd2}; |
|||
switch(type) |
|||
{ |
|||
case 1: |
|||
tgt_i2cwrite(I2C_SMB_BLOCK,i2caddr,1,addr,&mydata->data1,1); |
|||
|
|||
break; |
|||
|
|||
default: return -1;break; |
|||
} |
|||
return 0; |
|||
return -1; |
|||
} |
|||
|
|||
static int rom_ddr_reg_read(int type,long long addr,union commondata *mydata) |
|||
{ |
|||
char *nvrambuf; |
|||
extern char ddr3_reg_data,_start; |
|||
nvrambuf = 0xbfc00000+((int)&ddr3_reg_data -(int)&_start)+addr; |
|||
// printf("ddr3_reg_data=%x\nbuf=%x,ddr=%x\n",&ddr3_reg_data,nvrambuf,addr);
|
|||
switch(type) |
|||
{ |
|||
case 1:memcpy(&mydata->data1,nvrambuf,1);break; |
|||
case 2:memcpy(&mydata->data2,nvrambuf,2);break; |
|||
case 4:memcpy(&mydata->data4,nvrambuf,4);break; |
|||
case 8:memcpy(&mydata->data8,nvrambuf,8);break; |
|||
} |
|||
return 0; |
|||
} |
|||
|
|||
static int rom_ddr_reg_write(int type,long long addr,union commondata *mydata) |
|||
{ |
|||
char *nvrambuf; |
|||
char *nvramsecbuf; |
|||
char *nvram; |
|||
int offs; |
|||
extern char ddr3_reg_data,_start; |
|||
struct fl_device *dev=fl_devident(0xbfc00000,0); |
|||
int nvram_size=dev->fl_secsize; |
|||
|
|||
nvram = 0xbfc00000+((int)&ddr3_reg_data -(int)&_start); |
|||
offs=(int)nvram &(nvram_size - 1); |
|||
nvram =(int)nvram & ~(nvram_size - 1); |
|||
|
|||
/* Deal with an entire sector even if we only use part of it */ |
|||
|
|||
/* If NVRAM is found to be uninitialized, reinit it. */ |
|||
|
|||
/* Find end of evironment strings */ |
|||
nvramsecbuf = (char *)malloc(nvram_size); |
|||
|
|||
if(nvramsecbuf == 0) { |
|||
printf("Warning! Unable to malloc nvrambuffer!\n"); |
|||
return(-1); |
|||
} |
|||
|
|||
memcpy(nvramsecbuf, nvram, nvram_size); |
|||
if(fl_erase_device(nvram, nvram_size, FALSE)) { |
|||
printf("Error! Nvram erase failed!\n"); |
|||
free(nvramsecbuf); |
|||
return(0); |
|||
} |
|||
|
|||
nvrambuf = nvramsecbuf + offs; |
|||
switch(type) |
|||
{ |
|||
case 1:memcpy(nvrambuf+addr,&mydata->data1,1);break; |
|||
case 2:memcpy(nvrambuf+addr,&mydata->data2,2);break; |
|||
case 4:memcpy(nvrambuf+addr,&mydata->data4,4);break; |
|||
case 8:memcpy(nvrambuf+addr,&mydata->data8,8);break; |
|||
} |
|||
|
|||
if(fl_program_device(nvram, nvramsecbuf, nvram_size, FALSE)) { |
|||
printf("Error! Nvram program failed!\n"); |
|||
free(nvramsecbuf); |
|||
return(0); |
|||
} |
|||
free(nvramsecbuf); |
|||
return 0; |
|||
} |
|||
|
|||
|
|||
#if defined(DEVBD2F_SM502)||defined(DEVBD2F_FIREWALL) |
|||
|
|||
|
|||
#ifndef BCD_TO_BIN |
|||
#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10) |
|||
#endif |
|||
|
|||
#ifndef BIN_TO_BCD |
|||
#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10) |
|||
#endif |
|||
|
|||
void tm_binary_to_bcd(struct tm *tm) |
|||
{ |
|||
BIN_TO_BCD(tm->tm_sec); |
|||
BIN_TO_BCD(tm->tm_min); |
|||
BIN_TO_BCD(tm->tm_hour); |
|||
tm->tm_hour = tm->tm_hour|0x80; |
|||
BIN_TO_BCD(tm->tm_mday); |
|||
BIN_TO_BCD(tm->tm_mon); |
|||
BIN_TO_BCD(tm->tm_year); |
|||
BIN_TO_BCD(tm->tm_wday); |
|||
|
|||
} |
|||
|
|||
/*
|
|||
*isl 12027 |
|||
* */ |
|||
char gpio_i2c_settime(struct tm *tm) |
|||
{ |
|||
struct |
|||
{ |
|||
char tm_sec; |
|||
char tm_min; |
|||
char tm_hour; |
|||
char tm_mday; |
|||
char tm_mon; |
|||
char tm_year; |
|||
char tm_wday; |
|||
char tm_year_hi; |
|||
} rtcvar; |
|||
char i2caddr[]={0xde,0}; |
|||
|
|||
char a ; |
|||
word_addr = 1; |
|||
tm->tm_mon = tm->tm_mon + 1; |
|||
tm_binary_to_bcd(tm); |
|||
|
|||
//when rtc stop,can't set it ,follow 5 lines to resolve it
|
|||
a = 2; |
|||
tgt_i2cwrite(I2C_SINGLE,i2caddr,2,0x3f,&a,1); |
|||
a = 6; |
|||
tgt_i2cwrite(I2C_SINGLE,i2caddr,2,0x3f,&a,1); |
|||
tgt_i2cwrite(I2C_SINGLE,i2caddr,2,0x30,&a,1); |
|||
|
|||
a = 2; |
|||
tgt_i2cwrite(I2C_SINGLE,i2caddr,2,0x3f,&a,1); |
|||
a = 6; |
|||
tgt_i2cwrite(I2C_SINGLE,i2caddr,2,0x3f,&a,1); |
|||
|
|||
//begin set
|
|||
|
|||
rtcvar.tm_sec=tm->tm_sec; |
|||
rtcvar.tm_min=tm->tm_min; |
|||
rtcvar.tm_hour=tm->tm_hour; |
|||
rtcvar.tm_mday=tm->tm_mday; |
|||
rtcvar.tm_mon=tm->tm_mon; |
|||
rtcvar.tm_wday=tm->tm_wday; |
|||
if(tm->tm_year>=0xa0) |
|||
{ |
|||
rtcvar.tm_year = tm->tm_year - 0xa0; |
|||
rtcvar.tm_year_hi=20; |
|||
|
|||
} |
|||
else |
|||
{ |
|||
rtcvar.tm_year = tm->tm_year; |
|||
rtcvar.tm_year_hi=19; |
|||
} |
|||
tgt_i2cwrite(I2C_BLOCK,i2caddr,2,0x30,&rtcvar,sizeof(rtcvar)); |
|||
|
|||
return 1; |
|||
|
|||
} |
|||
|
|||
/*
|
|||
* sm502: rx8025 |
|||
* fire:isl12027 |
|||
*/ |
|||
|
|||
|
|||
|
|||
|
|||
#endif |
|||
|
|||
//----------------------------------------
|
|||
|
|||
static int syscall_i2c_type,syscall_i2c_addrlen; |
|||
static char syscall_i2c_addr[2]; |
|||
|
|||
static int i2c_read_syscall(int type,long long addr,union commondata *mydata) |
|||
{ |
|||
char c; |
|||
switch(type) |
|||
{ |
|||
case 1: |
|||
tgt_i2cread(syscall_i2c_type,syscall_i2c_addr,syscall_i2c_addrlen,addr,&mydata->data1,1); |
|||
|
|||
break; |
|||
|
|||
default: return -1;break; |
|||
} |
|||
return 0; |
|||
} |
|||
|
|||
static int i2c_write_syscall(int type,long long addr,union commondata *mydata) |
|||
{ |
|||
char c; |
|||
switch(type) |
|||
{ |
|||
case 1: |
|||
tgt_i2cwrite(syscall_i2c_type,syscall_i2c_addr,syscall_i2c_addrlen,addr,&mydata->data1,1); |
|||
|
|||
break; |
|||
|
|||
default: return -1;break; |
|||
} |
|||
return 0; |
|||
return -1; |
|||
} |
|||
//----------------------------------------
|
|||
|
|||
static int i2cs(int argc,char **argv) |
|||
{ |
|||
pcitag_t tag; |
|||
volatile int i; |
|||
if(argc<2) |
|||
return -1; |
|||
|
|||
i2cslot=strtoul(argv[1],0,0); |
|||
|
|||
switch(i2cslot) |
|||
{ |
|||
case 0: |
|||
case 1: |
|||
syscall1=(void*)DimmRead; |
|||
syscall2=(void*)DimmWrite; |
|||
break; |
|||
case 2: |
|||
syscall1=(void*)Ics950220Read; |
|||
syscall2=(void*)Ics950220Write; |
|||
break; |
|||
case 3: |
|||
syscall1=(void *)rom_ddr_reg_read; |
|||
syscall2=(void *)rom_ddr_reg_write; |
|||
if(argc==3 && !strcmp(argv[2][2],"revert")) |
|||
{ |
|||
extern char ddr3_reg_data,_start; |
|||
extern char ddr3_reg_data1; |
|||
printf("revert to default ddr setting\n"); |
|||
// tgt_flashprogram(0xbfc00000+((int)&ddr3_reg_data -(int)&_start),30*8,&ddr3_reg_data1,TRUE);
|
|||
} |
|||
break; |
|||
case -1: |
|||
if(argc<4)return -1; |
|||
syscall_i2c_type=strtoul(argv[2],0,0); |
|||
syscall_i2c_addrlen=argc-3; |
|||
for(i=3;i<argc;i++)syscall_i2c_addr[i-3]=strtoul(argv[i],0,0); |
|||
syscall1=(void*)i2c_read_syscall; |
|||
syscall2=(void*)i2c_write_syscall; |
|||
break; |
|||
default: |
|||
return -1; |
|||
} |
|||
|
|||
syscall_addrtype=0; |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
|
|||
|
|||
static const Cmd Cmds[] = |
|||
{ |
|||
{"MyCmds"}, |
|||
{"pnps", "", 0, "select pnp ops for d1,m1 ", pnps, 0, 99, CMD_REPEAT}, |
|||
{"dumpsis", "", 0, "dump sis registers", dumpsis, 0, 99, CMD_REPEAT}, |
|||
{"i2cs","slotno #slot 0-1 for dimm,slot 2 for ics95220,3 for ddrcfg,3 revert for revert to default ddr setting", 0, "select i2c ops for d1,m1", i2cs, 0, 99, CMD_REPEAT}, |
|||
{0, 0} |
|||
}; |
|||
|
|||
#ifdef DEVBD2F_SM502 |
|||
int power_button_poll(void *unused) |
|||
{ |
|||
int cause; |
|||
volatile int *p=0xbfe0011c; |
|||
asm("mfc0 %0,$13":"=r"(cause)); |
|||
if(cause&(1<<10))tgt_poweroff(); |
|||
return 0; |
|||
} |
|||
#endif |
|||
|
|||
static void init_cmd __P((void)) __attribute__ ((constructor)); |
|||
|
|||
static void |
|||
init_cmd() |
|||
{ |
|||
#ifdef DEVBD2F_SM502 |
|||
tgt_poll_register(1, power_button_poll, 0); |
|||
#endif |
|||
cmdlist_expand(Cmds, 1); |
|||
} |
|||
|
|||
@ -0,0 +1,142 @@ |
|||
/*smh : pcitlb.S |
|||
used to map address accessing for kuseg to address accessing for system memory beyond low 256M memory |
|||
used to map address accessing for kseg2 to address accessing for pci memory which are from 0x40000000 |
|||
*/ |
|||
|
|||
/***********************************************************************************************************/ |
|||
/**************************************** MAP KSEG2 ********************************************************/ |
|||
/** MAP virtual address: 0xc0000000~ 0xffffffff to physical address: 0x40000000~ 0x7fffffff for PCI-MEM **/ |
|||
/***********************************************************************************************************/ |
|||
|
|||
li t0, 0x40000000 |
|||
|
|||
.set mips64 |
|||
dmfc0 t1, COP_0_TLB_PG_MASK, 1 |
|||
or t1, t1, t0 |
|||
dmtc0 t1, COP_0_TLB_PG_MASK, 1 |
|||
|
|||
dmfc0 t0, COP_0_CONFIG, 3 |
|||
ori t0, t0, 0x80 |
|||
dmtc0 t0, COP_0_CONFIG, 3 |
|||
.set mips3 |
|||
|
|||
li t0, 0x01ffe000 |
|||
mtc0 t0, COP_0_TLB_PG_MASK # 16MB page |
|||
|
|||
li t0, 31 |
|||
|
|||
li t3, 0xc0000000 # entry_hi |
|||
#dli t4, (0x00000e0040000000 >> 6)|0x17 # entry_lo, uncached, valid, dirty, global |
|||
#li t4, 0x0e004000 |
|||
|
|||
li t4, 0x00004000 |
|||
#li t4, 0x0efdf000 |
|||
|
|||
.set mips64 |
|||
dsll t4, t4, 10 |
|||
.set mips3 |
|||
ori t4, t4, 0x17 |
|||
|
|||
li t5, (0x1000000>>6) # 16M stride |
|||
li t6, 0x2000000 # VPN2 32M stride |
|||
|
|||
.set mips64 |
|||
1: |
|||
dmtc0 t3, COP_0_TLB_HI |
|||
daddu t3, t3, t6 |
|||
|
|||
dmtc0 t4, COP_0_TLB_LO0 |
|||
daddu t4, t4, t5 |
|||
dmtc0 t4, COP_0_TLB_LO1 |
|||
daddu t4, t4, t5 |
|||
|
|||
.set mips3 |
|||
|
|||
mtc0 t0, COP_0_TLB_INDEX # 16MB page |
|||
nop |
|||
nop |
|||
nop |
|||
nop |
|||
nop |
|||
tlbwi # random++ |
|||
|
|||
bgez t0, 1b |
|||
addiu t0, t0, -1 |
|||
|
|||
|
|||
li t0, 32 |
|||
mtc0 t0, COP_0_TLB_WIRED # 16MB page |
|||
|
|||
|
|||
|
|||
/***********************************************************************************************************/ |
|||
/**************************************** MAP KUSEG ********************************************************/ |
|||
/** MAP virtual address: 0x40000000~ 0x7fffffff to physical address: 0x80000000~ 0xbfffffff for SYS-MEM **/ |
|||
/***********************************************************************************************************/ |
|||
|
|||
#ifdef CONFIG_GFXUMA /* for UMA mode. */ |
|||
|
|||
li t0, 0x80000000 |
|||
|
|||
.set mips64 |
|||
dmfc0 t1, COP_0_TLB_PG_MASK, 1 |
|||
or t1, t1, t0 |
|||
dmtc0 t1, COP_0_TLB_PG_MASK, 1 |
|||
|
|||
dmfc0 t0, COP_0_CONFIG, 3 |
|||
ori t0, t0, 0x80 |
|||
dmtc0 t0, COP_0_CONFIG, 3 |
|||
.set mips3 |
|||
|
|||
li t0, 0x01ffe000 |
|||
mtc0 t0, COP_0_TLB_PG_MASK # 16MB page |
|||
|
|||
li t0, 63 |
|||
|
|||
li t3, 0x40000000 # entry_hi |
|||
#dli t4, (0x00000e0040000000 >> 6)|0x17 # entry_lo, uncached, valid, dirty, global |
|||
#li t4, 0x0e004000 |
|||
|
|||
li t4, 0x00008000 |
|||
|
|||
#li t4, 0x0efdf000 |
|||
|
|||
.set mips64 |
|||
dsll t4, t4, 10 |
|||
.set mips3 |
|||
ori t4, t4, 0x17 |
|||
|
|||
li t5, (0x1000000>>6) # 16M stride |
|||
li t6, 0x2000000 # VPN2 32M stride |
|||
|
|||
.set mips64 |
|||
li t7, 32 |
|||
1: |
|||
dmtc0 t3, COP_0_TLB_HI |
|||
daddu t3, t3, t6 |
|||
|
|||
dmtc0 t4, COP_0_TLB_LO0 |
|||
daddu t4, t4, t5 |
|||
dmtc0 t4, COP_0_TLB_LO1 |
|||
daddu t4, t4, t5 |
|||
|
|||
.set mips3 |
|||
|
|||
mtc0 t0, COP_0_TLB_INDEX # 16MB page |
|||
nop |
|||
nop |
|||
nop |
|||
nop |
|||
nop |
|||
tlbwi # random++ |
|||
|
|||
#bnez t0, 1b |
|||
addiu t0, t0, -1 |
|||
bge t0, t7, 1b |
|||
nop |
|||
|
|||
|
|||
li t0, 64 |
|||
mtc0 t0, COP_0_TLB_WIRED # 16MB page |
|||
|
|||
#endif |
|||
@ -0,0 +1,768 @@ |
|||
|
|||
//extern onintr(int a,int *b);
|
|||
//#include "mips/cpu.h"
|
|||
#include "mips/prid.h" |
|||
|
|||
#include "mips.h" |
|||
#include "pmon.h" |
|||
#ifdef R3081 |
|||
#include "r3081.h" |
|||
#endif |
|||
#ifdef R3041 |
|||
#include "r3041.h" |
|||
#endif |
|||
|
|||
#include "ri.h" |
|||
|
|||
static unsigned long |
|||
mips_get_word_l(struct pt_regs *xcp, void *va, int *perr) |
|||
{ |
|||
*perr = 0; |
|||
return(*(unsigned long *)va); |
|||
} |
|||
|
|||
static int |
|||
mips_put_word_l(struct pt_regs *xcp, void *va, unsigned long val) |
|||
{ |
|||
*(unsigned long *)va = val; |
|||
return 0; |
|||
} |
|||
|
|||
static int emu_lwl(struct pt_regs * regs,mips_instruction ir,vaddr_t_l emulpc) |
|||
{ int err = 0; |
|||
/*the "ir" is the instruction causing the exception*/ |
|||
/*get the real address,perhaps the address is not word aligned*/ |
|||
void *va = REG_TO_VA_l (regs->regs[MIPSInst_RS(ir)])+ MIPSInst_SIMM(ir); |
|||
|
|||
unsigned long addr = 0; |
|||
unsigned long emul_pc = (unsigned long)emulpc; |
|||
|
|||
unsigned long little_three_bits; |
|||
unsigned long value,value_tmp; |
|||
|
|||
// printf("emu_lwl\r\n");
|
|||
|
|||
/*compute the correct position in the RT*/ |
|||
/*note !!!!: we have supposed the CPU is little_Endianness and status regiester's RE bit =0 */ |
|||
/*little Endianness*/ |
|||
little_three_bits = (unsigned long)va&(0x7); |
|||
value_tmp = regs->regs[MIPSInst_RT(ir)]; |
|||
switch(little_three_bits) { |
|||
case 0: |
|||
case 4: |
|||
/*must check lwl valid*/ |
|||
addr = (unsigned long) va; |
|||
check_axs(emul_pc,addr,4); |
|||
value = mips_get_word_l(regs,va,&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
value<<=24; |
|||
value_tmp &= 0xffffff; |
|||
regs->regs[MIPSInst_RT(ir)] =value_tmp|value; |
|||
break; |
|||
|
|||
case 1: |
|||
case 5: |
|||
addr = (unsigned long)va -1; |
|||
check_axs(emul_pc,addr,4); |
|||
value = mips_get_word_l(regs,(void *)((unsigned long) va-1),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
value<<=16; |
|||
value_tmp&=0xffff; |
|||
regs->regs[MIPSInst_RT(ir)] =value_tmp|value; |
|||
break; |
|||
|
|||
case 2: |
|||
case 6: |
|||
addr = (unsigned long)va - 2; |
|||
check_axs(emul_pc,addr,4); |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-2),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
|
|||
} |
|||
value<<=8; |
|||
value_tmp &= 0xff; |
|||
regs->regs[MIPSInst_RT(ir)] =value_tmp|value; |
|||
break; |
|||
|
|||
case 3: |
|||
case 7: |
|||
addr = (unsigned long)va - 3; |
|||
check_axs(emul_pc,addr,4); |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-3),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
}; |
|||
regs->regs[MIPSInst_RT(ir)] = value; |
|||
break; |
|||
} /*swith ended*/ |
|||
return 0; |
|||
|
|||
} |
|||
|
|||
static int emu_lwr(struct pt_regs *regs,mips_instruction ir,vaddr_t_l emulpc) |
|||
{ int err = 0; |
|||
/*the "ir" is the instruction causing the exception*/ |
|||
/*get the real address,perhaps the address is not word aligned*/ |
|||
void *va = REG_TO_VA_l (regs->regs[MIPSInst_RS(ir)]) |
|||
+ MIPSInst_SIMM(ir); |
|||
unsigned long addr; |
|||
unsigned long emul_pc = (unsigned long)emulpc; |
|||
unsigned long little_three_bits; |
|||
unsigned long value,value_tmp; |
|||
|
|||
// printf("emu_lwr\r\n");
|
|||
|
|||
/*compute the correct position in the RT*/ |
|||
/*note !!!!: we have supposed the CPU is little_Endianness and status regiester's RE bit =0 */ |
|||
little_three_bits = (unsigned long)va&(0x7); |
|||
value_tmp = regs->regs[MIPSInst_RT(ir)]; |
|||
switch(little_three_bits) { |
|||
case 0: |
|||
case 4: |
|||
/*must check lwl valid*/ |
|||
addr = (unsigned long)va ; |
|||
check_axs(emul_pc,addr,4); |
|||
value = mips_get_word_l(regs,va,&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
regs->regs[MIPSInst_RT(ir)] =value; |
|||
break; |
|||
|
|||
case 1: |
|||
case 5: |
|||
addr = (unsigned long)va -1; |
|||
check_axs(emul_pc,addr,4); |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-1),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
value>>=8; |
|||
value_tmp&=0xff000000; |
|||
regs->regs[MIPSInst_RT(ir)] =value_tmp|value; |
|||
break; |
|||
|
|||
case 2: |
|||
case 6: |
|||
addr = (unsigned long)va-2; |
|||
check_axs(emul_pc,addr,4); |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-2),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
|
|||
} |
|||
value>>=16; |
|||
value_tmp &= 0xffff0000; |
|||
regs->regs[MIPSInst_RT(ir)] =value_tmp|value; |
|||
break; |
|||
|
|||
case 3: |
|||
case 7: |
|||
addr = (unsigned long)va -3; |
|||
check_axs(emul_pc,addr,4); |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-3),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
}; |
|||
value>>=24; |
|||
value_tmp &= 0xffffff00; |
|||
regs->regs[MIPSInst_RT(ir)] = value_tmp|value; |
|||
break; |
|||
} /*swith ended*/ |
|||
return 0; |
|||
} |
|||
|
|||
static int emu_swl(struct pt_regs *regs,mips_instruction ir, vaddr_t_l emulpc) |
|||
{ |
|||
int err = 0; |
|||
/*the "ir" is the instruction causing the exception*/ |
|||
/*get the real address,perhaps the address is not word aligned*/ |
|||
void *va = REG_TO_VA_l (regs->regs[MIPSInst_RS(ir)]) |
|||
+ MIPSInst_SIMM(ir); |
|||
unsigned long addr; |
|||
unsigned long emul_pc = (unsigned long)emulpc; |
|||
unsigned long little_three_bits; |
|||
unsigned long value,value_tmp; |
|||
|
|||
// printf("emu_swl\r\n");
|
|||
|
|||
/*compute the correct position in the RT*/ |
|||
/*note !!!!: we have supposed the CPU is little_Endianness and status re
|
|||
* giester's RE bit =0 */ |
|||
little_three_bits = (unsigned long)va&(0x7); |
|||
value_tmp = regs->regs[MIPSInst_RT(ir)]; |
|||
switch(little_three_bits) { |
|||
case 0: |
|||
case 4: |
|||
addr = (unsigned long)va; |
|||
check_axs(emul_pc,addr,4); |
|||
value_tmp >>= 24; |
|||
value = mips_get_word_l(regs,va,&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
value &=0xffffff00; |
|||
value |= value_tmp; |
|||
if(mips_put_word_l(regs,va,value)){ |
|||
return SIGBUS; |
|||
} |
|||
break; |
|||
case 1: |
|||
case 5: |
|||
addr = (unsigned long)va -1; |
|||
check_axs(emul_pc,addr,4); |
|||
value_tmp >>= 16; |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-1),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
value &=0xffff0000; |
|||
value |= value_tmp; |
|||
if(mips_put_word_l(regs,(void *)((unsigned long)va-1),value)){ |
|||
return SIGBUS; |
|||
} |
|||
break; |
|||
case 2: |
|||
case 6: |
|||
addr = (unsigned long)va - 2; |
|||
check_axs(emul_pc,addr,4); |
|||
value_tmp >>= 8; |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-2),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
value &=0xff000000; |
|||
value |= value_tmp; |
|||
if(mips_put_word_l(regs,(void *)((unsigned long)va-2),value)){ |
|||
return SIGBUS; |
|||
} |
|||
break; |
|||
case 3: |
|||
case 7: |
|||
addr = (unsigned long)va - 3; |
|||
check_axs(emul_pc,addr,4); |
|||
value = value_tmp; |
|||
|
|||
if(mips_put_word_l(regs,(void *)((unsigned long)va-3),value)){ |
|||
return SIGBUS; |
|||
} |
|||
break; |
|||
} |
|||
return 0; |
|||
|
|||
} |
|||
|
|||
static int emu_swr(struct pt_regs *regs,mips_instruction ir, vaddr_t_l emulpc) |
|||
{ |
|||
int err = 0; |
|||
/*the "ir" is the instruction causing the exception*/ |
|||
/*get the real address,perhaps the address is not word aligned*/ |
|||
void *va = REG_TO_VA_l (regs->regs[MIPSInst_RS(ir)]) |
|||
+ MIPSInst_SIMM(ir); |
|||
unsigned long addr; |
|||
unsigned long emul_pc = (unsigned long)emulpc; |
|||
|
|||
|
|||
unsigned long little_three_bits; |
|||
unsigned long value,value_tmp; |
|||
|
|||
// printf("emu_swr\r\n");
|
|||
|
|||
/*compute the correct position in the RT*/ |
|||
/*note !!!!: we have supposed the CPU is little_Endianness and status re
|
|||
* giester's RE bit =0 */ |
|||
little_three_bits = (unsigned long)va&(0x7); |
|||
value_tmp = regs->regs[MIPSInst_RT(ir)]; |
|||
switch(little_three_bits) { |
|||
case 0: |
|||
case 4: |
|||
addr = (unsigned long) va; |
|||
check_axs(emul_pc,addr,4); |
|||
value = value_tmp; |
|||
if(mips_put_word_l(regs,va,value)){ |
|||
return SIGBUS; |
|||
} |
|||
break; |
|||
case 1: |
|||
case 5: |
|||
addr = (unsigned long)va -1; |
|||
check_axs(emul_pc,addr,4); |
|||
value_tmp <<= 8; |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-1),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
value &=0xff; |
|||
value |= value_tmp; |
|||
if(mips_put_word_l(regs,(void *)((unsigned long)va-1),value)){ |
|||
return SIGBUS; |
|||
} |
|||
break; |
|||
case 2: |
|||
case 6: |
|||
addr = (unsigned long)va - 2; |
|||
check_axs(emul_pc,addr,4); |
|||
value_tmp <<= 16; |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-2),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
value &=0xffff; |
|||
value |= value_tmp; |
|||
if(mips_put_word_l(regs,(void *)((unsigned long)va-2),value)){ |
|||
return SIGBUS; |
|||
} |
|||
break; |
|||
case 3: |
|||
case 7: |
|||
addr = (unsigned long)va -3; |
|||
check_axs(emul_pc,addr,4); |
|||
value_tmp <<= 24; |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-3),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
|
|||
value &= 0xffffff; |
|||
value |= value_tmp; |
|||
if(mips_put_word_l(regs,(void *)((unsigned long)va-3),value)){ |
|||
return SIGBUS; |
|||
} |
|||
break; |
|||
} |
|||
return 0; |
|||
|
|||
} |
|||
|
|||
|
|||
|
|||
static int emu_div(struct pt_regs *regs,mips_instruction ir) |
|||
{ |
|||
int x,y; |
|||
int flag = 0; |
|||
int quotient = 0,remainder = 0; |
|||
unsigned int absx,absy,absquotient = 0,absremainder = 0,bm = 1; |
|||
/*the "ir" is the instruction causing the exception*/ |
|||
x = regs->regs[MIPSInst_RS(ir)]; |
|||
y = regs->regs[MIPSInst_RT(ir)]; |
|||
|
|||
#ifdef __test_ri__ |
|||
//printf("now in function:emu_div().\r\n");
|
|||
#endif |
|||
|
|||
if( y == 0 ) {/*overflow*/ |
|||
return SIGABRT; |
|||
} |
|||
/*x and y ?????Ƿ???ͬ*/ |
|||
flag = (x&0x80000000)^(y&0x80000000); |
|||
|
|||
/*get the abs(x)*/ |
|||
if(x<0){ |
|||
absx = (unsigned int)-x; |
|||
}else { |
|||
absx = (unsigned int)x; |
|||
} |
|||
|
|||
/*get the abs(y)*/ |
|||
if(y<0){ |
|||
absy = (unsigned int) -y; |
|||
}else { |
|||
absy = (unsigned int)y; |
|||
} |
|||
|
|||
/*caculate the absx/absy*/ |
|||
if(absx<absy) {/*don't need to calculate*/ |
|||
absquotient = 0; |
|||
absremainder = absx; |
|||
goto end; |
|||
} |
|||
|
|||
while(!(absy&0x80000000)) |
|||
{ absy<<=1; |
|||
if(absx<absy){ |
|||
absy>>= 1; |
|||
break; |
|||
} |
|||
bm<<=1; |
|||
} |
|||
|
|||
for(;bm;bm>>=1){ |
|||
if(absx>=absy){ |
|||
absx -= absy; |
|||
absquotient |= bm; |
|||
if(absx == 0) |
|||
break; |
|||
} |
|||
absy >>= 1; |
|||
} |
|||
absremainder = absx; |
|||
|
|||
end: |
|||
if( flag ){/*????????*/ |
|||
quotient = -absquotient; |
|||
remainder = x-quotient*y; |
|||
}else { |
|||
quotient = absquotient; |
|||
remainder = x - quotient*y; |
|||
} |
|||
|
|||
regs->lo =(unsigned long)quotient; |
|||
regs->hi = (unsigned long)remainder; |
|||
|
|||
#ifdef __test_ri__ |
|||
// printf("x is: %d\r\n",x);
|
|||
// printf("y is: %d\r\n",y);
|
|||
// printf("result is: %d (:\r\n",quotient);
|
|||
#endif |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
static int emu_divu(struct pt_regs *regs,mips_instruction ir) |
|||
{ |
|||
unsigned int x,y,bm=1; |
|||
unsigned int quotient = 0,remainder = 0; |
|||
|
|||
/*the "ir" is the instruction causing the exception*/ |
|||
x = regs->regs[MIPSInst_RS(ir)]; |
|||
y = regs->regs[MIPSInst_RT(ir)]; |
|||
|
|||
if( y == 0 ) {/*overflow*/ |
|||
return SIGABRT; |
|||
} |
|||
|
|||
if(x<y) {/*don't need to calculate*/ |
|||
quotient = 0; |
|||
remainder = x; |
|||
goto end; |
|||
} |
|||
|
|||
while(!(y&0x80000000)) |
|||
{ y<<=1; |
|||
if(x<y){ |
|||
y>>= 1; |
|||
break; |
|||
} |
|||
bm<<=1; |
|||
} |
|||
|
|||
for(;bm;bm>>=1){ |
|||
if(x>=y){ |
|||
x -= y; |
|||
quotient |= bm; |
|||
if(x == 0) |
|||
break; |
|||
} |
|||
y >>= 1; |
|||
|
|||
} |
|||
remainder = x; |
|||
end: |
|||
regs->lo = quotient; |
|||
regs->hi = remainder; |
|||
return 0; |
|||
|
|||
} |
|||
|
|||
/*
|
|||
* Compute the return address and do emulate branch simulation, if required. |
|||
*/ |
|||
#define EFAULT 1 |
|||
int __compute_return_epc(struct pt_regs *regs) |
|||
{ |
|||
unsigned int *addr, bit, fcr31; |
|||
long epc; |
|||
mips_instruction insn; |
|||
|
|||
epc = regs->cp0_epc; |
|||
if (epc & 3) { |
|||
printf("%s: unaligned epc - sending SIGBUS.\n"); |
|||
// force_sig(SIGBUS, current);
|
|||
return -EFAULT; |
|||
} |
|||
|
|||
/*
|
|||
* Read the instruction |
|||
*/ |
|||
addr = (unsigned int *) (unsigned long) epc; |
|||
#if 0 |
|||
if (__get_user(insn, addr)) { |
|||
printf("%s: bad epc value - sending SIGSEGV.\n"); |
|||
// force_sig(SIGSEGV, current);
|
|||
return -EFAULT; |
|||
} |
|||
#endif |
|||
//bjzheng add __get_user is prevent page_fault exception,if this occurs,load from disk,but now my whole code is in ram.
|
|||
insn=*addr; |
|||
// printf("instruction is %x",insn);
|
|||
regs->regs[0] = 0; |
|||
switch (MIPSInst_OPCODE(insn)) { |
|||
/*
|
|||
* jr and jalr are in r_format format. |
|||
*/ |
|||
case spec_op: |
|||
switch (MIPSInst_FUNC(insn)) { |
|||
case jalr_op: |
|||
regs->regs[MIPSInst_RD(insn)] = epc + 8; |
|||
/* Fall through */ |
|||
case jr_op: |
|||
regs->cp0_epc = regs->regs[MIPSInst_RS(insn)]; |
|||
break; |
|||
} |
|||
break; |
|||
|
|||
/*
|
|||
* This group contains: |
|||
* bltz_op, bgez_op, bltzl_op, bgezl_op, |
|||
* bltzal_op, bgezal_op, bltzall_op, bgezall_op. |
|||
*/ |
|||
case bcond_op: |
|||
switch (MIPSInst_RT(insn)) { |
|||
case bltz_op: |
|||
case bltzl_op: |
|||
if ((long)regs->regs[MIPSInst_RS(insn)] < 0) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
case bgez_op: |
|||
case bgezl_op: |
|||
if ((long)regs->regs[MIPSInst_RS(insn)] >= 0) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
case bltzal_op: |
|||
case bltzall_op: |
|||
regs->regs[31] = epc + 8; |
|||
if ((long)regs->regs[MIPSInst_RS(insn)] < 0) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
case bgezal_op: |
|||
case bgezall_op: |
|||
regs->regs[31] = epc + 8; |
|||
if ((long)regs->regs[MIPSInst_RS(insn)] >= 0) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
} |
|||
break; |
|||
|
|||
/*
|
|||
* These are unconditional and in j_format. |
|||
*/ |
|||
case jal_op: |
|||
regs->regs[31] = regs->cp0_epc + 8; |
|||
case j_op: |
|||
epc += 4; |
|||
epc >>= 28; |
|||
epc <<= 28; |
|||
epc |= (MIPSInst_JTARGET(insn) << 2); |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
/*
|
|||
* These are conditional and in i_format. |
|||
*/ |
|||
case beq_op: |
|||
case beql_op: |
|||
if (regs->regs[MIPSInst_RS(insn)] == |
|||
regs->regs[MIPSInst_RT(insn)]) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
case bne_op: |
|||
case bnel_op: |
|||
if (regs->regs[MIPSInst_RS(insn)] != |
|||
regs->regs[MIPSInst_RT(insn)]) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
case blez_op: /* not really i_format */ |
|||
case blezl_op: |
|||
/* rt field assumed to be zero */ |
|||
if ((long)regs->regs[MIPSInst_RS(insn)] <= 0) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
case bgtz_op: |
|||
case bgtzl_op: |
|||
/* rt field assumed to be zero */ |
|||
if ((long)regs->regs[MIPSInst_RS(insn)] > 0) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
/*
|
|||
* And now the FPA/cp1 branch instructions. |
|||
*/ |
|||
case cop1_op: |
|||
#ifdef CONFIG_MIPS_FPU_EMULATOR |
|||
if(!(mips_cpu.options & MIPS_CPU_FPU)) |
|||
fcr31 = current->tss.fpu.soft.sr; |
|||
else |
|||
#endif |
|||
asm ("cfc1\t%0,$31":"=r" (fcr31)); |
|||
bit = (MIPSInst_RT(insn) >> 2); |
|||
bit += (bit != 0); |
|||
bit += 23; |
|||
switch (MIPSInst_RT(insn)) { |
|||
case 0: /* bc1f */ |
|||
case 2: /* bc1fl */ |
|||
if (~fcr31 & (1 << bit)) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
case 1: /* bc1t */ |
|||
case 3: /* bc1tl */ |
|||
if (fcr31 & (1 << bit)) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
} |
|||
break; |
|||
} |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
int do_ri (struct pt_regs *xcp) |
|||
{ |
|||
mips_instruction ir; |
|||
vaddr_t_l emulpc; |
|||
vaddr_t_l contpc; |
|||
int err = 0; |
|||
int sig; |
|||
|
|||
|
|||
ir = mips_get_word_l(xcp, REG_TO_VA_l xcp->cp0_epc, &err); |
|||
if (err) { |
|||
return SIGBUS; |
|||
} |
|||
|
|||
/* XXX NEC Vr54xx bug workaround */ |
|||
/* if ((xcp->cp0_cause & CAUSEF_BD) && !isBranchInstr (&ir))
|
|||
xcp->cp0_cause &= ~CAUSEF_BD;*/ |
|||
|
|||
if (xcp->cp0_cause & CAUSEF_BD) { |
|||
|
|||
/* The instruction to be emulated is in a branch delay slot
|
|||
* which means that we have to emulate the branch instruction |
|||
* BEFORE we do the emulating instruction. |
|||
* This branch could be a COP1 branch |
|||
*/ |
|||
|
|||
emulpc = REG_TO_VA_l(xcp->cp0_epc + 4); /* Snapshot emulation target */ |
|||
|
|||
#ifndef __bjzheng__ |
|||
if( __compute_return_epc(xcp)) {/*compute the return address*/ |
|||
#ifdef DBG |
|||
_mon_printf ("failed to emulate branch at %p\n", |
|||
REG_TO_VA_l (xcp->cp0_epc)); |
|||
#endif |
|||
return -1;; |
|||
} |
|||
#endif |
|||
|
|||
ir = mips_get_word_l(xcp, emulpc, &err); |
|||
if (err) { |
|||
return SIGBUS; |
|||
} |
|||
contpc = REG_TO_VA_l xcp->cp0_epc; |
|||
|
|||
} else { /* not in the Branch delay slot*/ |
|||
emulpc = REG_TO_VA_l xcp->cp0_epc; |
|||
contpc = REG_TO_VA_l xcp->cp0_epc + 4; |
|||
} |
|||
|
|||
switch(MIPSInst_OPCODE(ir)) { |
|||
case lwl_op: /*lwl instruction*/ |
|||
sig = emu_lwl(xcp,ir,emulpc); |
|||
if( sig!=0) { /*emul has failed*/ |
|||
return sig; |
|||
} |
|||
break; |
|||
|
|||
case lwr_op:/*lwr instruction*/ |
|||
sig = emu_lwr(xcp,ir,emulpc); |
|||
if ( sig != 0){ |
|||
/*emulate has failed!\n");*/ |
|||
return sig; |
|||
} |
|||
break; |
|||
|
|||
case swl_op: |
|||
sig = emu_swl(xcp,ir,emulpc); |
|||
if( sig!=0 ) { /*emul has failed!*/ |
|||
printf("emu_swl error\r\n"); |
|||
return sig; |
|||
} |
|||
break; |
|||
|
|||
case swr_op: |
|||
sig = emu_swr(xcp,ir,emulpc); |
|||
if( sig!=0 ) { /*emul has failed!*/ |
|||
printf("emu_swr error\r\n"); |
|||
return sig; |
|||
} |
|||
break; |
|||
case spec_op: |
|||
switch (MIPSInst_FUNC(ir)){ |
|||
case div_op:/*div_op*/ |
|||
sig = emu_div(xcp,ir); |
|||
if(sig) { |
|||
return sig; |
|||
} |
|||
break; |
|||
case divu_op:/* divu_op:*/ |
|||
sig = emu_divu(xcp,ir); |
|||
if(sig) { |
|||
return sig; |
|||
} |
|||
break; |
|||
default:; |
|||
|
|||
} |
|||
|
|||
default:; |
|||
} |
|||
|
|||
|
|||
/*we do it*/ |
|||
xcp->cp0_epc = VA_TO_REG_l(contpc); |
|||
xcp->cp0_cause &= ~CAUSEF_BD; |
|||
return sig; |
|||
|
|||
} |
|||
|
|||
File diff suppressed because it is too large
File diff suppressed because it is too large
File diff suppressed because it is too large
@ -0,0 +1 @@ |
|||
include "Targets/Bonito3a8780e/conf/Bonito.3a8780e" |
|||
@ -0,0 +1,255 @@ |
|||
# $Id: Bonito,v 1.1.1.1 2006/09/14 01:59:09 root Exp $ # # GENERIC configuration for Galileo EV64240 # # This file is supposed to be included by target file after # endian has been defined. |
|||
# |
|||
machine Bonito3a8780e mips # CPU Architecture, Platform |
|||
config pmon |
|||
option VGAROM_IN_BIOS |
|||
# |
|||
# Define target endian |
|||
# |
|||
makeoptions ENDIAN=EL # Little endian version. |
|||
|
|||
|
|||
#include "conf/GENERIC_ALL" |
|||
|
|||
# |
|||
# System Name and Target Name |
|||
# |
|||
option SYSTYPE="\"Bonito\"" |
|||
option TARGETNAME="\"Bonito\"" |
|||
|
|||
# |
|||
# Platform options |
|||
# |
|||
option loongson3A3 |
|||
option LSMC_2 |
|||
#option ARB_LEVEL |
|||
option DDR3_DIMM |
|||
|
|||
option AUTO_DDR_CONFIG |
|||
option USE_SB_I2C |
|||
|
|||
option BONITOEL |
|||
option DEVBD2F |
|||
option LS3_SERVER |
|||
option MIPS |
|||
option INET |
|||
option LS3_HT # Enable the IO cache coherent of HT |
|||
#option MCP68_IDE # Enable the MCP68 IDE 0 channel |
|||
#option USE_LPC_UART |
|||
#option MULTI_CHIP |
|||
option ENABLE_SATA #Enable SATA ,when enable IDE can also use, when commended only IDE can use |
|||
option BOOTCORE_ID=0 |
|||
option RESERVED_COREMASK=0xfff4 |
|||
option SHUTDOWN_MASK=0x0f00 |
|||
|
|||
# |
|||
# Uart serial baud rate selection |
|||
# |
|||
option BONITO_33M |
|||
#option BONITO_25M |
|||
#option BONITO_50M |
|||
|
|||
option LOONGSON_3ASINGLE |
|||
option BOOT_PARAM |
|||
select amd_780e |
|||
|
|||
## VGA option ## |
|||
option SERVER_3A |
|||
option RS780E |
|||
option USE_780E_VGA |
|||
option VGA_NO_ROM |
|||
option VGA_BASE=0xbe000000 |
|||
option VRAM_SIZE=128 |
|||
#option DEBUG_EMU_VGA |
|||
#option CONFIG_GFXUMA |
|||
|
|||
# |
|||
# GPU driver selection. Selects for video |
|||
# Disable all options below to disable gpu driver |
|||
# Enable all options below to enble gpu driver |
|||
# |
|||
select mod_x86emu_int10 |
|||
select mod_framebuffer |
|||
select mod_vesa |
|||
select mod_vgacon |
|||
option VESAFB |
|||
option INTERFACE_3A780E |
|||
|
|||
# |
|||
# flash type selection. Selects flash support |
|||
# |
|||
select mod_flash_amd # AMD flash device programming |
|||
select mod_flash_intel # intel flash device programming |
|||
select mod_flash_sst # intel flash device programming |
|||
select mod_debugger # Debugging module |
|||
select mod_symbols # Symbol table handling |
|||
select mod_s3load # Srecord loading |
|||
#select mod_fastload # LSI Fastload |
|||
select mod_elfload # ELF loading |
|||
|
|||
# |
|||
# Command selection. Selects pmon commands |
|||
# |
|||
select cmd_newmt |
|||
select cmd_setup |
|||
select mod_display |
|||
select cmd_about # Display info about PMON |
|||
select cmd_boot # Boot wrapper |
|||
select cmd_mycmd |
|||
select cmd_newmt |
|||
select cmd_cache # Cache enabling |
|||
#select cmd_call # Call a function command |
|||
select cmd_date # Time of day command |
|||
select cmd_env # Full blown environment command set |
|||
select cmd_flash # Flash programming cmds |
|||
select cmd_hist # Command history |
|||
select cmd_ifaddr # Interface address command |
|||
select cmd_l # Disassemble |
|||
select cmd_mem # Memory manipulation commands |
|||
select cmd_more # More paginator |
|||
select cmd_mt # Simple memory test command |
|||
select cmd_misc # Reboot & Flush etc. |
|||
#select cmd_stty # TTY setings command |
|||
select cmd_tr # Host port-through command |
|||
select cmd_devls # Device list |
|||
select cmd_set # As cmd_env but not req. cmd_hist |
|||
select cmd_testdisk |
|||
# |
|||
select cmd_test # test commands,test hardisk |
|||
select cmd_shell # Shell commands, vers, help, eval |
|||
|
|||
#select cmd_test_sata # Sata signal test command |
|||
select cmd_test_spi |
|||
# |
|||
# |
|||
# Platform options |
|||
# |
|||
select mod_uart_ns16550 # Standard UART driver |
|||
#option CONS_BAUD=B9600 |
|||
option CONS_BAUD=B115200 |
|||
select ext2 |
|||
select fatfs |
|||
#select mod_x86emu # X86 emulation for VGA |
|||
option MY40IO |
|||
option NOPCINAMES # Save some space for x86emu |
|||
#option FASTBOOT |
|||
#select vt82c686 #via686a/b code |
|||
#option VGA_BASE=0xb0000000 |
|||
|
|||
# |
|||
# Functional options. |
|||
# |
|||
option NOSNOOP # Caches are no-snooping |
|||
|
|||
# |
|||
# HAVE options. What tgt level provide |
|||
# |
|||
option HAVE_TOD # Time-Of-Day clock |
|||
option HAVE_NVENV # Platform has non-volatile env mem |
|||
option HAVE_LOGO # Output splash logo |
|||
option USE_SUPERIO_UART |
|||
#option USE_LEGACY_RTC |
|||
#option GODSONEV2A |
|||
#option LINUX_PC |
|||
#option LONGMENG |
|||
#option RADEON7000 |
|||
#option DEBUG_EMU_VGA |
|||
option AUTOLOAD |
|||
#option CONFIG_PCI0_LARGE_MEM |
|||
#option CONFIG_PCI0_HUGE_MEM |
|||
#option CONFIG_PCI0_GAINT_MEM |
|||
option CONFIG_CACHE_64K_4WAY |
|||
option NVRAM_IN_FLASH |
|||
|
|||
# |
|||
# Now the Machine specification |
|||
# |
|||
mainbus0 at root |
|||
localbus0 at mainbus0 |
|||
loopdev0 at mainbus0 |
|||
#fd0 at mainbus0 |
|||
pcibr0 at mainbus0 |
|||
#pcibr1 at mainbus0 |
|||
pci* at pcibr? |
|||
ppb* at pci? dev ? function ? # PCI-PCI bridges |
|||
pci* at ppb? bus ? |
|||
|
|||
|
|||
#### SCSI support |
|||
#siop* at pci? dev ? function ? # Symbios/NCR 53c... |
|||
#scsibus* at siop? |
|||
#sd* at scsibus? target ? lun ? |
|||
#cd* at scsibus? target ? lun ? |
|||
|
|||
#### Networking Devices |
|||
#gt0 at localbus? base 4 |
|||
#gt1 at localbus? base 5 |
|||
#gt2 at localbus? base 6 |
|||
# fxp normally only used for debugging (enable/disable both) |
|||
fxp0 at pci? dev ? function ? # Intel 82559 Device |
|||
inphy* at mii? phy ? # Intel 82555 PHYs |
|||
# rtl* at pci? dev ? function ? |
|||
rte* at pci? dev ? function ? |
|||
#rtk* at pci? dev ? function ? |
|||
#em* at pci? dev ? function ? |
|||
|
|||
#### USB |
|||
uhci* at pci? dev ? function ? |
|||
ohci* at pci? dev ? function ? |
|||
usb* at usbbus ? |
|||
|
|||
select mod_usb |
|||
select mod_usb_storage |
|||
select mod_usb_uhci |
|||
select mod_usb_ohci |
|||
select mod_usb_kbd |
|||
|
|||
|
|||
#### IDE controllers |
|||
option IDE_DMA |
|||
pciide* at pci ? dev ? function ? flags 0x0000 |
|||
|
|||
#### IDE hard drives |
|||
wd* at pciide? channel ? drive ? flags 0x0000 |
|||
|
|||
### LSI MegaRAID SAS RAID controllers |
|||
mfi* at pci? |
|||
scsibus* at mfi? |
|||
sd* at scsibus? target ? lun ? |
|||
option CONFIG_LSI_9260 # for LSI_9260-8i(2108) RAID card support |
|||
|
|||
#### Pseudo devices |
|||
pseudo-device loop 1 # network loopback |
|||
|
|||
ide_cd* at pciide? channel ? drive ? flags 0x0001 |
|||
select iso9660 |
|||
select ramfiles |
|||
select cmd_xyzmodem |
|||
option IDECD |
|||
option HAVE_NB_SERIAL |
|||
#option USE_ENVMAC |
|||
#option LOOKLIKE_PC |
|||
#select cmd_lwdhcp |
|||
#select cmd_bootp |
|||
option FOR_GXEMUL |
|||
select fatfs |
|||
option FLOATINGPT |
|||
#option PCI_IDSEL_VIA686B=17 |
|||
option PCI_IDSEL_SB700=14 |
|||
option WDC_NORESET |
|||
select gzip |
|||
option INPUT_FROM_BOTH |
|||
option OUTPUT_TO_BOTH |
|||
#option VIA686B_POWERFIXUP |
|||
option DEVBD2F_VIA |
|||
#option USE_GPIO_SERIAL |
|||
option CONFIG_VIDEO_SW_CURSOR |
|||
select http |
|||
#select nfs |
|||
select tcp |
|||
select inet |
|||
select tftpd |
|||
#select e100 |
|||
|
|||
# SCSI RAID disk drive support |
|||
select scsi_sd |
|||
@ -0,0 +1,19 @@ |
|||
ifndef S |
|||
S:=$(shell cd ../../../..; pwd) |
|||
endif |
|||
TARGET= ${S}/Targets/Bonito3a8780e |
|||
SUBTARGET?=Bonito |
|||
CPPFLAGS=-mips3 |
|||
|
|||
%OBJS |
|||
|
|||
%CFILES |
|||
|
|||
%SFILES |
|||
|
|||
%LOAD |
|||
|
|||
export CFILES OBJS SFILES |
|||
include ${S}/Makefile.inc |
|||
|
|||
%RULES |
|||
@ -0,0 +1,54 @@ |
|||
# $Id: files.Bonito |
|||
# |
|||
# Bonito Target specific files |
|||
# |
|||
|
|||
file Targets/Bonito3a8780e/pci/pci_machdep.c |
|||
file Targets/Bonito3a8780e/Bonito/tgt_machdep.c |
|||
file Targets/Bonito3a8780e/pci/cs5536_io.c cs5536 |
|||
file Targets/Bonito3a8780e/pci/cs5536_vsm.c cs5536 |
|||
file Targets/Bonito3a8780e/pci/rs780_cmn.c amd_780e |
|||
file Targets/Bonito3a8780e/pci/amd_780e.c amd_780e |
|||
file Targets/Bonito3a8780e/pci/sb700.c amd_780e |
|||
file Targets/Bonito3a8780e/pci/sb700_ide.c amd_780e |
|||
file Targets/Bonito3a8780e/pci/sb700_lpc.c amd_780e |
|||
file Targets/Bonito3a8780e/pci/sb700_sata.c amd_780e |
|||
file Targets/Bonito3a8780e/pci/sb700_usb.c amd_780e |
|||
|
|||
file pmon/cmds/msqt.c cmd_test_sata |
|||
|
|||
define localbus { [base = -1 ] } |
|||
device localbus |
|||
attach localbus at mainbus |
|||
file Targets/Bonito2fdev/dev/localbus.c localbus |
|||
|
|||
|
|||
# Ethernet driver for Discovery ethernet |
|||
device gt: ether, ifnet, ifmedia |
|||
attach gt at localbus |
|||
file sys/dev/ic/if_gt.c gt |
|||
|
|||
# |
|||
# Media Indepedent Interface (mii) |
|||
# |
|||
include "sys/dev/mii/files.mii" |
|||
|
|||
# Various PCI bridges |
|||
|
|||
include "sys/dev/pci/files.pci" |
|||
|
|||
# |
|||
# Machine-independent ATAPI drivers |
|||
# |
|||
|
|||
include "sys/dev/ata/files.ata" |
|||
|
|||
# |
|||
# SCSI framework |
|||
# |
|||
include "sys/scsi/files.scsi" |
|||
|
|||
# |
|||
# Custom application files |
|||
# |
|||
include "pmon/custom/files.custom" |
|||
@ -0,0 +1,105 @@ |
|||
|
|||
OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradbigmips", |
|||
"elf32-tradlittlemips") |
|||
OUTPUT_ARCH(mips) |
|||
ENTRY(_start) |
|||
SECTIONS |
|||
{ |
|||
|
|||
. = 0xffffffff8f010000; |
|||
.text : |
|||
{ |
|||
_ftext = . ; |
|||
*(.text) |
|||
*(.rodata) |
|||
*(.rodata1) |
|||
*(.reginfo) |
|||
*(.init) |
|||
*(.stub) |
|||
|
|||
*(.gnu.warning) |
|||
} =0 |
|||
_etext = .; |
|||
PROVIDE (etext = .); |
|||
.fini : { *(.fini) } =0 |
|||
.data : |
|||
{ |
|||
_fdata = . ; |
|||
*(.data) |
|||
. = ALIGN(32); |
|||
*(.data.align32) |
|||
. = ALIGN(64); |
|||
*(.data.align64) |
|||
. = ALIGN(128); |
|||
*(.data.align128) |
|||
. = ALIGN(4096); |
|||
*(.data.align4096) |
|||
CONSTRUCTORS |
|||
} |
|||
.data1 : { *(.data1) } |
|||
.ctors : |
|||
{ |
|||
__CTOR_LIST__ = .; |
|||
LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) |
|||
*(.ctors) |
|||
LONG(0) |
|||
__CTOR_END__ = .; |
|||
} |
|||
.dtors : |
|||
{ |
|||
__DTOR_LIST__ = .; |
|||
LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) |
|||
*(.dtors) |
|||
LONG(0) |
|||
__DTOR_END__ = .; |
|||
} |
|||
_gp = ALIGN(16) + 0x7ff0; |
|||
.got : |
|||
{ |
|||
*(.got.plt) *(.got) |
|||
} |
|||
|
|||
|
|||
|
|||
.sdata : { *(.sdata) } |
|||
.lit8 : { *(.lit8) } |
|||
.lit4 : { *(.lit4) } |
|||
_edata = .; |
|||
PROVIDE (edata = .); |
|||
__bss_start = .; |
|||
_fbss = .; |
|||
.sbss : { *(.sbss) *(.scommon) } |
|||
.bss : |
|||
{ |
|||
*(.dynbss) |
|||
*(.bss) |
|||
. = ALIGN(32); |
|||
*(.bss.align32) |
|||
. = ALIGN(64); |
|||
*(.bss.align64) |
|||
. = ALIGN(128); |
|||
*(.bss.align128) |
|||
. = ALIGN(4096); |
|||
*(.bss.align4096) |
|||
*(COMMON) |
|||
} |
|||
_end = . ; |
|||
PROVIDE (end = .); |
|||
|
|||
|
|||
.stab 0 : { *(.stab) } |
|||
.stabstr 0 : { *(.stabstr) } |
|||
|
|||
|
|||
|
|||
|
|||
.debug 0 : { *(.debug) } |
|||
.debug_srcinfo 0 : { *(.debug_srcinfo) } |
|||
.debug_aranges 0 : { *(.debug_aranges) } |
|||
.debug_pubnames 0 : { *(.debug_pubnames) } |
|||
.debug_sfnames 0 : { *(.debug_sfnames) } |
|||
.line 0 : { *(.line) } |
|||
|
|||
.gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } |
|||
.gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } |
|||
} |
|||
@ -0,0 +1,195 @@ |
|||
/* $Id: localbus.c,v 1.1.1.1 2006/09/14 01:59:09 root Exp $ */ |
|||
|
|||
/*
|
|||
* Copyright (c) 2001 Opsycon AB (www.opsycon.se) |
|||
* |
|||
* Redistribution and use in source and binary forms, with or without |
|||
* modification, are permitted provided that the following conditions |
|||
* are met: |
|||
* 1. Redistributions of source code must retain the above copyright |
|||
* notice, this list of conditions and the following disclaimer. |
|||
* 2. Redistributions in binary form must reproduce the above copyright |
|||
* notice, this list of conditions and the following disclaimer in the |
|||
* documentation and/or other materials provided with the distribution. |
|||
* 3. All advertising materials mentioning features or use of this software |
|||
* must display the following acknowledgement: |
|||
* This product includes software developed by Opsycon AB, Sweden. |
|||
* 4. The name of the author may not be used to endorse or promote products |
|||
* derived from this software without specific prior written permission. |
|||
* |
|||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS |
|||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
|||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
|||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
|||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
|||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
|||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
|||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
|||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
|||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
|||
* SUCH DAMAGE. |
|||
* |
|||
*/ |
|||
|
|||
/*
|
|||
* This is the localbus driver. It handles configuration of all |
|||
* devices on the Discovery localbus. |
|||
*/ |
|||
|
|||
#include <sys/param.h> |
|||
#include <sys/systm.h> |
|||
#include <sys/conf.h> |
|||
#include <sys/malloc.h> |
|||
#include <sys/device.h> |
|||
#include <sys/tty.h> |
|||
|
|||
#include <autoconf.h> |
|||
|
|||
#include <pmon/dev/gt64240reg.h> |
|||
|
|||
int localbusmatch __P((struct device *, void *, void *)); |
|||
void localbusattach __P((struct device *, struct device *, void *)); |
|||
int localbusprint __P((void *, const char *)); |
|||
void localbusscan __P((struct device *, void *)); |
|||
|
|||
|
|||
struct cfattach localbus_ca = { |
|||
sizeof(struct device), localbusmatch, localbusattach |
|||
}; |
|||
|
|||
struct cfdriver localbus_cd = { |
|||
NULL, "localbus", DV_DULL, 1 |
|||
}; |
|||
|
|||
int |
|||
localbusmatch(parent, match, aux) |
|||
struct device *parent; |
|||
void *match; |
|||
void *aux; |
|||
{ |
|||
return (1); |
|||
} |
|||
|
|||
int |
|||
localbusprint(aux, localbus) |
|||
void *aux; |
|||
const char *localbus; |
|||
{ |
|||
/* XXXX print flags */ |
|||
return (QUIET); |
|||
} |
|||
|
|||
|
|||
void |
|||
localbusscan(parent, match) |
|||
struct device *parent; |
|||
void *match; |
|||
{ |
|||
struct device *dev = match; |
|||
struct cfdata *cf = dev->dv_cfdata; |
|||
struct confargs lba; |
|||
bushook_t lbus; |
|||
|
|||
if (cf->cf_fstate == FSTATE_STAR) { |
|||
printf("localbus '*' devs not allowed!\n"); |
|||
free(dev, M_DEVBUF); |
|||
} |
|||
|
|||
if (cf->cf_loc[0] == -1) { |
|||
lba.ca_baseaddr = 0; |
|||
lba.ca_intr = 0; |
|||
lba.ca_nintr = 0; |
|||
} else { |
|||
lba.ca_baseaddr = cf->cf_loc[0]; |
|||
lba.ca_nintr= cf->cf_loc[1]; |
|||
lba.ca_intr = 0; |
|||
} |
|||
|
|||
lba.ca_bus = &lbus; |
|||
lba.ca_bus->bh_type = BUS_LOCAL; |
|||
lba.ca_bus->bh_matchname = NULL; |
|||
|
|||
#if 0 |
|||
lba.ca_iot = &sys_config.local; |
|||
lba.ca_memt = &sys_config.local; |
|||
#endif |
|||
|
|||
|
|||
if ((*cf->cf_attach->ca_match)(parent, dev, &lba) > 0) { |
|||
config_attach(parent, dev, &lba, localbusprint); |
|||
} |
|||
else { |
|||
free(dev, M_DEVBUF); |
|||
} |
|||
} |
|||
|
|||
void |
|||
localbusattach(parent, self, aux) |
|||
struct device *parent; |
|||
struct device *self; |
|||
void *aux; |
|||
{ |
|||
printf("\n"); |
|||
|
|||
config_scan(localbusscan, self); |
|||
} |
|||
|
|||
#if 0 |
|||
|
|||
void |
|||
gt64240_map() |
|||
{ |
|||
u_int32_t rval; |
|||
|
|||
static int gt64240_initialized; |
|||
|
|||
if(!gt64240_initialized) { |
|||
/*
|
|||
* Map GT register space. We map the entire chip at |
|||
* once since functions are scattered all over the |
|||
* address space and mapping functionwise would |
|||
* require a lot of small mappings. |
|||
* The objects gt64240_bt and gt64240_bh can |
|||
* be used by all functions require access to the GT. |
|||
*/ |
|||
if(bus_space_map(&sys_config.local, GT_REG(0), 65536, |
|||
0, >64240_bh) != 0 ) { |
|||
panic("localbus: unable to map GT64240 regs\n"); |
|||
} |
|||
gt64240_bt = &sys_config.local; |
|||
gt64240_initialized = 1; |
|||
|
|||
/*
|
|||
* Kill any active ethernet channels. |
|||
*/ |
|||
GT_WRITE(ETHERNET0_PORT_CONFIGURATION_REGISTER, 0); |
|||
GT_WRITE(ETHERNET1_PORT_CONFIGURATION_REGISTER, 0); |
|||
GT_WRITE(ETHERNET2_PORT_CONFIGURATION_REGISTER, 0); |
|||
GT_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER, 0); |
|||
GT_WRITE(ETHERNET1_SDMA_COMMAND_REGISTER, 0); |
|||
GT_WRITE(ETHERNET2_SDMA_COMMAND_REGISTER, 0); |
|||
|
|||
/*
|
|||
* Initialize the interrupt controller. Route MPP pins. |
|||
*/ |
|||
rval = GT_READ(MPP_CONTROL3); |
|||
rval &= 0xff0f00ff; /* Reset bits 29 and 27 */ |
|||
GT_WRITE(MPP_CONTROL3, rval); |
|||
|
|||
rval = GT_READ(MPP_CONTROL2); |
|||
rval &= 0xf00fffff; /* Reset bits 22 and 21 */ |
|||
GT_WRITE(MPP_CONTROL2, rval); |
|||
|
|||
rval = GT_READ(GPP_LEVEL_CONTROL); |
|||
rval |= 0x28600000; /* Active low transition == int */ |
|||
GT_WRITE(GPP_LEVEL_CONTROL, rval); |
|||
|
|||
rval = GT_READ(GPP_INTERRUPT_MASK); |
|||
rval |= 0x28600000; /* Enable PCI + Serial */ |
|||
GT_WRITE(GPP_INTERRUPT_MASK, rval); |
|||
/* Clear all pending ints. */ |
|||
GT_WRITE(GPP_INTERRUPT_CAUSE, 0); |
|||
} |
|||
return; |
|||
} |
|||
#endif |
|||
@ -0,0 +1,54 @@ |
|||
/* $Id: pflash_tgt.h,v 1.1.1.1 2006/09/14 01:59:09 root Exp $ */ |
|||
|
|||
/*
|
|||
* Copyright (c) 2000 Opsycon AB (www.opsycon.se) |
|||
* |
|||
* Redistribution and use in source and binary forms, with or without |
|||
* modification, are permitted provided that the following conditions |
|||
* are met: |
|||
* 1. Redistributions of source code must retain the above copyright |
|||
* notice, this list of conditions and the following disclaimer. |
|||
* 2. Redistributions in binary form must reproduce the above copyright |
|||
* notice, this list of conditions and the following disclaimer in the |
|||
* documentation and/or other materials provided with the distribution. |
|||
* 3. All advertising materials mentioning features or use of this software |
|||
* must display the following acknowledgement: |
|||
* This product includes software developed by |
|||
* Opsycon Open System Consulting AB, Sweden. |
|||
* 4. The name of the author may not be used to endorse or promote products |
|||
* derived from this software without specific prior written permission. |
|||
* |
|||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS |
|||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
|||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
|||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
|||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
|||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
|||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
|||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
|||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
|||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
|||
* SUCH DAMAGE. |
|||
* |
|||
*/ |
|||
|
|||
/*
|
|||
* Define a 'struct fl_map' init set for each flash area on the target. |
|||
*/ |
|||
|
|||
/* Note! Not requiered but prefered, sort in ascending address order */ |
|||
|
|||
/*
|
|||
* NOTE about 'width' codes. Usually the 'width' is the number of |
|||
* bytes that are accessed at the same time while the next value |
|||
* is the number of chips. Bytes per chips can be found by dividing |
|||
* 'width' with 'chips'. The code 9 for width is special to handle |
|||
* how the cp7000 addresses the AMD single chip when not mapped as |
|||
* boot device. |
|||
*/ |
|||
|
|||
#define TARGET_FLASH_DEVICES_16 \ |
|||
{ PHYS_TO_UNCACHED(BONITO_FLASH_BASE), 0x00100000, 1, 1, FL_BUS_8 }, \ |
|||
{ PHYS_TO_UNCACHED(0x1e000000), 0x02000000, 1, 1, FL_BUS_16 }, \ |
|||
{ 0x00000000, 0x00000000 } |
|||
|
|||
@ -0,0 +1,519 @@ |
|||
/*
|
|||
* Bonito Register Map |
|||
* Copyright (c) 1999 Algorithmics Ltd |
|||
* |
|||
* Algorithmics gives permission for anyone to use and modify this file |
|||
* without any obligation or license condition except that you retain |
|||
* this copyright message in any source redistribution in whole or part. |
|||
* |
|||
* Updated copies of this and other files can be found at |
|||
* ftp://ftp.algor.co.uk/pub/bonito/
|
|||
* |
|||
* Users of the Bonito controller are warmly recommended to contribute |
|||
* any useful changes back to Algorithmics (mail to |
|||
* bonito@algor.co.uk). |
|||
*/ |
|||
|
|||
/* Revision 1.48 autogenerated on 08/17/99 15:20:01 */ |
|||
|
|||
#ifndef _BONITO_H_ |
|||
|
|||
#ifdef __ASSEMBLER__ |
|||
//__ASSEMBLER__ is not defined
|
|||
/* offsets from base register */ |
|||
#define BONITO(x) (x) |
|||
|
|||
#else /* !__ASSEMBLER */ |
|||
extern char *heaptop; |
|||
|
|||
/* offsets from base pointer, this construct allows optimisation */ |
|||
/* static char * const _bonito = PA_TO_KVA1(BONITO_BASE); */ |
|||
/*#define BONITO(x) *(volatile unsigned long *)(PHYS_TO_UNCACHED(BONITO_REG_BASE)+(x))*/ |
|||
#define BONITO(x) *(volatile unsigned long *)(0xbfe00000+(x)) |
|||
#endif /* __ASSEMBLER__ */ |
|||
|
|||
#define RTC_INDEX_REG 0x70 |
|||
#define RTC_DATA_REG 0x71 |
|||
#define RTC_NVRAM_BASE 0x0e |
|||
|
|||
|
|||
#define GS3_UART0_BASE 0xbfe001e0 |
|||
#define GS3_UART1_BASE 0xbfe001e8 |
|||
#define GS3_UART_BASE GS3_UART0_BASE |
|||
#ifdef LS3_HT |
|||
#define COM1_BASE_ADDR 0xb80003f8 |
|||
#define COM2_BASE_ADDR 0xb80002f8 |
|||
#else |
|||
#define COM1_BASE_ADDR 0xbfd003f8 |
|||
#define COM2_BASE_ADDR 0xbfd002f8 |
|||
#endif |
|||
#ifndef COM3_BASE_ADDR |
|||
#define COM3_BASE_ADDR 0xbff003f8 |
|||
#endif |
|||
//#define NS16550HZ 1843200
|
|||
#define NS16550HZ 3686400 |
|||
/*********************************************************************/ |
|||
/*nvram define */ |
|||
/*********************************************************************/ |
|||
#ifdef NVRAM_IN_FLASH |
|||
# define NVRAM_SIZE 494 |
|||
# define NVRAM_SECSIZE 500 |
|||
# define NVRAM_OFFS 0x000ff000 |
|||
# define ETHER_OFFS 494 /* Ethernet address base */ |
|||
#else /* Use clock ram, 256 bytes only */ |
|||
# define NVRAM_SIZE 114 |
|||
# define NVRAM_SECSIZE NVRAM_SIZE /* Helper */ |
|||
# define NVRAM_OFFS 0 |
|||
# define ETHER_OFFS 108 /* Ethernet address base */ |
|||
#endif |
|||
|
|||
|
|||
|
|||
/*********************************************************************/ |
|||
/*PCI map */ |
|||
/*********************************************************************/ |
|||
|
|||
#ifdef X86_LIKE_SPACE |
|||
/* To make address spaces alike with x86 system, we put sdram
|
|||
* start address at 0 and pci devices' start address at 0x14000000 for |
|||
* both CPU address space & PCI memory address space. |
|||
* |
|||
* We have 3 64M window in CPU address space to access PCI memory,but the |
|||
* legacy PCI start pci memory from 0x10000000, so we can use the same address to access |
|||
* them from cpu memory space. But to access the 0xc0000 vga ram, we have to |
|||
* reserve the first window. Only the last two are used for pci devices. |
|||
* --zfx 060716 |
|||
*/ |
|||
/* make sdram appear at both cpu & pci memory space 0,
|
|||
* so for dma the physical address can be directly used |
|||
* as bus address. --zfx 060716 |
|||
*/ |
|||
|
|||
#define PCI_MEM_SPACE_PCI_BASE 0x40000000 |
|||
#define PCI_LOCAL_MEM_PCI_BASE 0x00000000 |
|||
#define PCI_LOCAL_MEM_ISA_BASE 0x80000000 |
|||
#define PCI_LOCAL_REG_PCI_BASE 0x90000000 |
|||
|
|||
#else |
|||
|
|||
#define PCI_MEM_SPACE_PCI_BASE 0x40000000 |
|||
#define PCI_LOCAL_MEM_PCI_BASE 0x80000000 |
|||
#define PCI_LOCAL_MEM_ISA_BASE 0x00800000 |
|||
#define PCI_LOCAL_REG_PCI_BASE 0x90000000 |
|||
|
|||
#endif |
|||
|
|||
#define PCI_IO_SPACE_BASE 0x00000000 |
|||
|
|||
#define BONITO_BOOT_BASE 0x1fc00000 |
|||
#define BONITO_BOOT_SIZE 0x00100000 |
|||
#define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1) |
|||
#define BONITO_FLASH_BASE 0x1fc00000 |
|||
#define BONITO_FLASH_SIZE 0x03000000 |
|||
#define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1) |
|||
#define BONITO_SOCKET_BASE 0x1f800000 |
|||
#define BONITO_SOCKET_SIZE 0x00400000 |
|||
#define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1) |
|||
#define BONITO_REG_BASE 0x1fe00000 |
|||
#define BONITO_REG_SIZE 0x00040000 |
|||
#define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1) |
|||
#define BONITO_DEV_BASE 0x1ff00000 |
|||
#define BONITO_DEV_SIZE 0x00100000 |
|||
#define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1) |
|||
#define BONITO_PCILO_BASE 0x40000000 |
|||
#define BONITO_PCILO_BASE_VA 0xc0000000 |
|||
#ifdef LS3_HT |
|||
#define BONITO_PCILO_SIZE 0x40000000 |
|||
#else |
|||
#define BONITO_PCILO_SIZE 0x0c000000 |
|||
#endif |
|||
#define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1) |
|||
#define BONITO_PCILO0_BASE 0x40000000 |
|||
#define BONITO_PCILO1_BASE 0x80000000 |
|||
#ifdef LS3_HT |
|||
//#define BONITO_PCILO2_BASE 0x1c000000
|
|||
//#define BONITO_PCIHI_BASE 0x18000000
|
|||
//#define BONITO_PCIHI_SIZE 0x02000000
|
|||
//#define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1)
|
|||
//#define BONITO_PCIIO_BASE 0x1fd00000
|
|||
//#define BONITO_PCIIO_BASE_VA 0xbfd00000
|
|||
#define BONITO_PCIIO_BASE 0x18000000 |
|||
#define BONITO_PCIIO_BASE_VA 0xb8000000 |
|||
#define BONITO_PCIIO_SIZE 0x02000000 |
|||
#else |
|||
#define BONITO_PCILO2_BASE 0x18000000 |
|||
#define BONITO_PCIHI_BASE 0x20000000 |
|||
#define BONITO_PCIHI_SIZE 0x20000000 |
|||
#define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1) |
|||
#define BONITO_PCIIO_BASE 0x1fd00000 |
|||
#define BONITO_PCIIO_BASE_VA 0xbfd00000 |
|||
#define BONITO_PCIIO_SIZE 0x00010000 |
|||
#endif |
|||
#define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1) |
|||
#define BONITO_PCICFG_BASE 0x1a000000 |
|||
#define BONITO_PCICFG_SIZE 0x00080000 |
|||
#define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1) |
|||
#define BONITO_PCICFG0_BASE 0x1a000000 |
|||
#define BONITO_PCICFG1_BASE 0x1b000000 |
|||
#define BONITO_PCICFG0_BASE_VA 0xba000000 |
|||
#define BONITO_PCICFG1_BASE_VA 0xbb000000 |
|||
|
|||
|
|||
/* Bonito Register Bases */ |
|||
|
|||
#define BONITO_PCICONFIGBASE 0x00 |
|||
#define BONITO_REGBASE 0x100 |
|||
|
|||
|
|||
/* PCI Configuration Registers */ |
|||
|
|||
#define BONITO_PCI_REG(x) BONITO(BONITO_PCICONFIGBASE + (x)) |
|||
#define BONITO_PCIDID BONITO_PCI_REG(0x00) |
|||
#define BONITO_PCICMD BONITO_PCI_REG(0x04) |
|||
#define BONITO_PCICLASS BONITO_PCI_REG(0x08) |
|||
#define BONITO_PCILTIMER BONITO_PCI_REG(0x0c) |
|||
#define BONITO_PCIBASE0 BONITO_PCI_REG(0x10) |
|||
#define BONITO_PCIBASE1 BONITO_PCI_REG(0x14) |
|||
#define BONITO_PCIBASE2 BONITO_PCI_REG(0x18) |
|||
#define BONITO_PCIEXPRBASE BONITO_PCI_REG(0x30) |
|||
#define BONITO_PCIINT BONITO_PCI_REG(0x3c) |
|||
|
|||
#define BONITO_PCICMD_PERR_CLR 0x80000000 |
|||
#define BONITO_PCICMD_SERR_CLR 0x40000000 |
|||
#define BONITO_PCICMD_MABORT_CLR 0x20000000 |
|||
#define BONITO_PCICMD_MTABORT_CLR 0x10000000 |
|||
#define BONITO_PCICMD_TABORT_CLR 0x08000000 |
|||
#define BONITO_PCICMD_MPERR_CLR 0x01000000 |
|||
#define BONITO_PCICMD_PERRRESPEN 0x00000040 |
|||
#define BONITO_PCICMD_ASTEPEN 0x00000080 |
|||
#define BONITO_PCICMD_SERREN 0x00000100 |
|||
#define BONITO_PCILTIMER_BUSLATENCY 0x0000ff00 |
|||
#define BONITO_PCILTIMER_BUSLATENCY_SHIFT 8 |
|||
|
|||
|
|||
|
|||
|
|||
/* 1. Bonito h/w Configuration */ |
|||
/* Power on register */ |
|||
|
|||
#define BONITO_BONPONCFG BONITO(BONITO_REGBASE + 0x00) |
|||
|
|||
#define BONITO_BONPONCFG_SYSCONTROLLERRD 0x00040000 |
|||
#define BONITO_BONPONCFG_ROMCS1SAMP 0x00020000 |
|||
#define BONITO_BONPONCFG_ROMCS0SAMP 0x00010000 |
|||
#define BONITO_BONPONCFG_CPUBIGEND 0x00004000 |
|||
#define BONITO_BONPONCFG_CPUPARITY 0x00002000 |
|||
#define BONITO_BONPONCFG_CPUTYPE 0x00000007 |
|||
#define BONITO_BONPONCFG_CPUTYPE_SHIFT 0 |
|||
#define BONITO_BONPONCFG_PCIRESET_OUT 0x00000008 |
|||
#define BONITO_BONPONCFG_IS_ARBITER 0x00000010 |
|||
#define BONITO_BONPONCFG_ROMBOOT 0x000000c0 |
|||
#define BONITO_BONPONCFG_ROMBOOT_SHIFT 6 |
|||
|
|||
#define BONITO_BONPONCFG_ROMBOOT_FLASH (0x0<<BONITO_BONPONCFG_ROMBOOT_SHIFT) |
|||
#define BONITO_BONPONCFG_ROMBOOT_SOCKET (0x1<<BONITO_BONPONCFG_ROMBOOT_SHIFT) |
|||
#define BONITO_BONPONCFG_ROMBOOT_SDRAM (0x2<<BONITO_BONPONCFG_ROMBOOT_SHIFT) |
|||
#define BONITO_BONPONCFG_ROMBOOT_CPURESET (0x3<<BONITO_BONPONCFG_ROMBOOT_SHIFT) |
|||
|
|||
#define BONITO_BONPONCFG_ROMCS0WIDTH 0x00000100 |
|||
#define BONITO_BONPONCFG_ROMCS1WIDTH 0x00000200 |
|||
#define BONITO_BONPONCFG_ROMCS0FAST 0x00000400 |
|||
#define BONITO_BONPONCFG_ROMCS1FAST 0x00000800 |
|||
#define BONITO_BONPONCFG_CONFIG_DIS 0x00000020 |
|||
|
|||
|
|||
/* Other Bonito configuration */ |
|||
|
|||
#define BONITO_BONGENCFG_OFFSET 0x4 |
|||
#define BONITO_BONGENCFG BONITO(BONITO_REGBASE + BONITO_BONGENCFG_OFFSET) |
|||
|
|||
#define BONITO_BONGENCFG_DEBUGMODE 0x00000001 |
|||
#define BONITO_BONGENCFG_SNOOPEN 0x00000002 |
|||
#define BONITO_BONGENCFG_CPUSELFRESET 0x00000004 |
|||
|
|||
#define BONITO_BONGENCFG_FORCE_IRQA 0x00000008 |
|||
#define BONITO_BONGENCFG_IRQA_ISOUT 0x00000010 |
|||
#define BONITO_BONGENCFG_IRQA_FROM_INT1 0x00000020 |
|||
#define BONITO_BONGENCFG_BYTESWAP 0x00000040 |
|||
|
|||
#define BONITO_BONGENCFG_PREFETCHEN 0x00000100 |
|||
#define BONITO_BONGENCFG_WBEHINDEN 0x00000200 |
|||
#define BONITO_BONGENCFG_CACHEALG 0x00000c00 |
|||
#define BONITO_BONGENCFG_CACHEALG_SHIFT 10 |
|||
#define BONITO_BONGENCFG_PCIQUEUE 0x00001000 |
|||
#define BONITO_BONGENCFG_CACHESTOP 0x00002000 |
|||
#define BONITO_BONGENCFG_MSTRBYTESWAP 0x00004000 |
|||
#define BONITO_BONGENCFG_BUSERREN 0x00008000 |
|||
#define BONITO_BONGENCFG_NORETRYTIMEOUT 0x00010000 |
|||
#define BONITO_BONGENCFG_SHORTCOPYTIMEOUT 0x00020000 |
|||
|
|||
/* 2. IO & IDE configuration */ |
|||
|
|||
#define BONITO_IODEVCFG BONITO(BONITO_REGBASE + 0x08) |
|||
|
|||
/* 3. IO & IDE configuration */ |
|||
|
|||
#define BONITO_SDCFG BONITO(BONITO_REGBASE + 0x0c) |
|||
|
|||
/* 4. PCI address map control */ |
|||
|
|||
#define BONITO_PCIMAP BONITO(BONITO_REGBASE + 0x10) |
|||
#define BONITO_PCIMEMBASECFG BONITO(BONITO_REGBASE + 0x14) |
|||
#define BONITO_PCIMAP_CFG BONITO(BONITO_REGBASE + 0x18) |
|||
|
|||
/* 5. ICU & GPIO regs */ |
|||
|
|||
/* GPIO Regs - r/w */ |
|||
|
|||
#define BONITO_GPIODATA_OFFSET 0x1c |
|||
#define BONITO_GPIODATA BONITO(BONITO_REGBASE + BONITO_GPIODATA_OFFSET) |
|||
#define BONITO_GPIOIE BONITO(BONITO_REGBASE + 0x20) |
|||
|
|||
/* ICU Configuration Regs - r/w */ |
|||
|
|||
#define BONITO_INTEDGE BONITO(BONITO_REGBASE + 0x24) |
|||
#define BONITO_INTSTEER BONITO(BONITO_REGBASE + 0x28) |
|||
#define BONITO_INTPOL BONITO(BONITO_REGBASE + 0x2c) |
|||
|
|||
/* ICU Enable Regs - IntEn & IntISR are r/o. */ |
|||
|
|||
#define BONITO_INTENSET BONITO(BONITO_REGBASE + 0x30) |
|||
#define BONITO_INTENCLR BONITO(BONITO_REGBASE + 0x34) |
|||
#define BONITO_INTEN BONITO(BONITO_REGBASE + 0x38) |
|||
#define BONITO_INTISR BONITO(BONITO_REGBASE + 0x3c) |
|||
|
|||
/* PCI mail boxes */ |
|||
|
|||
#define BONITO_PCIMAIL0_OFFSET 0x40 |
|||
#define BONITO_PCIMAIL1_OFFSET 0x44 |
|||
#define BONITO_PCIMAIL2_OFFSET 0x48 |
|||
#define BONITO_PCIMAIL3_OFFSET 0x4c |
|||
#define BONITO_PCIMAIL0 BONITO(BONITO_REGBASE + 0x40) |
|||
#define BONITO_PCIMAIL1 BONITO(BONITO_REGBASE + 0x44) |
|||
#define BONITO_PCIMAIL2 BONITO(BONITO_REGBASE + 0x48) |
|||
#define BONITO_PCIMAIL3 BONITO(BONITO_REGBASE + 0x4c) |
|||
|
|||
|
|||
/* 6. PCI cache */ |
|||
|
|||
#define BONITO_PCICACHECTRL BONITO(BONITO_REGBASE + 0x50) |
|||
#define BONITO_PCICACHETAG BONITO(BONITO_REGBASE + 0x54) |
|||
|
|||
#define BONITO_PCIBADADDR BONITO(BONITO_REGBASE + 0x58) |
|||
#define BONITO_PCIMSTAT BONITO(BONITO_REGBASE + 0x5c) |
|||
|
|||
|
|||
/*
|
|||
#define BONITO_PCIRDPOST BONITO(BONITO_REGBASE + 0x60) |
|||
#define BONITO_PCIDATA BONITO(BONITO_REGBASE + 0x64) |
|||
*/ |
|||
|
|||
/* 7. IDE DMA & Copier */ |
|||
|
|||
#define BONITO_CONFIGBASE 0x000 |
|||
#define BONITO_BONITOBASE 0x100 |
|||
#define BONITO_LDMABASE 0x200 |
|||
#define BONITO_COPBASE 0x300 |
|||
#define BONITO_REG_BLOCKMASK 0x300 |
|||
|
|||
#define BONITO_LDMACTRL BONITO(BONITO_LDMABASE + 0x0) |
|||
#define BONITO_LDMASTAT BONITO(BONITO_LDMABASE + 0x0) |
|||
#define BONITO_LDMAADDR BONITO(BONITO_LDMABASE + 0x4) |
|||
#define BONITO_LDMAGO BONITO(BONITO_LDMABASE + 0x8) |
|||
#define BONITO_LDMADATA BONITO(BONITO_LDMABASE + 0xc) |
|||
|
|||
#define BONITO_COPCTRL BONITO(BONITO_COPBASE + 0x0) |
|||
#define BONITO_COPSTAT BONITO(BONITO_COPBASE + 0x0) |
|||
#define BONITO_COPPADDR BONITO(BONITO_COPBASE + 0x4) |
|||
#define BONITO_COPDADDR BONITO(BONITO_COPBASE + 0x8) |
|||
#define BONITO_COPGO BONITO(BONITO_COPBASE + 0xc) |
|||
|
|||
|
|||
/* ###### Bit Definitions for individual Registers #### */ |
|||
|
|||
/* Gen DMA. */ |
|||
|
|||
#define BONITO_IDECOPDADDR_DMA_DADDR 0x0ffffffc |
|||
#define BONITO_IDECOPDADDR_DMA_DADDR_SHIFT 2 |
|||
#define BONITO_IDECOPPADDR_DMA_PADDR 0xfffffffc |
|||
#define BONITO_IDECOPPADDR_DMA_PADDR_SHIFT 2 |
|||
#define BONITO_IDECOPGO_DMA_SIZE 0x0000fffe |
|||
#define BONITO_IDECOPGO_DMA_SIZE_SHIFT 0 |
|||
#define BONITO_IDECOPGO_DMA_WRITE 0x00010000 |
|||
#define BONITO_IDECOPGO_DMAWCOUNT 0x000f0000 |
|||
#define BONITO_IDECOPGO_DMAWCOUNT_SHIFT 16 |
|||
|
|||
#define BONITO_IDECOPCTRL_DMA_STARTBIT 0x80000000 |
|||
#define BONITO_IDECOPCTRL_DMA_RSTBIT 0x40000000 |
|||
|
|||
/* DRAM - sdCfg */ |
|||
|
|||
#define BONITO_SDCFG_AROWBITS 0x00000003 |
|||
#define BONITO_SDCFG_AROWBITS_SHIFT 0 |
|||
#define BONITO_SDCFG_ACOLBITS 0x0000000c |
|||
#define BONITO_SDCFG_ACOLBITS_SHIFT 2 |
|||
#define BONITO_SDCFG_ABANKBIT 0x00000010 |
|||
#define BONITO_SDCFG_ASIDES 0x00000020 |
|||
#define BONITO_SDCFG_AABSENT 0x00000040 |
|||
#define BONITO_SDCFG_AWIDTH64 0x00000080 |
|||
|
|||
#define BONITO_SDCFG_BROWBITS 0x00000300 |
|||
#define BONITO_SDCFG_BROWBITS_SHIFT 8 |
|||
#define BONITO_SDCFG_BCOLBITS 0x00000c00 |
|||
#define BONITO_SDCFG_BCOLBITS_SHIFT 10 |
|||
#define BONITO_SDCFG_BBANKBIT 0x00001000 |
|||
#define BONITO_SDCFG_BSIDES 0x00002000 |
|||
#define BONITO_SDCFG_BABSENT 0x00004000 |
|||
#define BONITO_SDCFG_BWIDTH64 0x00008000 |
|||
|
|||
#define BONITO_SDCFG_EXTRDDATA 0x00010000 |
|||
#define BONITO_SDCFG_EXTRASCAS 0x00020000 |
|||
#define BONITO_SDCFG_EXTPRECH 0x00040000 |
|||
#define BONITO_SDCFG_EXTRASWIDTH 0x00180000 |
|||
#define BONITO_SDCFG_EXTRASWIDTH_SHIFT 19 |
|||
#define BONITO_SDCFG_DRAMRESET 0x00200000 |
|||
#define BONITO_SDCFG_DRAMEXTREGS 0x00400000 |
|||
#define BONITO_SDCFG_DRAMPARITY 0x00800000 |
|||
|
|||
/* PCI Cache - pciCacheCtrl */ |
|||
|
|||
#define BONITO_PCICACHECTRL_CACHECMD 0x00000007 |
|||
#define BONITO_PCICACHECTRL_CACHECMD_SHIFT 0 |
|||
#define BONITO_PCICACHECTRL_CACHECMDLINE 0x00000018 |
|||
#define BONITO_PCICACHECTRL_CACHECMDLINE_SHIFT 3 |
|||
#define BONITO_PCICACHECTRL_CMDEXEC 0x00000020 |
|||
|
|||
#define BONITO_IODEVCFG_BUFFBIT_CS0 0x00000001 |
|||
#define BONITO_IODEVCFG_SPEEDBIT_CS0 0x00000002 |
|||
#define BONITO_IODEVCFG_MOREABITS_CS0 0x00000004 |
|||
|
|||
#define BONITO_IODEVCFG_BUFFBIT_CS1 0x00000008 |
|||
#define BONITO_IODEVCFG_SPEEDBIT_CS1 0x00000010 |
|||
#define BONITO_IODEVCFG_MOREABITS_CS1 0x00000020 |
|||
|
|||
#define BONITO_IODEVCFG_BUFFBIT_CS2 0x00000040 |
|||
#define BONITO_IODEVCFG_SPEEDBIT_CS2 0x00000080 |
|||
#define BONITO_IODEVCFG_MOREABITS_CS2 0x00000100 |
|||
|
|||
#define BONITO_IODEVCFG_BUFFBIT_CS3 0x00000200 |
|||
#define BONITO_IODEVCFG_SPEEDBIT_CS3 0x00000400 |
|||
#define BONITO_IODEVCFG_MOREABITS_CS3 0x00000800 |
|||
|
|||
#define BONITO_IODEVCFG_BUFFBIT_IDE 0x00001000 |
|||
#define BONITO_IODEVCFG_SPEEDBIT_IDE 0x00002000 |
|||
#define BONITO_IODEVCFG_WORDSWAPBIT_IDE 0x00004000 |
|||
#define BONITO_IODEVCFG_MODEBIT_IDE 0x00008000 |
|||
#define BONITO_IODEVCFG_DMAON_IDE 0x001f0000 |
|||
#define BONITO_IODEVCFG_DMAON_IDE_SHIFT 16 |
|||
#define BONITO_IODEVCFG_DMAOFF_IDE 0x01e00000 |
|||
#define BONITO_IODEVCFG_DMAOFF_IDE_SHIFT 21 |
|||
#define BONITO_IODEVCFG_EPROMSPLIT 0x02000000 |
|||
|
|||
/* gpio */ |
|||
#define BONITO_GPIO_GPIOW 0x000003ff |
|||
#define BONITO_GPIO_GPIOW_SHIFT 0 |
|||
#define BONITO_GPIO_GPIOR 0x01ff0000 |
|||
#define BONITO_GPIO_GPIOR_SHIFT 16 |
|||
#define BONITO_GPIO_GPINR 0xfe000000 |
|||
#define BONITO_GPIO_GPINR_SHIFT 25 |
|||
#define BONITO_GPIO_IOW(N) (1<<(BONITO_GPIO_GPIOW_SHIFT+(N))) |
|||
#define BONITO_GPIO_IOR(N) (1<<(BONITO_GPIO_GPIOR_SHIFT+(N))) |
|||
#define BONITO_GPIO_INR(N) (1<<(BONITO_GPIO_GPINR_SHIFT+(N))) |
|||
|
|||
/* ICU */ |
|||
#define BONITO_ICU_MBOXES 0x0000000f |
|||
#define BONITO_ICU_MBOXES_SHIFT 0 |
|||
#define BONITO_ICU_DMARDY 0x00000010 |
|||
#define BONITO_ICU_DMAEMPTY 0x00000020 |
|||
#define BONITO_ICU_COPYRDY 0x00000040 |
|||
#define BONITO_ICU_COPYEMPTY 0x00000080 |
|||
#define BONITO_ICU_COPYERR 0x00000100 |
|||
#define BONITO_ICU_PCIIRQ 0x00000200 |
|||
#define BONITO_ICU_MASTERERR 0x00000400 |
|||
#define BONITO_ICU_SYSTEMERR 0x00000800 |
|||
#define BONITO_ICU_DRAMPERR 0x00001000 |
|||
#define BONITO_ICU_RETRYERR 0x00002000 |
|||
#define BONITO_ICU_GPIOS 0x01ff0000 |
|||
#define BONITO_ICU_GPIOS_SHIFT 16 |
|||
#define BONITO_ICU_GPINS 0x7e000000 |
|||
#define BONITO_ICU_GPINS_SHIFT 25 |
|||
#define BONITO_ICU_MBOX(N) (1<<(BONITO_ICU_MBOXES_SHIFT+(N))) |
|||
#define BONITO_ICU_GPIO(N) (1<<(BONITO_ICU_GPIOS_SHIFT+(N))) |
|||
#define BONITO_ICU_GPIN(N) (1<<(BONITO_ICU_GPINS_SHIFT+(N))) |
|||
|
|||
/* pcimap */ |
|||
|
|||
#define BONITO_PCIMAP_PCIMAP_LO0 0x0000003f |
|||
#define BONITO_PCIMAP_PCIMAP_LO0_SHIFT 0 |
|||
#define BONITO_PCIMAP_PCIMAP_LO1 0x00000fc0 |
|||
#define BONITO_PCIMAP_PCIMAP_LO1_SHIFT 6 |
|||
#define BONITO_PCIMAP_PCIMAP_LO2 0x0003f000 |
|||
#define BONITO_PCIMAP_PCIMAP_LO2_SHIFT 12 |
|||
#define BONITO_PCIMAP_PCIMAP_2 0x00040000 |
|||
#define BONITO_PCIMAP_WIN(WIN,ADDR) ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) |
|||
|
|||
#define BONITO_PCIMAP_WINSIZE (1<<26) |
|||
#define BONITO_PCIMAP_WINOFFSET(ADDR) ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1)) |
|||
#define BONITO_PCIMAP_WINBASE(ADDR) ((ADDR) << 26) |
|||
|
|||
/* pcimembaseCfg */ |
|||
|
|||
#define BONITO_PCIMEMBASECFG_MASK 0xf0000000 |
|||
#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK 0x0000001f |
|||
#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT 0 |
|||
#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS 0x000003e0 |
|||
#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS_SHIFT 5 |
|||
#define BONITO_PCIMEMBASECFG_MEMBASE0_CACHED 0x00000400 |
|||
#define BONITO_PCIMEMBASECFG_MEMBASE0_IO 0x00000800 |
|||
|
|||
#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK 0x0001f000 |
|||
#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK_SHIFT 12 |
|||
#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS 0x003e0000 |
|||
#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS_SHIFT 17 |
|||
#define BONITO_PCIMEMBASECFG_MEMBASE1_CACHED 0x00400000 |
|||
#define BONITO_PCIMEMBASECFG_MEMBASE1_IO 0x00800000 |
|||
|
|||
#define BONITO_PCIMEMBASECFG_ASHIFT 23 |
|||
#define BONITO_PCIMEMBASECFG_AMASK 0x007fffff |
|||
#define BONITO_PCIMEMBASECFGSIZE(WIN,SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) |
|||
#define BONITO_PCIMEMBASECFGBASE(WIN,BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) |
|||
|
|||
#define BONITO_PCIMEMBASECFG_SIZE(WIN,CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK) |
|||
|
|||
|
|||
#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) |
|||
#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) |
|||
#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) |
|||
|
|||
#define BONITO_PCITOPHYS(WIN,ADDR,CFG) ( \ |
|||
(((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG)))) | \ |
|||
(BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG)) \ |
|||
) |
|||
|
|||
/* PCICmd */ |
|||
|
|||
#define BONITO_PCICMD_MEMEN 0x00000002 |
|||
#define BONITO_PCICMD_MSTREN 0x00000004 |
|||
|
|||
/* DDR - sdCfg */ |
|||
#define BONITO_SDCFG_TRC_SHIFT 0 |
|||
#define BONITO_SDCFG_TRP_SHIFT 2 |
|||
#define BONITO_SDCFG_TWR_SHIFT 3 |
|||
#define BONITO_SDCFG_TCAS_SHIFT 4 |
|||
#define BONITO_SDCFG_TRAS_SHIFT 6 |
|||
#define BONITO_SDCFG_TRFC_SHIFT 7 |
|||
#define BONITO_SDCFG_TRCD_SHIFT 9 |
|||
#define BONITO_SDCFG_TREF_SHIFT 10 |
|||
#define BONITO_SDCFG_DDRTYPE_SHIFT 22 |
|||
#define BONITO_SDCFG_ISSEQ_SHIFT 26 |
|||
#define BONITO_SDCFG_DIMM_MOD_NUM_SHIFT 27 |
|||
|
|||
#define VTSB_BUS 0 |
|||
#ifdef PCI_IDSEL_VIA686B |
|||
#define VTSB_DEV PCI_IDSEL_VIA686B |
|||
#else |
|||
#define VTSB_DEV 17 |
|||
#endif |
|||
#define VTSB_ISA_FUNC 0 |
|||
#define VTSB_IDE_FUNC 1 |
|||
#endif /* _BONITO_H_ */ |
|||
@ -0,0 +1,571 @@ |
|||
/*
|
|||
* cs5536.h |
|||
* |
|||
* The include file of cs5536 sourthbridge define which is used in the pmon only. |
|||
* you can modify it or change it, please set the modify time and steps. |
|||
* |
|||
* Author : jlliu <liujl@lemote.com> |
|||
* Data : 07-6-27 |
|||
*/ |
|||
|
|||
#ifndef _CS5536_H |
|||
#define _CS5536_H |
|||
|
|||
/*************************************************************************/ |
|||
|
|||
/*
|
|||
* basic define |
|||
*/ |
|||
#define PCI_IO_BASE 0x1fd00000 //( < 0x1fe00000)
|
|||
#define PCI_IO_BASE_VA 0xbfd00000 |
|||
#define PCI_MEM_BASE 0x10000000 //( < 0x1c000000 )
|
|||
#define PCI_MEM_BASE_VA 0xb0000000 |
|||
|
|||
/*
|
|||
* MSR module base |
|||
*/ |
|||
#define GET_MSR_ADDR(x) (((x<<9)&0xff100000)|(x&0x3fff)) |
|||
#define CS5536_SB_MSR_BASE (0x00000000) |
|||
#define CS5536_GLIU_MSR_BASE (0x10000000) |
|||
#define CS5536_ILLEGAL_MSR_BASE (0x20000000) |
|||
#define CS5536_USB_MSR_BASE (0x40000000) |
|||
#define CS5536_IDE_MSR_BASE (0x60000000) |
|||
#define CS5536_DIVIL_MSR_BASE (0x80000000) |
|||
#define CS5536_ACC_MSR_BASE (0xa0000000) |
|||
#define CS5536_UNUSED_MSR_BASE (0xc0000000) |
|||
#define CS5536_GLCP_MSR_BASE (0xe0000000) |
|||
|
|||
#define SB_MSR_REG(offset) (CS5536_SB_MSR_BASE | offset) |
|||
#define GLIU_MSR_REG(offset) (CS5536_GLIU_MSR_BASE | offset) |
|||
#define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE| offset) |
|||
#define USB_MSR_REG(offset) (CS5536_USB_MSR_BASE | offset) |
|||
#define IDE_MSR_REG(offset) (CS5536_IDE_MSR_BASE | offset) |
|||
#define DIVIL_MSR_REG(offset) (CS5536_DIVIL_MSR_BASE | offset) |
|||
#define ACC_MSR_REG(offset) (CS5536_ACC_MSR_BASE | offset) |
|||
#define UNUSED_MSR_REG(offset) (CS5536_UNUSED_MSR_BASE | offset) |
|||
#define GLCP_MSR_REG(offset) (CS5536_GLCP_MSR_BASE | offset) |
|||
/*
|
|||
* PCI MSR ACCESS |
|||
*/ |
|||
#define PCI_MSR_CTRL 0xF0 |
|||
#define PCI_MSR_ADDR 0xF4 |
|||
#define PCI_MSR_DATA_LO 0xF8 |
|||
#define PCI_MSR_DATA_HI 0xFC |
|||
|
|||
/******************************* MSR *****************************************/ |
|||
|
|||
/*
|
|||
* GLIU STANDARD MSR |
|||
*/ |
|||
#define GLIU_CAP 0x00 |
|||
#define GLIU_CONFIG 0x01 |
|||
#define GLIU_SMI 0x02 |
|||
#define GLIU_ERROR 0x03 |
|||
#define GLIU_PM 0x04 |
|||
#define GLIU_DIAG 0x05 |
|||
|
|||
/*
|
|||
* GLIU SPEC. MSR |
|||
*/ |
|||
#define GLIU_P2D_BM0 0x20 |
|||
#define GLIU_P2D_BM1 0x21 |
|||
#define GLIU_P2D_BM2 0x22 |
|||
#define GLIU_P2D_BMK0 0x23 |
|||
#define GLIU_P2D_BMK1 0x24 |
|||
#define GLIU_P2D_BM3 0x25 |
|||
#define GLIU_P2D_BM4 0x26 |
|||
#define GLIU_COH 0x80 |
|||
#define GLIU_PAE 0x81 |
|||
#define GLIU_ARB 0x82 |
|||
#define GLIU_ASMI 0x83 |
|||
#define GLIU_AERR 0x84 |
|||
#define GLIU_DEBUG 0x85 |
|||
#define GLIU_PHY_CAP 0x86 |
|||
#define GLIU_NOUT_RESP 0x87 |
|||
#define GLIU_NOUT_WDATA 0x88 |
|||
#define GLIU_WHOAMI 0x8B |
|||
#define GLIU_SLV_DIS 0x8C |
|||
#define GLIU_IOD_BM0 0xE0 |
|||
#define GLIU_IOD_BM1 0xE1 |
|||
#define GLIU_IOD_BM2 0xE2 |
|||
#define GLIU_IOD_BM3 0xE3 |
|||
#define GLIU_IOD_BM4 0xE4 |
|||
#define GLIU_IOD_BM5 0xE5 |
|||
#define GLIU_IOD_BM6 0xE6 |
|||
#define GLIU_IOD_BM7 0xE7 |
|||
#define GLIU_IOD_BM8 0xE8 |
|||
#define GLIU_IOD_BM9 0xE9 |
|||
#define GLIU_IOD_SC0 0xEA |
|||
#define GLIU_IOD_SC1 0xEB |
|||
#define GLIU_IOD_SC2 0xEC |
|||
#define GLIU_IOD_SC3 0xED |
|||
#define GLIU_IOD_SC4 0xEE |
|||
#define GLIU_IOD_SC5 0xEF |
|||
#define GLIU_IOD_SC6 0xF0 |
|||
#define GLIU_IOD_SC7 0xF1 |
|||
|
|||
/*
|
|||
* SB STANDARD |
|||
*/ |
|||
#define SB_CAP 0x00 |
|||
#define SB_CONFIG 0x01 |
|||
#define SB_SMI 0x02 |
|||
#define SB_ERROR 0x03 |
|||
#define SB_MAR_ERR_EN 0x00000001 |
|||
#define SB_TAR_ERR_EN 0x00000002 |
|||
#define SB_RSVD_BIT1 0x00000004 |
|||
#define SB_EXCEP_ERR_EN 0x00000008 |
|||
#define SB_SYSE_ERR_EN 0x00000010 |
|||
#define SB_PARE_ERR_EN 0x00000020 |
|||
#define SB_TAS_ERR_EN 0x00000040 |
|||
#define SB_MAR_ERR_FLAG 0x00010000 |
|||
#define SB_TAR_ERR_FLAG 0x00020000 |
|||
#define SB_RSVD_BIT2 0x00040000 |
|||
#define SB_EXCEP_ERR_FLAG 0x00080000 |
|||
#define SB_SYSE_ERR_FLAG 0x00100000 |
|||
#define SB_PARE_ERR_FLAG 0x00200000 |
|||
#define SB_TAS_ERR_FLAG 0x00400000 |
|||
#define SB_PM 0x04 |
|||
#define SB_DIAG 0x05 |
|||
|
|||
/*
|
|||
* SB SPEC. |
|||
*/ |
|||
#define SB_CTRL 0x10 |
|||
#define SB_R0 0x20 |
|||
#define SB_R1 0x21 |
|||
#define SB_R2 0x22 |
|||
#define SB_R3 0x23 |
|||
#define SB_R4 0x24 |
|||
#define SB_R5 0x25 |
|||
#define SB_R6 0x26 |
|||
#define SB_R7 0x27 |
|||
#define SB_R8 0x28 |
|||
#define SB_R9 0x29 |
|||
#define SB_R10 0x2A |
|||
#define SB_R11 0x2B |
|||
#define SB_R12 0x2C |
|||
#define SB_R13 0x2D |
|||
#define SB_R14 0x2E |
|||
#define SB_R15 0x2F |
|||
|
|||
/*
|
|||
* GLCP STANDARD |
|||
*/ |
|||
#define GLCP_CAP 0x00 |
|||
#define GLCP_CONFIG 0x01 |
|||
#define GLCP_SMI 0x02 |
|||
#define GLCP_ERROR 0x03 |
|||
#define GLCP_PM 0x04 |
|||
#define GLCP_DIAG 0x05 |
|||
|
|||
/*
|
|||
* GLCP SPEC. |
|||
*/ |
|||
#define GLCP_CLK_DIS_DELAY 0x08 |
|||
#define GLCP_PM_CLK_DISABLE 0x09 |
|||
#define GLCP_GLB_PM 0x0B |
|||
#define GLCP_DBG_OUT 0x0C |
|||
#define GLCP_RSVD1 0x0D |
|||
#define GLCP_SOFT_COM 0x0E |
|||
#define SOFT_BAR_SMB_FLAG 0x00000001 |
|||
#define SOFT_BAR_GPIO_FLAG 0x00000002 |
|||
#define SOFT_BAR_MFGPT_FLAG 0x00000004 |
|||
#define SOFT_BAR_IRQ_FLAG 0x00000008 |
|||
#define SOFT_BAR_PMS_FLAG 0x00000010 |
|||
#define SOFT_BAR_ACPI_FLAG 0x00000020 |
|||
#define SOFT_BAR_FLSH0_FLAG 0x00000040 |
|||
#define SOFT_BAR_FLSH1_FLAG 0x00000080 |
|||
#define SOFT_BAR_FLSH2_FLAG 0x00000100 |
|||
#define SOFT_BAR_FLSH3_FLAG 0x00000200 |
|||
#define SOFT_BAR_IDE_FLAG 0x00000400 |
|||
#define SOFT_BAR_ACC_FLAG 0x00000800 |
|||
#define SOFT_BAR_OHCI_FLAG 0x00001000 |
|||
#define SOFT_BAR_EHCI_FLAG 0x00002000 |
|||
#define SOFT_BAR_UDC_FLAG 0x00004000 |
|||
#define SOFT_BAR_OTG_FLAG 0x00008000 |
|||
#define GLCP_RSVD2 0x0F |
|||
#define GLCP_CLK_OFF 0x10 |
|||
#define GLCP_CLK_ACTIVE 0x11 |
|||
#define GLCP_CLK_DISABLE 0x12 |
|||
#define GLCP_CLK4ACK 0x13 |
|||
#define GLCP_SYS_RST 0x14 |
|||
#define GLCP_RSVD3 0x15 |
|||
#define GLCP_DBG_CLK_CTRL 0x16 |
|||
#define GLCP_CHIP_REV_ID 0x17 |
|||
|
|||
/*
|
|||
* DIVIL STANDARD |
|||
*/ |
|||
#define DIVIL_CAP 0x00 |
|||
#define DIVIL_CONFIG 0x01 |
|||
#define DIVIL_SMI 0x02 |
|||
#define DIVIL_ERROR 0x03 |
|||
#define DIVIL_PM 0x04 |
|||
#define DIVIL_DIAG 0x05 |
|||
|
|||
/*
|
|||
* DIVIL SPEC. |
|||
*/ |
|||
#define DIVIL_LBAR_IRQ 0x08 |
|||
#define DIVIL_LBAR_KEL 0x09 |
|||
#define DIVIL_LBAR_SMB 0x0B |
|||
#define DIVIL_LBAR_GPIO 0x0C |
|||
#define DIVIL_LBAR_MFGPT 0x0D |
|||
#define DIVIL_LBAR_ACPI 0x0E |
|||
#define DIVIL_LBAR_PMS 0x0F |
|||
#define DIVIL_LBAR_FLSH0 0x10 |
|||
#define DIVIL_LBAR_FLSH1 0x11 |
|||
#define DIVIL_LBAR_FLSH2 0x12 |
|||
#define DIVIL_LBAR_FLSH3 0x13 |
|||
#define DIVIL_LEG_IO 0x14 |
|||
#define DIVIL_BALL_OPTS 0x15 |
|||
#define DIVIL_SOFT_IRQ 0x16 |
|||
#define DIVIL_SOFT_RESET 0x17 |
|||
// NOR FLASH
|
|||
#define NORF_CTRL 0x18 |
|||
#define NORF_T01 0x19 |
|||
#define NORF_T23 0x1A |
|||
// NAND FLASH
|
|||
#define NANDF_DATA 0x1B |
|||
#define NANDF_CTRL 0x1C |
|||
#define NANDF_RSVD 0x1D |
|||
// KEL Keyboard Emulation Logic
|
|||
#define KEL_CTRL 0x1F |
|||
// PIC
|
|||
#define PIC_YZSEL_LOW 0x20 |
|||
#define PIC_YSEL_HIGH 0x21 |
|||
#define PIC_ZSEL_LOW 0x22 |
|||
#define PIC_ZSEL_HIGH 0x23 |
|||
#define PIC_IRQM_PRIM 0x24 |
|||
#define PIC_IRQM_LPC 0x25 |
|||
#define PIC_XIRR_STS_LOW 0x26 |
|||
#define PIC_XIRR_STS_HIGH 0x27 |
|||
#define PCI_SHDW 0x34 |
|||
// MFGPT
|
|||
#define MFGPT_IRQ 0x28 |
|||
#define MFGPT_NR 0x29 |
|||
#define MFGPT_RSVD 0x2A |
|||
#define MFGPT_SETUP 0x2B |
|||
// FLOPPY
|
|||
#define FLPY_3F2_SHDW 0x30 |
|||
#define FLPY_3F7_SHDW 0x31 |
|||
#define FLPY_372_SHDW 0x32 |
|||
#define FLPY_377_SHDW 0x33 |
|||
// PIT
|
|||
#define PIT_SHDW 0x36 |
|||
#define PIT_CNTRL 0x37 |
|||
// UART
|
|||
#define UART1_MOD 0x38 |
|||
#define UART1_DONG 0x39 |
|||
#define UART1_CONF 0x3A |
|||
#define UART1_RSVD 0x3B |
|||
#define UART2_MOD 0x3C |
|||
#define UART2_DONG 0x3D |
|||
#define UART2_CONF 0x3E |
|||
#define UART2_RSVD 0x3F |
|||
// DMA
|
|||
#define DIVIL_AC_DMA 0x1E |
|||
#define DMA_MAP 0x40 |
|||
#define DMA_SHDW_CH0 0x41 |
|||
#define DMA_SHDW_CH1 0x42 |
|||
#define DMA_SHDW_CH2 0x43 |
|||
#define DMA_SHDW_CH3 0x44 |
|||
#define DMA_SHDW_CH4 0x45 |
|||
#define DMA_SHDW_CH5 0x46 |
|||
#define DMA_SHDW_CH6 0x47 |
|||
#define DMA_SHDW_CH7 0x48 |
|||
#define DMA_MSK_SHDW 0x49 |
|||
// LPC
|
|||
#define LPC_EADDR 0x4C |
|||
#define LPC_ESTAT 0x4D |
|||
#define LPC_SIRQ 0x4E |
|||
#define LPC_RSVD 0x4F |
|||
// PMC
|
|||
#define PMC_LTMR 0x50 |
|||
#define PMC_RSVD 0x51 |
|||
// RTC
|
|||
#define RTC_RAM_LOCK 0x54 |
|||
#define RTC_DOMA_OFFSET 0x55 |
|||
#define RTC_MONA_OFFSET 0x56 |
|||
#define RTC_CEN_OFFSET 0x57 |
|||
|
|||
/*
|
|||
* IDE STANDARD |
|||
*/ |
|||
#define IDE_CAP 0x00 |
|||
#define IDE_CONFIG 0x01 |
|||
#define IDE_SMI 0x02 |
|||
#define IDE_ERROR 0x03 |
|||
#define IDE_PM 0x04 |
|||
#define IDE_DIAG 0x05 |
|||
|
|||
/*
|
|||
* ACC STANDARD |
|||
*/ |
|||
#define ACC_CAP 0x00 |
|||
#define ACC_CONFIG 0x01 |
|||
#define ACC_SMI 0x02 |
|||
#define ACC_ERROR 0x03 |
|||
#define ACC_PM 0x04 |
|||
#define ACC_DIAG 0x05 |
|||
|
|||
/*
|
|||
* IDE SPEC. |
|||
*/ |
|||
#define IDE_IO_BAR 0x08 |
|||
#define IDE_CFG 0x10 |
|||
#define IDE_DTC 0x12 |
|||
#define IDE_CAST 0x13 |
|||
#define IDE_ETC 0x14 |
|||
#define IDE_INTERNAL_PM 0x15 |
|||
|
|||
/*
|
|||
* USB STANDARD |
|||
*/ |
|||
#define USB_CAP 0x00 |
|||
#define USB_CONFIG 0x01 |
|||
#define USB_SMI 0x02 |
|||
#define USB_ERROR 0x03 |
|||
#define USB_PM 0x04 |
|||
#define USB_DIAG 0x05 |
|||
|
|||
/*
|
|||
* USB SPEC. |
|||
*/ |
|||
#define USB_OHCI 0x08 |
|||
#define USB_EHCI 0x09 |
|||
#define USB_UDC 0x0A |
|||
#define USB_OTG 0x0B |
|||
|
|||
/********************************** NATIVE ************************************/ |
|||
|
|||
#define CS5536_IDE_RANGE 0xfffffff0 |
|||
#define CS5536_IDE_LENGTH 0x10 |
|||
|
|||
/*
|
|||
* IDE NATIVE : I/O SPACE |
|||
* REG : 8BITS WIDTH |
|||
* BASE : DETERMINED BY MSR |
|||
*/ |
|||
#define IDE_BM_CMD 0x00 |
|||
#define IDE_BM_STS 0x02 |
|||
#define IDE_BM_PRD 0x04 |
|||
|
|||
/*
|
|||
* ACC |
|||
*/ |
|||
#define CS5536_ACC_RANGE 0xffffff80 |
|||
#define CS5536_ACC_LENGTH 0x80 |
|||
|
|||
/*
|
|||
* USB NATIVE : MEM SPACE |
|||
* REG : 32BITS WIDTH |
|||
*/ |
|||
#define CS5536_OHCI_RANGE 0xfffff000 |
|||
#define CS5536_OHCI_LENGTH 0x1000 |
|||
|
|||
#define CS5536_EHCI_RANGE 0xfffff000 |
|||
#define CS5536_EHCI_LENGTH 0x1000 |
|||
|
|||
#define CS5536_UDC_RANGE 0xffffe000 |
|||
#define CS5536_UDC_LENGTH 0x2000 |
|||
|
|||
#define CS5536_OTG_RANGE 0xfffff000 |
|||
#define CS5536_OTG_LENGTH 0x1000 |
|||
|
|||
// OHCI NATIVE
|
|||
#define OHCI_REVISION 0x00 |
|||
#define OHCI_CONTROL 0x04 |
|||
#define OHCI_COMMAND_STATUS 0x08 |
|||
#define OHCI_INT_STATUS 0x0C |
|||
#define OHCI_INT_ENABLE 0x10 |
|||
#define OHCI_INT_DISABLE 0x14 |
|||
#define OHCI_HCCA 0x18 |
|||
#define OHCI_PERI_CUR_ED 0x1C |
|||
#define OHCI_CTRL_HEAD_ED 0x20 |
|||
#define OHCI_CTRL_CUR_ED 0x24 |
|||
#define OHCI_BULK_HEAD_ED 0x28 |
|||
#define OHCI_BULK_CUR_ED 0x2C |
|||
#define OHCI_DONE_HEAD 0x30 |
|||
#define OHCI_FM_INTERVAL 0x34 |
|||
#define OHCI_FM_REMAINING 0x38 |
|||
#define OHCI_FM_NUMBER 0x3C |
|||
#define OHCI_PERI_START 0x40 |
|||
#define OHCI_LS_THRESHOLD 0x44 |
|||
#define OHCI_RH_DESCRIPTORA 0x48 |
|||
#define OHCI_RH_DESCRIPTORB 0x4C |
|||
#define OHCI_RH_STATUS 0x50 |
|||
#define OHCI_RH_PORT_STATUS1 0x54 |
|||
#define OHCI_RH_PORT_STATUS2 0x58 |
|||
#define OHCI_RH_PORT_STATUS3 0x5C |
|||
#define OHCI_RH_PORT_STATUS4 0x60 |
|||
|
|||
/*
|
|||
* DIVIL NATIVE |
|||
*/ |
|||
#define CS5536_IRQ_RANGE 0xffffffe0 // USERD FOR PCI PROBE
|
|||
#define CS5536_IRQ_LENGTH 0x20 // THE REGS ACTUAL LENGTH
|
|||
|
|||
#define CS5536_SMB_RANGE 0xfffffff8 |
|||
#define CS5536_SMB_LENGTH 0x08 |
|||
|
|||
#define CS5536_GPIO_RANGE 0xffffff00 |
|||
#define CS5536_GPIO_LENGTH 0x100 |
|||
|
|||
#define CS5536_MFGPT_RANGE 0xffffffc0 |
|||
#define CS5536_MFGPT_LENGTH 0x40 |
|||
|
|||
#define CS5536_ACPI_RANGE 0xffffffe0 |
|||
#define CS5536_ACPI_LENGTH 0x20 |
|||
|
|||
#define CS5536_PMS_RANGE 0xffffff80 |
|||
#define CS5536_PMS_LENGTH 0x80 |
|||
|
|||
|
|||
// KEL : MEM SPACE; REG :32BITS WIDTH
|
|||
#define KEL_HCE_CTRL 0x100 |
|||
#define KEL_HCE_IN 0x104 |
|||
#define KEL_HCE_OUT 0x108 |
|||
#define KEL_HCE_STS 0x10C |
|||
#define KEL_PORTA 0x92 //8bits
|
|||
// PIC : I/O SPACE; REG : 8BITS
|
|||
#define PIC_ICW1_MASTER 0x20 |
|||
#define PIC_ICW1_SLAVE 0xA0 |
|||
#define PIC_ICW2_MASTER 0x21 |
|||
#define PIC_ICW2_SLAVE 0xA1 |
|||
#define PIC_ICW3_MASTER 0x21 |
|||
#define PIC_ICW3_SLAVE 0xA1 |
|||
#define PIC_ICW4_MASTER 0x21 |
|||
#define PIC_ICW4_SLAVE 0xA1 |
|||
#define PIC_OCW1_MASTER 0x21 |
|||
#define PIC_OCW1_SLAVE 0xA1 |
|||
#define PIC_OCW2_MASTER 0x20 |
|||
#define PIC_OCW2_SLAVE 0xA0 |
|||
#define PIC_OCW3_MASTER 0x20 |
|||
#define PIC_OCW3_SLAVE 0xA0 |
|||
#define PIC_IRR_MASTER 0x20 |
|||
#define PIC_IRR_SLAVE 0xA0 |
|||
#define PIC_ISR_MASTER 0x20 |
|||
#define PIC_ISR_SLAVE 0xA0 |
|||
#define PIC_INT_SEL1 0x4D0 |
|||
#define PIC_INT_SEL2 0x4D1 |
|||
// GPIO : I/O SPACE; REG : 32BITS
|
|||
#define GPIOL_OUT_VAL 0x00 |
|||
#define GPIOL_OUT_EN 0x04 |
|||
#define GPIOL_OUT_OD_EN 0x08 |
|||
#define GPIOL_OUT_INVRT_EN 0x0c |
|||
#define GPIOL_OUT_AUX1_SEL 0x10 |
|||
#define GPIOL_OUT_AUX2_SEL 0x14 |
|||
#define GPIOL_PU_EN 0x18 |
|||
#define GPIOL_PD_EN 0x1c |
|||
#define GPIOL_IN_EN 0x20 |
|||
#define GPIOL_IN_INVRT_EN 0x24 |
|||
#define GPIOL_IN_FLTR_EN 0x28 |
|||
#define GPIOL_IN_EVNTCNT_EN 0x2c |
|||
#define GPIOL_IN_READBACK 0x30 |
|||
#define GPIOL_IN_AUX1_SEL 0x34 |
|||
#define GPIOL_EVNT_EN 0x38 |
|||
#define GPIOL_LOCK_EN 0x3c |
|||
#define GPIOL_IN_POSEDGE_EN 0x40 |
|||
#define GPIOL_IN_NEGEDGE_EN 0x44 |
|||
#define GPIOL_IN_POSEDGE_STS 0x48 |
|||
#define GPIOL_IN_NEGEDGE_STS 0x4c |
|||
#define GPIOH_OUT_VAL 0x80 |
|||
#define GPIOH_OUT_EN 0x84 |
|||
#define GPIOH_OUT_OD_EN 0x88 |
|||
#define GPIOH_OUT_INVRT_EN 0x8c |
|||
#define GPIOH_OUT_AUX1_SEL 0x90 |
|||
#define GPIOH_OUT_AUX2_SEL 0x94 |
|||
#define GPIOH_PU_EN 0x98 |
|||
#define GPIOH_PD_EN 0x9c |
|||
#define GPIOH_IN_EN 0xA0 |
|||
#define GPIOH_IN_INVRT_EN 0xA4 |
|||
#define GPIOH_IN_FLTR_EN 0xA8 |
|||
#define GPIOH_IN_EVNTCNT_EN 0xAc |
|||
#define GPIOH_IN_READBACK 0xB0 |
|||
#define GPIOH_IN_AUX1_SEL 0xB4 |
|||
#define GPIOH_EVNT_EN 0xB8 |
|||
#define GPIOH_LOCK_EN 0xBc |
|||
#define GPIOH_IN_POSEDGE_EN 0xC0 |
|||
#define GPIOH_IN_NEGEDGE_EN 0xC4 |
|||
#define GPIOH_IN_POSEDGE_STS 0xC8 |
|||
#define GPIOH_IN_NEGEDGE_STS 0xCC |
|||
// SMB : I/O SPACE, REG : 8BITS WIDTH
|
|||
#define SMB_SDA 0x00 |
|||
#define SMB_STS 0x01 |
|||
#define SMB_STS_SLVSTP (1 << 7) |
|||
#define SMB_STS_SDAST (1 << 6) |
|||
#define SMB_STS_BER (1 << 5) |
|||
#define SMB_STS_NEGACK (1 << 4) |
|||
#define SMB_STS_STASTR (1 << 3) |
|||
#define SMB_STS_NMATCH (1 << 2) |
|||
#define SMB_STS_MASTER (1 << 1) |
|||
#define SMB_STS_XMIT (1 << 0) |
|||
#define SMB_CTRL_STS 0x02 |
|||
#define SMB_CSTS_TGSTL (1 << 5) |
|||
#define SMB_CSTS_TSDA (1 << 4) |
|||
#define SMB_CSTS_GCMTCH (1 << 3) |
|||
#define SMB_CSTS_MATCH (1 << 2) |
|||
#define SMB_CSTS_BB (1 << 1) |
|||
#define SMB_CSTS_BUSY (1 << 0) |
|||
#define SMB_CTRL1 0x03 |
|||
#define SMB_CTRL1_STASTRE (1 << 7) |
|||
#define SMB_CTRL1_NMINTE (1 << 6) |
|||
#define SMB_CTRL1_GCMEN (1 << 5) |
|||
#define SMB_CTRL1_ACK (1 << 4) |
|||
#define SMB_CTRL1_RSVD (1 << 3) |
|||
#define SMB_CTRL1_INTEN (1 << 2) |
|||
#define SMB_CTRL1_STOP (1 << 1) |
|||
#define SMB_CTRL1_START (1 << 0) |
|||
#define SMB_ADDR 0x04 |
|||
#define SMB_ADDR_SAEN (1 << 7) |
|||
#define SMB_CTRL2 0x05 |
|||
#define SMB_ENABLE (1 << 0) |
|||
#define SMB_CTRL3 0x06 |
|||
|
|||
/*********************************** LEGACY I/O *******************************/ |
|||
|
|||
/*
|
|||
* LEGACY I/O SPACE BASE |
|||
*/ |
|||
#define CS5536_LEGACY_BASE_ADDR (PCI_IO_BASE_VA | 0x0000) |
|||
|
|||
/*
|
|||
* IDE LEGACY REG : legacy IO address is 0x170~0x177 and 0x376 (0x1f0~0x1f7 and 0x3f6) |
|||
* all registers are 16bits except the IDE_LEGACY_DATA reg |
|||
* some registers are read only and the |
|||
*/ |
|||
#define PRI_IDE_LEGACY_REG(offset) (CS5536_LEGACY_BASE_ADDR | 0x1f0 | offset) |
|||
#define SEC_IDE_LEGACY_REG(offset) (CS5536_LEGACY_BASE_ADDR | 0x170 | offset) |
|||
|
|||
#define IDE_LEGACY_DATA 0x00 // RW
|
|||
#define IDE_LEGACY_ERROR 0x01 // RO
|
|||
#define IDE_LEGACY_FEATURE 0x01 // WO
|
|||
#define IDE_LEGACY_SECTOR_COUNT 0x02 // RW
|
|||
#define IDE_LEGACY_SECTOR_NUM 0x03 // RW
|
|||
#define IDE_LEGACY_CYL_LO 0x04 // RW
|
|||
#define IDE_LEGACY_CYL_HI 0x05 // RW
|
|||
#define IDE_LEGACY_HEAD 0x06 // RW
|
|||
#define IDE_LEGACY_HEAD_DRV (1 << 4) |
|||
#define IDE_LEGACY_HEAD_LBA (1 << 6) |
|||
#define IDE_LEGACY_HEAD_IBM (1 << 7 | 1 << 5) |
|||
#define IDE_LEGACY_STATUS 0x07 // RO
|
|||
#define IDE_LEGACY_STATUS_ERR (1 << 0) |
|||
#define IDE_LEGACY_STATUS_IDX (1 << 1) |
|||
#define IDE_LEGACY_STATUS_CORR (1 << 2) |
|||
#define IDE_LEGACY_STATUS_DRQ (1 << 3) |
|||
#define IDE_LEGACY_STATUS_DSC (1 << 4) |
|||
#define IDE_LEGACY_STATUS_DWF (1 << 5) |
|||
#define IDE_LEGACY_STATUS_DRDY (1 << 6) |
|||
#define IDE_LEGACY_STATUS_BUSY (1 << 7) |
|||
#define IDE_LEGACY_COMMAND 0x07 // WO
|
|||
#define IDE_LEGACY_ASTATUS 0x206 // RO
|
|||
#define IDE_LEGACY_CTRL 0x206 // WO
|
|||
#define IDE_LEGACY_CTRL_IDS 0x02 |
|||
#define IDE_LEGACY_CTRL_RST 0x04 |
|||
#define IDE_LEGACY_CTRL_4BIT 0x08 |
|||
|
|||
/**********************************************************************************/ |
|||
|
|||
#endif /* _CS5536_H */ |
|||
@ -0,0 +1,138 @@ |
|||
/*
|
|||
* cs5536_vsm.h |
|||
* the definition file of cs5536 Virtual Support Module(VSM). |
|||
* pci configuration space can be accessed through the VSM, so |
|||
* there is no need the MSR read/write now, except the spec. MSR |
|||
* registers which are not implemented yet. |
|||
* |
|||
* Author : jlliu <liujl@lemote.com> |
|||
* Date : 07-07-04 |
|||
* |
|||
*/ |
|||
|
|||
#ifndef _CS5536_PCI_H |
|||
#define _CS5536_PCI_H |
|||
|
|||
/**********************************************************************/ |
|||
|
|||
#define PCI_SPECIAL_SHUTDOWN 1 |
|||
|
|||
/************************* PCI BUS DEVICE FUNCTION ********************/ |
|||
|
|||
/*
|
|||
* PCI bus device function |
|||
*/ |
|||
#define PCI_BUS_CS5536 0 |
|||
#define PCI_CFG_BASE 0x02000000 |
|||
|
|||
#define CS5536_ISA_FUNC 0 |
|||
#define CS5536_FLASH_FUNC 1 |
|||
#define CS5536_IDE_FUNC 2 |
|||
#define CS5536_ACC_FUNC 3 |
|||
#define CS5536_OHCI_FUNC 4 |
|||
#define CS5536_EHCI_FUNC 5 |
|||
#define CS5536_UDC_FUNC 6 |
|||
#define CS5536_OTG_FUNC 7 |
|||
#define CS5536_FUNC_START 0 |
|||
#define CS5536_FUNC_END 7 |
|||
#define CS5536_FUNC_COUNT (CS5536_FUNC_END - CS5536_FUNC_START + 1) |
|||
|
|||
/***************************** STANDARD PCI-2.2 EXPANSION ***********************/ |
|||
|
|||
/*
|
|||
* PCI configuration space |
|||
* we have to virtualize the PCI configure space head, so we should |
|||
* define the necessary IDs and some others. |
|||
*/ |
|||
/* VENDOR ID */ |
|||
#define CS5536_VENDOR_ID 0x1022 |
|||
|
|||
/* DEVICE ID */ |
|||
#define CS5536_ISA_DEVICE_ID 0x2090 |
|||
#define CS5536_FLASH_DEVICE_ID 0x2091 |
|||
#define CS5536_IDE_DEVICE_ID 0x2092 |
|||
#define CS5536_ACC_DEVICE_ID 0x2093 |
|||
#define CS5536_OHCI_DEVICE_ID 0x2094 |
|||
#define CS5536_EHCI_DEVICE_ID 0x2095 |
|||
#define CS5536_UDC_DEVICE_ID 0x2096 |
|||
#define CS5536_OTG_DEVICE_ID 0x2097 |
|||
|
|||
/* CLASS CODE : CLASS SUB-CLASS INTERFACE */ |
|||
#define CS5536_ISA_CLASS_CODE 0x060100 |
|||
#define CS5536_FLASH_CLASS_CODE 0x050100 |
|||
#define CS5536_IDE_CLASS_CODE 0x010180 |
|||
#define CS5536_ACC_CLASS_CODE 0x040100 |
|||
#define CS5536_OHCI_CLASS_CODE 0x0C0310 |
|||
#define CS5536_EHCI_CLASS_CODE 0x0C0320 |
|||
#define CS5536_UDC_CLASS_CODE 0x0C03FE |
|||
#define CS5536_OTG_CLASS_CODE 0x0C0380 |
|||
|
|||
/* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */ |
|||
#define PCI_NONE_BIST 0x00 //RO not implemented yet.
|
|||
#define PCI_BRIDGE_HEADER_TYPE 0x80 //RO
|
|||
#define PCI_NORMAL_HEADER_TYPE 0x00 |
|||
#define PCI_NORMAL_LATENCY_TIMER 0x40 |
|||
#define PCI_NORMAL_CACHE_LINE_SIZE 0x08 //RW
|
|||
|
|||
/* BAR */ |
|||
#define PCI_BAR0_REG 0x10 |
|||
#define PCI_BAR1_REG 0x14 |
|||
#define PCI_BAR2_REG 0x18 |
|||
#define PCI_BAR3_REG 0x1c |
|||
#define PCI_BAR4_REG 0x20 |
|||
#define PCI_BAR5_REG 0x24 |
|||
#define PCI_BAR_COUNT 6 |
|||
#define PCI_BAR_RANGE_MASK 0xFFFFFFFE |
|||
|
|||
/* CARDBUS CIS POINTER */ |
|||
#define PCI_CARDBUS_CIS_POINTER 0x00000000 |
|||
|
|||
/* SUBSYSTEM VENDOR ID */ |
|||
#define CS5536_SUB_VENDOR_ID CS5536_VENDOR_ID |
|||
|
|||
/* SUBSYSTEM ID */ |
|||
#define CS5536_ISA_SUB_ID CS5536_ISA_DEVICE_ID |
|||
#define CS5536_FLASH_SUB_ID CS5536_FLASH_DEVICE_ID |
|||
#define CS5536_IDE_SUB_ID CS5536_IDE_DEVICE_ID |
|||
#define CS5536_ACC_SUB_ID CS5536_ACC_DEVICE_ID |
|||
#define CS5536_OHCI_SUB_ID CS5536_OHCI_DEVICE_ID |
|||
#define CS5536_EHCI_SUB_ID CS5536_EHCI_DEVICE_ID |
|||
#define CS5536_UDC_SUB_ID CS5536_UDC_DEVICE_ID |
|||
#define CS5536_OTG_SUB_ID CS5536_OTG_DEVICE_ID |
|||
|
|||
/* EXPANSION ROM BAR */ |
|||
#define PCI_EXPANSION_ROM_BAR 0x00000000 |
|||
|
|||
/* CAPABILITIES POINTER */ |
|||
#define PCI_CAPLIST_POINTER 0x00000000 |
|||
#define PCI_CAPLIST_USB_POINTER 0x40 |
|||
/* INTERRUPT */ |
|||
#define PCI_MAX_LATENCY 0x00 |
|||
#define PCI_MIN_GRANT 0x00 |
|||
|
|||
/**************************** EXPANSION PCI REG **************************************/ |
|||
|
|||
/*
|
|||
* IDE EXPANSION |
|||
*/ |
|||
#define PCI_IDE_CFG_REG 0x40 |
|||
#define CS5536_IDE_FLASH_SIGNATURE 0xDEADBEEF |
|||
#define PCI_IDE_DTC_REG 0x48 |
|||
#define PCI_IDE_CAST_REG 0x4C |
|||
#define PCI_IDE_ETC_REG 0x50 |
|||
#define PCI_IDE_PM_REG 0x54 |
|||
|
|||
/*
|
|||
* OHCI EXPANSION |
|||
*/ |
|||
#define PCI_USB_PM_REG 0x40 |
|||
|
|||
/*
|
|||
* EHCI EXPANSION |
|||
*/ |
|||
#define PCI_EHCI_LEGSMIEN_REG 0x50 |
|||
#define PCI_EHCI_LEGSMISTS_REG 0x54 |
|||
#define PCI_EHCI_FLADJ_REG 0x60 |
|||
|
|||
#endif /* _CS5536_PCI_H_ */ |
|||
|
|||
@ -0,0 +1,18 @@ |
|||
#ifndef FIREWALL_H |
|||
#define FIREWALL_H |
|||
|
|||
#define PCI_IDSEL_ATP8260 9 |
|||
#define IOG 0x4000 |
|||
#define I2CREG_ADDR (0xbfd00000|(IOG)|0xB0) |
|||
#define I2C_NACK 0x80 |
|||
#define I2C_RD 0x20 |
|||
#define I2C_WR 0x10 |
|||
#define I2C_START 0x80 |
|||
#define I2C_STOP 0x40 |
|||
|
|||
#define LS2F_COMA_ADDR 0xbe000000 |
|||
#define LS2F_COMB_ADDR 0xbe000020 |
|||
#define LS2F_PP_ADDR 0xbe000040 |
|||
#define LS2F_COM_CLK 1843200 |
|||
|
|||
#endif |
|||
@ -0,0 +1,81 @@ |
|||
/*
|
|||
* i8254.h: definitions for i8254 programmable interval timer in P5064 |
|||
* |
|||
* Copyright (c) 1997-1999, Algorithmics Ltd. All rights reserved. |
|||
* |
|||
* This program is free software; you can redistribute it and/or modify |
|||
* it under the terms of the "Free MIPS" License Agreement, a copy of |
|||
* which is available at: |
|||
* |
|||
* http://www.algor.co.uk/ftp/pub/doc/freemips-license.txt
|
|||
* |
|||
* You may not, however, modify or remove any part of this copyright |
|||
* message if this program is redistributed or reused in whole or in |
|||
* part. |
|||
* |
|||
* This program is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* "Free MIPS" License for more details. |
|||
*/ |
|||
|
|||
/* Timer 0 is clock interrupt (irq0)
|
|||
* Timer 1 is refresh clock |
|||
* Timer 2 is speaker tone |
|||
*/ |
|||
|
|||
#define PT_CLOCK 0 |
|||
#define PT_REFRESH 1 |
|||
#define PT_SPEAKER 2 |
|||
#define PT_CONTROL 3 |
|||
|
|||
#ifndef __ASSEMBLER__ |
|||
struct i8254 { |
|||
unsigned char pt_counter0; |
|||
unsigned char pt_counter1; |
|||
unsigned char pt_counter2; |
|||
unsigned char pt_control; |
|||
}; |
|||
|
|||
#define pt_clock pt_counter0 |
|||
#define pt_refresh pt_counter1 |
|||
#define pt_speaker pt_counter2 |
|||
|
|||
#else |
|||
|
|||
#define PT_REG(x) (x) |
|||
|
|||
#endif |
|||
|
|||
/*
|
|||
* control word definitions |
|||
*/ |
|||
#define PTCW_RBCMD (3<<6) /* read-back command */ |
|||
#define PTCW_RB_NCNT 0x20 /* rb: no count */ |
|||
#define PTCW_RB_NSTAT 0x10 /* rb: no status */ |
|||
#define PTCW_RB_SC(x) (0x02<<(x)) /* rb: select counter x */ |
|||
#define PTCW_SC(x) ((x)<<6) /* select counter x */ |
|||
#define PTCW_CLCMD (0<<4) /* counter latch command */ |
|||
#define PTCW_LSB (1<<4) /* r/w least signif. byte only */ |
|||
#define PTCW_MSB (2<<4) /* r/w most signif. byte only */ |
|||
#define PTCW_16B (3<<4) /* r/w 16 bits, lsb then msb */ |
|||
#define PTCW_MODE(x) ((x)<<1) /* set mode to x */ |
|||
#define PTCW_BCD 0x1 /* operate in BCD mode */ |
|||
|
|||
/*
|
|||
* Status word definitions |
|||
*/ |
|||
#define PTSW_OUTPUT 0x80 /* output pin active */ |
|||
#define PTSW_NULL 0x40 /* null count */ |
|||
|
|||
/*
|
|||
* Mode definitions |
|||
*/ |
|||
#define MODE_ITC 0 /* interrupt on terminal count */ |
|||
#define MODE_HROS 1 /* hw retriggerable one-shot */ |
|||
#define MODE_RG 2 /* rate generator */ |
|||
#define MODE_SQW 3 /* square wave generator */ |
|||
#define MODE_STS 4 /* software triggered strobe */ |
|||
#define MODE_HTS 5 /* hardware triggered strobe */ |
|||
|
|||
#define PT_CRYSTAL 14318180 /* timer crystal hz (ticks/sec) */ |
|||
@ -0,0 +1,189 @@ |
|||
/* $OpenBSD: isapnpreg.h,v 1.4 1997/12/25 09:22:41 downsj Exp $ */ |
|||
/* $NetBSD: isapnpreg.h,v 1.5 1997/08/12 07:34:34 mikel Exp $ */ |
|||
|
|||
/*
|
|||
* Copyright (c) 199 Christos Zoulas. All rights reserved. |
|||
* |
|||
* Redistribution and use in source and binary forms, with or without |
|||
* modification, are permitted provided that the following conditions |
|||
* are met: |
|||
* 1. Redistributions of source code must retain the above copyright |
|||
* notice, this list of conditions and the following disclaimer. |
|||
* 2. Redistributions in binary form must reproduce the above copyright |
|||
* notice, this list of conditions and the following disclaimer in the |
|||
* documentation and/or other materials provided with the distribution. |
|||
* 3. All advertising materials mentioning features or use of this software |
|||
* must display the following acknowledgement: |
|||
* This product includes software developed by Christos Zoulas. |
|||
* 4. The name of the author may not be used to endorse or promote products |
|||
* derived from this software without specific prior written permission. |
|||
* |
|||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
|||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
|||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
|||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
|||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
|||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
|||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
|||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
|||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
|||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
|||
*/ |
|||
|
|||
#ifndef _DEV_ISA_ISAPNPREG_H_ |
|||
#define _DEV_ISA_ISAPNPREG_H_ |
|||
|
|||
/*
|
|||
* ISA Plug and Play register definitions; |
|||
* From Plug and Play ISA Specification V1.0a, May 5 1994 |
|||
*/ |
|||
|
|||
#define ISAPNP_MAX_CARDS 8 |
|||
#define ISAPNP_MAX_IDENT 32 |
|||
#define ISAPNP_MAX_DEVCLASS 16 |
|||
#define ISAPNP_SERIAL_SIZE 9 |
|||
#define ISAPNP_MAX_TAGSIZE 256 |
|||
|
|||
#define ISAPNP_ADDR 0x279 /* Write only */ |
|||
#define ISAPNP_WRDATA 0xa79 /* Write only */ |
|||
|
|||
/* The read port is in range 0x203 to 0x3ff */ |
|||
#define ISAPNP_RDDATA_MIN 0x203 /* Read only */ |
|||
#define ISAPNP_RDDATA_MAX 0x3ff |
|||
|
|||
#define ISAPNP_LFSR_INIT 0x6A /* Initial value of LFSR sequence */ |
|||
#define ISAPNP_LFSR_LENGTH 32 /* Number of values in LFSR sequence */ |
|||
/* Formula to compute the next value */ |
|||
#define ISAPNP_LFSR_NEXT(v) (((v) >> 1) | (((v) & 1) ^ (((v) & 2) >> 1)) << 7) |
|||
|
|||
#define ISAPNP_SET_RD_PORT 0x00 |
|||
#define ISAPNP_SERIAL_ISOLATION 0x01 |
|||
#define ISAPNP_CONFIG_CONTROL 0x02 |
|||
#define ISAPNP_CC_RESET 0x01 |
|||
#define ISAPNP_CC_WAIT_FOR_KEY 0x02 |
|||
#define ISAPNP_CC_RESET_CSN 0x04 |
|||
#define ISAPNP_CC_RESET_DRV 0x07 |
|||
#define ISAPNP_WAKE 0x03 |
|||
#define ISAPNP_RESOURCE_DATA 0x04 |
|||
#define ISAPNP_STATUS 0x05 |
|||
#define ISAPNP_CARD_SELECT_NUM 0x06 |
|||
#define ISAPNP_LOGICAL_DEV_NUM 0x07 |
|||
|
|||
#define ISAPNP_ACTIVATE 0x30 |
|||
#define ISAPNP_IO_RANGE_CHECK 0x31 |
|||
|
|||
#define ISAPNP_NUM_MEM 4 |
|||
#define ISAPNP_MEM_DESC { 0x40, 0x48, 0x50, 0x58 } |
|||
#define ISAPNP_MEM_BASE_23_16 0x0 |
|||
#define ISAPNP_MEM_BASE_15_8 0x1 |
|||
#define ISAPNP_MEM_CONTROL 0x2 |
|||
#define ISAPNP_MEM_CONTROL_LIMIT 1 |
|||
#define ISAPNP_MEM_CONTROL_16 2 |
|||
#define ISAPNP_MEM_LRANGE_23_16 0x3 |
|||
#define ISAPNP_MEM_LRANGE_15_8 0x4 |
|||
|
|||
#define ISAPNP_NUM_IO 8 |
|||
|
|||
#define ISAPNP_IO_DESC0 0x60 |
|||
#define ISAPNP_IO_DESC1 0x62 |
|||
#define ISAPNP_IO_DESC2 0x64 |
|||
#define ISAPNP_IO_DESC3 0x66 |
|||
#define ISAPNP_IO_DESC4 0x68 |
|||
#define ISAPNP_IO_DESC5 0x6a |
|||
#define ISAPNP_IO_DESC6 0x6c |
|||
#define ISAPNP_IO_DESC7 0x6e |
|||
#define ISAPNP_IO_DESC { 0x60, 0x62, 0x64, 0x68, 0x6a, 0x6c, 0x6e } |
|||
#define ISAPNP_IO_BASE_15_8 0x0 |
|||
#define ISAPNP_IO_BASE_7_0 0x1 |
|||
|
|||
#define ISAPNP_IRQ_DESC0 0x70 |
|||
#define ISAPNP_IRQ_DESC1 0x72 |
|||
#define ISAPNP_NUM_IRQ 16 |
|||
#define ISAPNP_IRQ_DESC { 0x70, 0x72 } |
|||
#define ISAPNP_IRQ_NUMBER 0x0 |
|||
#define ISAPNP_IRQ_CONTROL 0x1 |
|||
#define ISAPNP_IRQ_LEVEL 1 |
|||
#define ISAPNP_IRQ_HIGH 2 |
|||
|
|||
#define ISAPNP_NUM_DRQ 8 |
|||
#define ISAPNP_DRQ_DESC { 0x74, 0x75 } |
|||
|
|||
#define ISAPNP_NUM_MEM32 4 |
|||
#define ISAPNP_MEM32_DESC { 0x76, 0x80, 0x90, 0xa0 } |
|||
#define ISAPNP_MEM32_BASE_31_24 0x0 |
|||
#define ISAPNP_MEM32_BASE_23_16 0x1 |
|||
#define ISAPNP_MEM32_BASE_15_8 0x2 |
|||
#define ISAPNP_MEM32_BASE_7_0 0x3 |
|||
#define ISAPNP_MEM32_CONTROL 0x4 |
|||
#define ISAPNP_MEM32_CONTROL_LIMIT 1 |
|||
#define ISAPNP_MEM32_CONTROL_16 2 |
|||
#define ISAPNP_MEM32_CONTROL_32 6 |
|||
#define ISAPNP_MEM32_LRANGE_31_24 0x5 |
|||
#define ISAPNP_MEM32_LRANGE_23_16 0x6 |
|||
#define ISAPNP_MEM32_LRANGE_15_8 0x7 |
|||
#define ISAPNP_MEM32_LRANGE_7_0 0x8 |
|||
|
|||
/* Small Tags */ |
|||
#define ISAPNP_TAG_VERSION_NUM 0x1 |
|||
#define ISAPNP_TAG_LOGICAL_DEV_ID 0x2 |
|||
#define ISAPNP_TAG_COMPAT_DEV_ID 0x3 |
|||
#define ISAPNP_TAG_IRQ_FORMAT 0x4 |
|||
#define ISAPNP_IRQTYPE_EDGE_PLUS 1 |
|||
#define ISAPNP_IRQTYPE_EDGE_MINUS 2 |
|||
#define ISAPNP_IRQTYPE_LEVEL_PLUS 4 |
|||
#define ISAPNP_IRQTYPE_LEVEL_MINUS 8 |
|||
#define ISAPNP_TAG_DMA_FORMAT 0x5 |
|||
#define ISAPNP_DMAWIDTH_8 0x00 |
|||
#define ISAPNP_DMAWIDTH_8_16 0x01 |
|||
#define ISAPNP_DMAWIDTH_16 0x02 |
|||
#define ISAPNP_DMAWIDTH_RESERVED 0x03 |
|||
#define ISAPNP_DMAWIDTH_MASK 0x03 |
|||
#define ISAPNP_DMAATTR_BUS_MASTER 0x04 |
|||
#define ISAPNP_DMAATTR_INCR_8 0x08 |
|||
#define ISAPNP_DMAATTR_INCR_16 0x10 |
|||
#define ISAPNP_DMAATTR_MASK 0x1c |
|||
#define ISAPNP_DMASPEED_COMPAT 0x00 |
|||
#define ISAPNP_DMASPEED_A 0x20 |
|||
#define ISAPNP_DMASPEED_B 0x40 |
|||
#define ISAPNP_DMASPEED_F 0x60 |
|||
#define ISAPNP_DMASPEED_MASK 0x60 |
|||
#define ISAPNP_TAG_DEP_START 0x6 |
|||
#define ISAPNP_DEP_PREFERRED 0x0 |
|||
#define ISAPNP_DEP_ACCEPTABLE 0x1 |
|||
#define ISAPNP_DEP_FUNCTIONAL 0x2 |
|||
#define ISAPNP_DEP_RESERVED 0x3 |
|||
#define ISAPNP_DEP_MASK 0x3 |
|||
#define ISAPNP_DEP_UNSET 0x80 /* Internal */ |
|||
#define ISAPNP_DEP_CONFLICTING 0x81 /* Internal */ |
|||
#define ISAPNP_TAG_DEP_END 0x7 |
|||
#define ISAPNP_TAG_IO_PORT_DESC 0x8 |
|||
#define ISAPNP_IOFLAGS_16 0x1 |
|||
#define ISAPNP_TAG_FIXED_IO_PORT_DESC 0x9 |
|||
#define ISAPNP_TAG_RESERVED1 0xa |
|||
#define ISAPNP_TAG_RESERVED2 0xb |
|||
#define ISAPNP_TAG_RESERVED3 0xc |
|||
#define ISAPNP_TAG_RESERVED4 0xd |
|||
#define ISAPNP_TAG_VENDOR_DEF 0xe |
|||
#define ISAPNP_TAG_END 0xf |
|||
|
|||
/* Large Tags */ |
|||
#define ISAPNP_LARGE_TAG 0x80 |
|||
#define ISAPNP_TAG_MEM_RANGE_DESC 0x81 |
|||
#define ISAPNP_MEMATTR_WRITEABLE 0x01 |
|||
#define ISAPNP_MEMATTR_CACHEABLE 0x02 |
|||
#define ISAPNP_MEMATTR_HIGH_ADDR 0x04 |
|||
#define ISAPNP_MEMATTR_SHADOWABLE 0x20 |
|||
#define ISAPNP_MEMATTR_ROM 0x40 |
|||
#define ISAPNP_MEMATTR_MASK 0x67 |
|||
#define ISAPNP_MEMWIDTH_8 0x00 |
|||
#define ISAPNP_MEMWIDTH_16 0x08 |
|||
#define ISAPNP_MEMWIDTH_8_16 0x10 |
|||
#define ISAPNP_MEMWIDTH_32 0x18 |
|||
#define ISAPNP_MEMWIDTH_MASK 0x18 |
|||
#define ISAPNP_TAG_ANSI_IDENT_STRING 0x82 |
|||
#define ISAPNP_TAG_UNICODE_IDENT_STRING 0x83 |
|||
#define ISAPNP_TAG_VENDOR_DEFINED 0x84 |
|||
#define ISAPNP_TAG_MEM32_RANGE_DESC 0x85 |
|||
#define ISAPNP_TAG_FIXED_MEM32_RANGE_DESC 0x86 |
|||
|
|||
#endif /* _DEV_ISA_ISAPNPREG_H_ */ |
|||
@ -0,0 +1,65 @@ |
|||
/* $Id: pmon_target.h,v 1.1.1.1 2006/09/14 01:59:09 root Exp $ */ |
|||
|
|||
/*
|
|||
* Copyright (c) 2001 Opsycon AB (www.opsycon.se) |
|||
* |
|||
* Redistribution and use in source and binary forms, with or without |
|||
* modification, are permitted provided that the following conditions |
|||
* are met: |
|||
* 1. Redistributions of source code must retain the above copyright |
|||
* notice, this list of conditions and the following disclaimer. |
|||
* 2. Redistributions in binary form must reproduce the above copyright |
|||
* notice, this list of conditions and the following disclaimer in the |
|||
* documentation and/or other materials provided with the distribution. |
|||
* 3. All advertising materials mentioning features or use of this software |
|||
* must display the following acknowledgement: |
|||
* This product includes software developed by Opsycon AB, Sweden. |
|||
* 4. The name of the author may not be used to endorse or promote products |
|||
* derived from this software without specific prior written permission. |
|||
* |
|||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS |
|||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
|||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
|||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
|||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
|||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
|||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
|||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
|||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
|||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
|||
* SUCH DAMAGE. |
|||
* |
|||
*/ |
|||
|
|||
#include <target/bonito.h> |
|||
|
|||
#ifdef SBD_DEBUG |
|||
#define SBD_DISPLAY(text, code) /* No display function */ |
|||
#else |
|||
void hexserial __P((int)); |
|||
#define SBD_DISPLAY(text, code) tgt_display(text, code) |
|||
#endif |
|||
|
|||
/*
|
|||
* Name of envvar that has to be set to enable expert mode. |
|||
*/ |
|||
#define EXPERT "galileoexpert" |
|||
|
|||
/*
|
|||
* Target arch specifics |
|||
*/ |
|||
#define HAVE_QUAD /* Native 64 bit integers */ |
|||
|
|||
/*
|
|||
* Boot loader parameters. |
|||
*/ |
|||
|
|||
#define TGT_BOOT_ADR 0x80400000 /* Load 4 meg up. */ |
|||
#define TGT_BOOT_SIZ 0x00002000 /* Suck in 8k */ |
|||
#define TGT_BOOT_OFF 0x00000400 /* Start reading from byte 1024 */ |
|||
|
|||
/*
|
|||
* Target dependent CLIENTPC settings |
|||
*/ |
|||
#define CLIENTPC 0x80100000 |
|||
#define SETCLIENTPC "80100000" |
|||
@ -0,0 +1,74 @@ |
|||
/*
|
|||
* mips/prid.h: MIPS processor ID values (cp_imp field). |
|||
* |
|||
* Copyright (c) 1998-1999, Algorithmics Ltd. All rights reserved. |
|||
* |
|||
* This program is free software; you can redistribute it and/or modify |
|||
* it under the terms of the "Free MIPS" License Agreement, a copy of |
|||
* which is available at: |
|||
* |
|||
* http://www.algor.co.uk/ftp/pub/doc/freemips-license.txt
|
|||
* |
|||
* You may not, however, modify or remove any part of this copyright |
|||
* message if this program is redistributed or reused in whole or in |
|||
* part. |
|||
* |
|||
* This program is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* "Free MIPS" License for more details. |
|||
*/ |
|||
|
|||
/*
|
|||
* MIPS CPU types |
|||
*/ |
|||
#define PRID_R2000 0x01 /* MIPS R2000 CPU ISA I */ |
|||
#define PRID_R3000 0x02 /* MIPS R3000 CPU ISA I */ |
|||
#define PRID_R6000 0x03 /* MIPS R6000 CPU ISA II */ |
|||
#define PRID_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */ |
|||
#define PRID_LR33K 0x05 /* LSI Logic R3000 derivate ISA I */ |
|||
#define PRID_R6000A 0x06 /* MIPS R6000A CPU ISA II */ |
|||
#define PRID_R3IDT 0x07 /* IDT R3000 derivates ISA I */ |
|||
#define PRID_R3IDT_R3041 0x07 /* R3041 (cp_rev field) */ |
|||
#define PRID_R3IDT_R36100 0x10 /* R36100 (cp_rev field) */ |
|||
#define PRID_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */ |
|||
#define PRID_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */ |
|||
#define PRID_R4300 0x0b /* NEC VR4300 CPU ISA III */ |
|||
#define PRID_R4100 0x0c /* NEC VR4100 CPU ISA III */ |
|||
#define PRID_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ |
|||
#define PRID_RC6457X 0x15 /* IDT RC6457X CPU ISA IV */ |
|||
#define PRID_R4600 0x20 /* QED R4600 Orion ISA III */ |
|||
#define PRID_R4700 0x21 /* QED R4700 Orion ISA III */ |
|||
#define PRID_R3900 0x22 /* Toshiba/Philips R3900 CPU ISA I */ |
|||
#define PRID_R4650 0x22 /* QED R4650/R4640 CPU ISA III */ |
|||
#define PRID_R5000 0x23 /* MIPS R5000 CPU ISA IV */ |
|||
#define PRID_RC3236X 0x26 /* IDT RC3236X CPU ISA IV */ |
|||
#define PRID_RM7000 0x27 /* QED RM7000 CPU ISA IV */ |
|||
#define PRID_RM52XX 0x28 /* QED RM52XX CPU ISA IV */ |
|||
#define PRID_RC6447X 0x30 /* IDT RC6447X CPU ISA III */ |
|||
#define PRID_R5400 0x54 /* NEC Vr5400 CPU ISA IV */ |
|||
#define PRID_JADE 0x80 /* MIPS JADE ISA MIPS32 */ |
|||
|
|||
/*
|
|||
* MIPS FPU types |
|||
*/ |
|||
#define PRID_SOFT 0x00 /* Software emulation ISA I */ |
|||
#define PRID_R2360 0x01 /* MIPS R2360 FPC ISA I */ |
|||
#define PRID_R2010 0x02 /* MIPS R2010 FPC ISA I */ |
|||
#define PRID_R3010 0x03 /* MIPS R3010 FPC ISA I */ |
|||
#define PRID_R6010 0x04 /* MIPS R6010 FPC ISA II */ |
|||
#define PRID_R4010 0x05 /* MIPS R4000/R4400 FPC ISA II */ |
|||
#define PRID_LR33010 0x06 /* LSI Logic derivate ISA I */ |
|||
#define PRID_R10010 0x09 /* MIPS R10000/T5 FPU ISA IV */ |
|||
#define PRID_R4210 0x0a /* MIPS R4200 FPC (ICE) ISA III */ |
|||
#define PRID_UNKF1 0x0b /* unnanounced product cpu ISA III */ |
|||
#define PRID_R8010 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ |
|||
#define PRID_RC6457XF 0x15 /* IDT RC6457X FPU ISA IV */ |
|||
#define PRID_R4610 0x20 /* QED R4600 Orion ISA III */ |
|||
#define PRID_R3SONY 0x21 /* Sony R3000 based FPU ISA I */ |
|||
#define PRID_R3910 0x22 /* Toshiba/Philips R3900 FPU ISA I */ |
|||
#define PRID_R5010 0x23 /* MIPS R5000 FPU ISA IV */ |
|||
#define PRID_RM7000F 0x27 /* QED RM7000 FPU ISA IV */ |
|||
#define PRID_RM52XXF 0x28 /* QED RM52X FPU ISA IV */ |
|||
#define PRID_RC6447XF 0x30 /* IDT RC6447X FPU ISA III */ |
|||
#define PRID_R5400F 0x54 /* NEC Vr5400 FPU ISA IV */ |
|||
@ -0,0 +1,255 @@ |
|||
typedef void * vaddr_t_l; |
|||
|
|||
#define MIPSInst(x) x |
|||
|
|||
#define I_OPCODE_SFT 26 |
|||
#define MIPSInst_OPCODE(x) (MIPSInst(x) >> I_OPCODE_SFT) |
|||
|
|||
#define I_JTARGET_SFT 0 |
|||
#define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff) |
|||
|
|||
#define I_RS_SFT 21 |
|||
#define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT) |
|||
|
|||
#define I_RT_SFT 16 |
|||
#define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT) |
|||
|
|||
#define I_IMM_SFT 0 |
|||
#define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff))) |
|||
#define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff) |
|||
|
|||
#define I_CACHEOP_SFT 18 |
|||
#define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT) |
|||
|
|||
#define I_CACHESEL_SFT 16 |
|||
#define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT) |
|||
|
|||
#define I_RD_SFT 11 |
|||
#define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT) |
|||
|
|||
#define I_RE_SFT 6 |
|||
#define MIPSInst_RE(x) ((MIPSInst(x) & 0x000007c0) >> I_RE_SFT) |
|||
|
|||
#define I_FUNC_SFT 0 |
|||
#define MIPSInst_FUNC(x) (MIPSInst(x) & 0x0000003f) |
|||
|
|||
#define I_FFMT_SFT 21 |
|||
#define MIPSInst_FFMT(x) ((MIPSInst(x) & 0x01e00000) >> I_FFMT_SFT) |
|||
|
|||
#define I_FT_SFT 16 |
|||
#define MIPSInst_FT(x) ((MIPSInst(x) & 0x001f0000) >> I_FT_SFT) |
|||
|
|||
#define I_FS_SFT 11 |
|||
#define MIPSInst_FS(x) ((MIPSInst(x) & 0x0000f800) >> I_FS_SFT) |
|||
|
|||
#define I_FD_SFT 6 |
|||
#define MIPSInst_FD(x) ((MIPSInst(x) & 0x000007c0) >> I_FD_SFT) |
|||
|
|||
#define I_FR_SFT 21 |
|||
#define MIPSInst_FR(x) ((MIPSInst(x) & 0x03e00000) >> I_FR_SFT) |
|||
|
|||
#define I_FMA_FUNC_SFT 2 |
|||
#define MIPSInst_FMA_FUNC(x) ((MIPSInst(x) & 0x0000003c) >> I_FMA_FUNC_SFT) |
|||
|
|||
#define I_FMA_FFMT_SFT 0 |
|||
#define MIPSInst_FMA_FFMT(x) (MIPSInst(x) & 0x00000003) |
|||
|
|||
#define REG_TO_VA_l (vaddr_t_l) |
|||
#define VA_TO_REG_l (unsigned long) |
|||
|
|||
#define CAUSEB_BD 31 |
|||
#define CAUSEF_BD (1 << 31) |
|||
|
|||
|
|||
typedef unsigned int mips_instruction; |
|||
|
|||
/*
|
|||
* Major opcodes; before MIPS IV cop1x was called cop3. |
|||
*/ |
|||
enum major_op { |
|||
spec_op, bcond_op, j_op, jal_op, |
|||
beq_op, bne_op, blez_op, bgtz_op, |
|||
addi_op, addiu_op, slti_op, sltiu_op, |
|||
andi_op, ori_op, xori_op, lui_op, |
|||
cop0_op, cop1_op, cop2_op, cop1x_op, |
|||
beql_op, bnel_op, blezl_op, bgtzl_op, |
|||
daddi_op, daddiu_op, ldl_op, ldr_op, |
|||
major_1c_op, jalx_op, major_1e_op, major_1f_op, |
|||
lb_op, lh_op, lwl_op, lw_op, |
|||
lbu_op, lhu_op, lwr_op, lwu_op, |
|||
sb_op, sh_op, swl_op, sw_op, |
|||
sdl_op, sdr_op, swr_op, cache_op, |
|||
ll_op, lwc1_op, lwc2_op, pref_op, |
|||
lld_op, ldc1_op, ldc2_op, ld_op, |
|||
sc_op, swc1_op, swc2_op, major_3b_op, /* Opcode 0x3b is unused */ |
|||
scd_op, sdc1_op, sdc2_op, sd_op |
|||
}; |
|||
|
|||
/*
|
|||
* func field of spec opcode. |
|||
*/ |
|||
enum spec_op { |
|||
sll_op, movc_op, srl_op, sra_op, |
|||
sllv_op, srlv_op, srav_op, spec1_unused_op, /* Opcode 0x07 is unused */ |
|||
jr_op, jalr_op, movz_op, movn_op, |
|||
syscall_op, break_op, spim_op, sync_op, |
|||
mfhi_op, mthi_op, mflo_op, mtlo_op, |
|||
dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op, |
|||
mult_op, multu_op, div_op, divu_op, |
|||
dmult_op, dmultu_op, ddiv_op, ddivu_op, |
|||
add_op, addu_op, sub_op, subu_op, |
|||
and_op, or_op, xor_op, nor_op, |
|||
spec3_unused_op, spec4_unused_op, slt_op, sltu_op, |
|||
dadd_op, daddu_op, dsub_op, dsubu_op, |
|||
tge_op, tgeu_op, tlt_op, tltu_op, |
|||
teq_op, spec5_unused_op, tne_op, spec6_unused_op, |
|||
dsll_op, spec7_unused_op, dsrl_op, dsra_op, |
|||
dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op |
|||
}; |
|||
|
|||
/*
|
|||
* rt field of bcond opcodes. |
|||
*/ |
|||
enum rt_op { |
|||
bltz_op, bgez_op, bltzl_op, bgezl_op, |
|||
spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07, |
|||
tgei_op, tgeiu_op, tlti_op, tltiu_op, |
|||
teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op, |
|||
bltzal_op, bgezal_op, bltzall_op, bgezall_op |
|||
/*
|
|||
* The others (0x14 - 0x1f) are unused. |
|||
*/ |
|||
}; |
|||
|
|||
/*
|
|||
* rs field of cop opcodes. |
|||
*/ |
|||
enum cop_op { |
|||
mfc_op = 0x00, dmfc_op = 0x01, |
|||
cfc_op = 0x02, mtc_op = 0x04, |
|||
dmtc_op = 0x05, ctc_op = 0x06, |
|||
bc_op = 0x08, cop_op = 0x10, |
|||
copm_op = 0x18 |
|||
}; |
|||
|
|||
/*
|
|||
* rt field of cop.bc_op opcodes |
|||
*/ |
|||
|
|||
enum bcop_op { |
|||
bcf_op, bct_op, bcfl_op, bctl_op |
|||
}; |
|||
|
|||
/*
|
|||
* func field of cop0 coi opcodes. |
|||
*/ |
|||
enum cop0_coi_func { |
|||
tlbr_op = 0x01, tlbwi_op = 0x02, |
|||
tlbwr_op = 0x06, tlbp_op = 0x08, |
|||
rfe_op = 0x10, eret_op = 0x18 |
|||
}; |
|||
|
|||
/*
|
|||
* func field of cop0 com opcodes. |
|||
*/ |
|||
enum cop0_com_func { |
|||
tlbr1_op = 0x01, tlbw_op = 0x02, |
|||
tlbp1_op = 0x08, dctr_op = 0x09, |
|||
dctw_op = 0x0a |
|||
}; |
|||
|
|||
/*
|
|||
* fmt field of cop1 opcodes. |
|||
*/ |
|||
enum cop1_fmt { |
|||
s_fmt, d_fmt, e_fmt, q_fmt, |
|||
w_fmt, l_fmt |
|||
}; |
|||
|
|||
/*
|
|||
* func field of cop1 instructions using d, s or w format. |
|||
*/ |
|||
enum cop1_sdw_func { |
|||
fadd_op = 0x00, fsub_op = 0x01, |
|||
fmul_op = 0x02, fdiv_op = 0x03, |
|||
fsqrt_op = 0x04, fabs_op = 0x05, |
|||
fmov_op = 0x06, fneg_op = 0x07, |
|||
froundl_op = 0x08, ftruncl_op = 0x09, |
|||
fceill_op = 0x0a, ffloorl_op = 0x0b, |
|||
fround_op = 0x0c, ftrunc_op = 0x0d, |
|||
fceil_op = 0x0e, ffloor_op = 0x0f, |
|||
fmovc_op = 0x11, fmovz_op = 0x12, |
|||
fmovn_op = 0x13, frecip_op = 0x15, |
|||
frsqrt_op = 0x16, fcvts_op = 0x20, |
|||
fcvtd_op = 0x21, fcvte_op = 0x22, |
|||
fcvtw_op = 0x24, fcvtl_op = 0x25, |
|||
fcmp_op = 0x30 |
|||
}; |
|||
|
|||
/*
|
|||
* func field of cop1x opcodes (MIPS IV). |
|||
*/ |
|||
enum cop1x_func { |
|||
lwxc1_op = 0x00, ldxc1_op = 0x01, |
|||
pfetch_op = 0x07, swxc1_op = 0x08, |
|||
sdxc1_op = 0x09, madd_s_op = 0x20, |
|||
madd_d_op = 0x21, madd_e_op = 0x22, |
|||
msub_s_op = 0x28, msub_d_op = 0x29, |
|||
msub_e_op = 0x2a, nmadd_s_op = 0x30, |
|||
nmadd_d_op = 0x31, nmadd_e_op = 0x32, |
|||
nmsub_s_op = 0x38, nmsub_d_op = 0x39, |
|||
nmsub_e_op = 0x3a |
|||
}; |
|||
|
|||
/*
|
|||
* func field for mad opcodes (MIPS IV). |
|||
*/ |
|||
enum mad_func { |
|||
madd_op = 0x08, msub_op = 0x0a, |
|||
nmadd_op = 0x0c, nmsub_op = 0x0e |
|||
}; |
|||
|
|||
struct pt_regs { |
|||
/* Pad bytes for argument save space on the stack. */ |
|||
unsigned long pad0[6]; |
|||
|
|||
/* Saved main processor registers. */ |
|||
unsigned long regs[32]; |
|||
|
|||
/* Other saved registers. */ |
|||
unsigned long lo; |
|||
unsigned long hi; |
|||
|
|||
/*
|
|||
* saved cp0 registers |
|||
*/ |
|||
unsigned long cp0_epc; |
|||
unsigned long cp0_badvaddr; |
|||
unsigned long cp0_status; |
|||
unsigned long cp0_cause; |
|||
}; |
|||
|
|||
#define SIGHUP 1 /* Hangup (POSIX). */ |
|||
#define SIGINT 2 /* Interrupt (ANSI). */ |
|||
#define SIGQUIT 3 /* Quit (POSIX). */ |
|||
#define SIGILL 4 /* Illegal instruction (ANSI). */ |
|||
#define SIGTRAP 5 /* Trace trap (POSIX). */ |
|||
#define SIGEMT 7 |
|||
#define SIGFPE 8 /* Floating-point exception (ANSI). */ |
|||
#define SIGKILL 9 /* Kill, unblockable (POSIX). */ |
|||
#define SIGBUS 10 /* BUS error (4.2 BSD). */ |
|||
#define SIGSEGV 11 /* Segmentation violation (ANSI). */ |
|||
#define SIGSYS 12 |
|||
#define SIGPIPE 13 /* Broken pipe (POSIX). */ |
|||
#define SIGALRM 14 /* Alarm clock (POSIX). */ |
|||
#define SIGTERM 15 /* Termination (ANSI). */ |
|||
#define SIGCLD SIGCHLD /* Same as SIGCHLD (System V). */ |
|||
#define SIGPWR 19 /* Power failure restart (System V). */ |
|||
#define SIGPOLL SIGIO /* Pollable event occurred (System V). */ |
|||
//bjzheng
|
|||
#define check_axs(pc,a,s) \ |
|||
if ((long)(~(pc) & ((a) | ((a)+(s)))) < 0) \ |
|||
return -1; |
|||
|
|||
#define user_mode(regs) ((regs)->cp0_status & 0x10) |
|||
extern int do_ri(struct pt_regs *); |
|||
@ -0,0 +1,229 @@ |
|||
/*
|
|||
* p6032/sbd.h: Algorithmics P-6032 board definition header file |
|||
* |
|||
* Copyright (c) 2000 Algorithmics Ltd - all rights reserved. |
|||
* |
|||
* This program is NOT free software, it is supplied under the terms |
|||
* of the SDE-MIPS License Agreement, a copy of which is available at: |
|||
* |
|||
* http://www.algor.co.uk/algor/info/sde-license.pdf
|
|||
* |
|||
* Any company which has obtained and signed a valid SDE-MIPS license |
|||
* may use and modify this software internally and use (without |
|||
* restrictions) any derived binary. You may not, however, |
|||
* redistribute this in whole or in part as source code, nor may you |
|||
* modify or remove any part of this copyright message. |
|||
*/ |
|||
|
|||
#ifndef __SBD_H__ |
|||
#define __SBD_H__ |
|||
|
|||
#ifndef MHZ |
|||
/* fastest possible pipeline clock */ |
|||
#define MHZ 200 |
|||
#endif |
|||
|
|||
#ifndef SYSCLK_MHZ |
|||
/* fastest possible bus clock */ |
|||
#define SYSCLK_MHZ 100 |
|||
#endif |
|||
|
|||
#define RAMCYCLE 60 /* ~60ns dram cycle */ |
|||
#define ROMCYCLE 800 /* ~1500ns rom cycle */ |
|||
#define CACHECYCLE (1000/MHZ) /* pipeline clock */ |
|||
#define CYCLETIME CACHECYCLE |
|||
#define CACHEMISS (CYCLETIME * 6) |
|||
|
|||
/*
|
|||
* rough scaling factors for 2 instruction DELAY loop to get 1ms and 1us delays |
|||
*/ |
|||
#define ASMDELAY(ns,icycle) \ |
|||
(((ns) + (icycle)) / ((icycle) * 2)) |
|||
|
|||
#define CACHENS(ns) ASMDELAY((ns), CACHECYCLE) |
|||
#define RAMNS(ns) ASMDELAY((ns), CACHEMISS+RAMCYCLE) |
|||
#define ROMNS(ns) ASMDELAY((ns), CACHEMISS+ROMCYCLE) |
|||
#define CACHEUS(us) ASMDELAY((us)*1000, CACHECYCLE) |
|||
#define RAMUS(us) ASMDELAY((us)*1000, CACHEMISS+RAMCYCLE) |
|||
#define ROMUS(us) ASMDELAY((us)*1000, CACHEMISS+ROMCYCLE) |
|||
#define CACHEMS(ms) ((ms) * ASMDELAY(1000000, CACHECYCLE)) |
|||
#define RAMMS(ms) ((ms) * ASMDELAY(1000000, CACHEMISS+RAMCYCLE)) |
|||
#define ROMMS(ms) ((ms) * ASMDELAY(1000000, CACHEMISS+ROMCYCLE)) |
|||
|
|||
#ifndef __ASSEMBLER__ |
|||
extern void _sbd_nsdelay (unsigned long); |
|||
#define nsdelay(ns) _sbd_nsdelay(ns) |
|||
#define usdelay(us) _sbd_nsdelay((us)*1000) |
|||
#define msdelay(ms) _sbd_nsdelay((ms)*1000000) |
|||
#endif |
|||
|
|||
|
|||
#define PCI_MEM_SPACE (BONITO_PCILO_BASE+0x00000000) /* 192MB */ |
|||
#define PCI_MEM_SPACE_SIZE BONITO_PCILO_SIZE |
|||
#define PCI_IO_SPACE BONITO_PCIIO_BASE /* 1MB */ |
|||
#define PCI_IO_SPACE_SIZE BONITO_PCIIO_SIZE |
|||
#define PCI_CFG_SPACE BONITO_PCICFG_BASE /* 512KB */ |
|||
#define PCI_CFG_SPACE_SIZE BONITO_PCICFG_SIZE |
|||
#define BOOTPROM_BASE BONITO_BOOT_BASE |
|||
#define BONITO_BASE BONITO_REG_BASE |
|||
#define CPLD_BASE (BONITO_DEV_BASE+0x00000) /* IOCS0 */ |
|||
#define LED_BASE (BONITO_DEV_BASE+0x40000) /* IOCS1 */ |
|||
#define IDE0_BASE (BONITO_DEV_BASE+0x80000) /* IOCS2 */ |
|||
#define IDE1_BASE (BONITO_DEV_BASE+0xc0000) /* IOCS3 */ |
|||
#define FLASH_BASE BONITO_FLASH_BASE |
|||
#define FLASH_SIZE BONITO_FLASH_SIZE |
|||
#define BOOT_BASE BONITO_BOOT_BASE |
|||
#define BOOT_SIZE BONITO_BOOT_SIZE |
|||
#define SOCKET_BASE BONITO_SOCKET_BASE |
|||
#define SOCKET_SIZE BONITO_SOCKET_SIZE |
|||
|
|||
#define PCI_IDSEL_SLOT1 13 |
|||
#define PCI_IDSEL_SLOT2 14 |
|||
#define PCI_IDSEL_SLOT3 15 |
|||
#define PCI_IDSEL_SLOT4 16 |
|||
#define PCI_IDSEL_ETH 18 |
|||
#define PCI_IDSEL_BONITO 19 |
|||
|
|||
/* Define UART baud rate and register layout */ |
|||
#define NS16550_HZ (24000000/13) |
|||
#ifdef __ASSEMBLER__ |
|||
#if #endian(big) |
|||
#define NSREG(x) ((x)^3) |
|||
#else |
|||
#define NSREG(x) (x) |
|||
#endif |
|||
#else |
|||
#define nsreg(x) unsigned char x |
|||
#if #endian(big) |
|||
#define nslayout(r0,r1,r2,r3) nsreg(r3); nsreg(r2); nsreg(r1); nsreg(r0) |
|||
#endif |
|||
#endif |
|||
#define UART0_BASE ISAPORT_BASE(UART0_PORT) |
|||
#define UART1_BASE ISAPORT_BASE(UART1_PORT) |
|||
|
|||
/* Bonito GPIO definitions */ |
|||
#define PIO_PCI_IRQA BONITO_GPIO_IOR(0) /* PCI IRQA */ |
|||
#define PIO_PCI_IRQB BONITO_GPIO_IOR(1) /* PCI IRQB */ |
|||
#define PIO_PCI_IRQC BONITO_GPIO_IOR(2) /* PCI IRQC */ |
|||
#define PIO_PCI_IRQD BONITO_GPIO_IOR(3) /* PCI IRQD */ |
|||
#define PIO_CPLDARB BONITO_GPIO_IOW(4) /* CPLD arbiter */ |
|||
#define PIO_PCIRESET BONITO_GPIO_IOW(5) /* PCI reset */ |
|||
#define PIO_ISA_NMI BONITO_GPIO_IN(0) /* ISA NMI */ |
|||
#define PIO_ISA_IRQ BONITO_GPIO_IN(1) /* ISA IRQ */ |
|||
#define PIO_ETH_IRQ BONITO_GPIO_IN(2) /* Ethernet IRQ */ |
|||
#define PIO_IDE_IRQ BONITO_GPIO_IN(3) /* Bonito IDE IRQ */ |
|||
#define PIO_UART1_IRQ BONITO_GPIO_IN(4) /* ISA IRQ3 */ |
|||
#define PIO_UART0_IRQ BONITO_GPIO_IN(5) /* ISA IRQ4 */ |
|||
|
|||
|
|||
/* ICU masks */ |
|||
#define ICU_PCI_IRQA BONITO_ICU_GPIO(0) |
|||
#define ICU_PCI_IRQB BONITO_ICU_GPIO(1) |
|||
#define ICU_PCI_IRQC BONITO_ICU_GPIO(2) |
|||
#define ICU_PCI_IRQD BONITO_ICU_GPIO(3) |
|||
#define ICU_NMI_IRQ BONITO_ICU_GPIN(0) |
|||
#define ICU_ISA_IRQ BONITO_ICU_GPIN(1) |
|||
#define ICU_ETH_IRQ BONITO_ICU_GPIN(2) |
|||
#define ICU_BIDE_IRQ BONITO_ICU_GPIN(3) |
|||
#define ICU_UART1_IRQ BONITO_ICU_GPIN(4) |
|||
#define ICU_UART0_IRQ BONITO_ICU_GPIN(5) |
|||
#define ICU_DRAMPERR BONITO_ICU_DRAMPERR |
|||
#define ICU_CPUPERR BONITO_ICU_CPUPERR |
|||
#define ICU_IDEDMA BONITO_ICU_IDEDMA |
|||
#define ICU_PCICOPIER BONITO_ICU_PCICOPIER |
|||
#define ICU_POSTEDRD BONITO_ICU_POSTEDRD |
|||
#define ICU_PCIIRQ BONITO_ICU_PCIIRQ |
|||
#define ICU_MASTERERR BONITO_ICU_MASTERERR |
|||
#define ICU_SYSTEMERR BONITO_ICU_SYSTEMERR |
|||
#define ICU_RETRYERR BONITO_ICU_RETRYERR |
|||
#define ICU_MBOXES BONITO_ICU_MBOXES |
|||
|
|||
/* default PIO input enable */ |
|||
#define PIO_IE (~(PIO_CPLDARB|PIO_PCIRESET)) |
|||
|
|||
/* ISA addresses */ |
|||
#define ISAPORT_BASE(x) (PCI_IO_SPACE + (x)) |
|||
#define ISAMEM_BASE(x) (PCI_MEM_SPACE + (x)) |
|||
|
|||
/* ISA i/o ports */ |
|||
#define DMA1_PORT 0x000 |
|||
#define ICU1_PORT 0x020 |
|||
#define CTC_PORT 0x040 |
|||
#define DIAG_PORT 0x061 |
|||
#define RTC_ADDR_PORT 0x070 |
|||
#define RTC_DATA_PORT 0x071 |
|||
#define KEYBD_PORT 0x060 |
|||
#define DMAPAGE_PORT 0x080 |
|||
#define SYSC_PORT 0x092 |
|||
#define ICU2_PORT 0x0a0 |
|||
#define DMA2_PORT 0x0c0 |
|||
#define IDE_PORT 0x1f0 |
|||
#define UART1_PORT 0x2f8 |
|||
#define UART0_PORT 0x3f8 |
|||
#define ECP_PORT 0x378 |
|||
#define CEN_LATCH_PORT 0x37c /* P5064 special */ |
|||
#define FDC_PORT 0x3f0 |
|||
#define SMB_PORT 0x7000 /* Intel convention? */ |
|||
#define GPIO_PORT 0xe000 /* FIXME: where should this go? */ |
|||
#define BMDMA_PORT 0xf000 /* Intel convention? */ |
|||
|
|||
/* ISA interrupt numbers */ |
|||
#define TIMER0_IRQ 0 |
|||
#define KEYBOARD_IRQ 1 |
|||
#define ICU2_IRQ 2 |
|||
#define SERIAL2_IRQ 3 |
|||
#define SERIAL1_IRQ 4 |
|||
#define PARALLEL2_IRQ 5 |
|||
#define FDC_IRQ 6 |
|||
#define PARALLEL1_IRQ 7 |
|||
#define RTC_IRQ 8 |
|||
#define NET_IRQ 9 |
|||
#define MATH_IRQ 13 |
|||
#define IDE_IRQ 14 |
|||
|
|||
|
|||
#define _SBD_FLASHENV 0 /* Store environment in flash #0 */ |
|||
#undef _SBD_RTCENV /* Store environment in RTC */ |
|||
|
|||
#define RTC_HZ 16 |
|||
#define RTC_RATE RTC_RATE_16Hz |
|||
|
|||
#ifndef __ASSEMBLER__ |
|||
|
|||
/* prototypes for board specific functions */ |
|||
|
|||
#if defined(FLASHDEV_OK) |
|||
extern flashcookie_t _sbd_bflashopen (paddr_t); |
|||
extern flashcookie_t _sbd_uflashopen (paddr_t); |
|||
#endif |
|||
/* urgh - find some other way to prototype these functions FIXME */ |
|||
#if defined(__FLASHROM_H__) |
|||
extern int _flash8_probe (struct fromcookie *fcp, unsigned int o); |
|||
extern int _flash16_probe (struct fromcookie *fcp, unsigned int o); |
|||
#endif |
|||
|
|||
#if !defined(PMON) |
|||
extern void _bonito_iobc_wbinv (unsigned int pa, size_t nb); |
|||
extern void _bonito_iobc_inval (unsigned int pa, size_t nb); |
|||
extern void _bonito_clean_dcache (void *va, size_t nb); |
|||
extern void _bonito_inval_dcache (void *va, size_t nb); |
|||
#endif |
|||
|
|||
#endif |
|||
|
|||
#if !defined(__ASSEMBLER__) && !defined(inb) |
|||
/* i/o port access ala 80x86 for ISA bus peripherals */ |
|||
unsigned char inb (unsigned int); |
|||
unsigned short inw (unsigned int); |
|||
unsigned long inl (unsigned int); |
|||
void outb (unsigned int, unsigned char); |
|||
void outw (unsigned int, unsigned short); |
|||
void outl (unsigned int, unsigned long); |
|||
void * ioport_map (unsigned int); |
|||
#endif |
|||
|
|||
/* divert device drivers to Bonito-specific cache cleaning code */ |
|||
#define _sbd_clean_dcache _bonito_clean_dcache |
|||
#define _sbd_inval_dcache _bonito_inval_dcache |
|||
|
|||
#endif /* __SBD_H__ */ |
|||
@ -0,0 +1,48 @@ |
|||
/*
|
|||
* via686b.h: VIA 686B southbridge |
|||
* |
|||
* Copyright (c) 2006, Lemote Ltd. All rights reserved. |
|||
* |
|||
* This program is free software; you can redistribute it and/or modify |
|||
* it under the terms of the GPL License Agreement. |
|||
* |
|||
* You may not, however, modify or remove any part of this copyright |
|||
* message if this program is redistributed or reused in whole or in |
|||
* part. |
|||
* |
|||
* This program is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* GPL License for more details. |
|||
*/ |
|||
|
|||
/*** CONFIG REGISTERS AND VALUES */ |
|||
#define SMBUS_IO_BASE_ADDR 0x90 |
|||
#define SMBUS_IO_BASE_VALUE 0xeee1 |
|||
|
|||
#define SMBUS_HOST_CONFIG_ADDR 0xd2 |
|||
#define SMBUS_HOST_CONFIG_ENABLE_BIT 0x1 |
|||
|
|||
#define SMBUS_HOST_SLAVE_COMMAND 0xd3 |
|||
|
|||
/*** SMBUS IO REGISTERS AND VALUES */ |
|||
#define SMBUS_HOST_STATUS ((SMBUS_IO_BASE_VALUE & 0xfff0) + 0x0) |
|||
#define SMBUS_HOST_STATUS_BUSY 0x1 |
|||
#define SMBUS_HOST_STATUS_INT 0x2 |
|||
#define SMBUS_HOST_STATUS_DEVERR 0x4 |
|||
#define SMBUS_HOST_STATUS_COLLISION 0x8 |
|||
#define SMBUS_HOST_STATUS_FAIL 0x10 |
|||
|
|||
#define SMBUS_HOST_CONTROL ((SMBUS_IO_BASE_VALUE & 0xfff0) + 0x2) |
|||
#define SMBUS_HOST_CONTROL_START 0x40 |
|||
#define SMBUS_HOST_CONTROL_KILL 0x2 |
|||
#define SMBUS_HOST_CONTROL_INTEN 0x1 |
|||
|
|||
#define SMBUS_HOST_COMMAND ((SMBUS_IO_BASE_VALUE & 0xfff0) + 0x3) |
|||
|
|||
#define SMBUS_HOST_ADDRESS ((SMBUS_IO_BASE_VALUE & 0xfff0) + 0x4) |
|||
#define SMBUS_HOST_ADDRESS_READOP 0x1 |
|||
#define SMBUS_HOST_ADDRESS_WRITEOP 0x0 |
|||
|
|||
#define SMBUS_HOST_DATA0 ((SMBUS_IO_BASE_VALUE & 0xfff0) + 0x5) |
|||
#define SMBUS_HOST_DATA1 ((SMBUS_IO_BASE_VALUE & 0xfff0) + 0x6) |
|||
@ -0,0 +1,967 @@ |
|||
#include "rs780_cmn.h" |
|||
#include "amd_780e.h" |
|||
|
|||
#include "rs780_pcie.c" |
|||
#include "rs780_gfx.c" |
|||
#include "rs780.c" |
|||
#include "sb700_usb.c" |
|||
#include "sb700_lpc.c" |
|||
#include "sb700_ide.c" |
|||
#include "sb700_sata.c" |
|||
#include "sb700_sm.c" |
|||
#include "sb700_pci.c" |
|||
//#include "blade_io.h"
|
|||
|
|||
#define INB(addr) (*(volatile unsigned char *) (addr)) |
|||
#define INW(addr) (*(volatile unsigned short *) (addr)) |
|||
#define INL(addr) (*(volatile unsigned int *) (addr)) |
|||
|
|||
#define OUTB(b,addr) (*(volatile unsigned char *) (addr) = (b)) |
|||
#define OUTW(b,addr) (*(volatile unsigned short *) (addr) = (b)) |
|||
#define OUTL(b,addr) (*(volatile unsigned int *) (addr) = (b)) |
|||
|
|||
static u8 get_sb700_revision(void); |
|||
|
|||
void rs780_por_pcicfg_init(device_t nb_tag) |
|||
{ |
|||
printk_info("enter rs780_por_pcicfg_init\n"); |
|||
/* enable PCI Memory Access */ |
|||
set_nbcfg_enable_bits_8(nb_tag, 0x04, (u8)(~0xfd), 0x02); |
|||
/* Set RCRB Enable */ |
|||
set_nbcfg_enable_bits_8(nb_tag, 0x84, (u8)(~0xFF), 0x1); |
|||
|
|||
/* allow decode of 640k-1MB */ |
|||
set_nbcfg_enable_bits_8(nb_tag, 0x84, (u8)(~0xEF), 0x10); |
|||
#if 1 |
|||
/* Enable PM2_CNTL(BAR2) IO mapped cfg write access to be broadcast to both NB and SB */ |
|||
set_nbcfg_enable_bits_8(nb_tag, 0x84, (u8)(~0xFF), 0x4); |
|||
/* Power Management Register Enable */ |
|||
set_nbcfg_enable_bits_8(nb_tag, 0x84, (u8)(~0xFF), 0x80); |
|||
|
|||
/* Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge
|
|||
* Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation |
|||
* BMMsgEn */ |
|||
//set_nbcfg_enable_bits_8(nb_tag, 0x4C, (u8)(~0x00), 0x42 | 1);
|
|||
//lycheng disable APIC_ENABLE
|
|||
set_nbcfg_enable_bits_8(nb_tag, 0x4C, (u8)(~0x00), 0x40 | 1); |
|||
|
|||
/* Reg4Ch[16]=1 (WakeC2En) enable Wake_from_C2 message generation.
|
|||
* Reg4Ch[18]=1 (P4IntEnable) Enable north-bridge to accept MSI with address 0xFEEx_xxxx from south-bridge */ |
|||
//set_nbcfg_enable_bits_8(nb_tag, 0x4E, (u8)(~0xFF), 0x05);
|
|||
//lycheng disable P4IntEnable
|
|||
set_nbcfg_enable_bits_8(nb_tag, 0x4E, (u8)(~0xFF), 0x01); |
|||
#endif |
|||
/* Reg94h[4:0] = 0x0 P drive strength offset 0
|
|||
* Reg94h[6:5] = 0x2 P drive strength additive adjust */ |
|||
set_nbcfg_enable_bits_8(nb_tag, 0x94, (u8)(~0x80), 0x40); |
|||
|
|||
/* Reg94h[20:16] = 0x0 N drive strength offset 0
|
|||
* Reg94h[22:21] = 0x2 N drive strength additive adjust */ |
|||
set_nbcfg_enable_bits_8(nb_tag, 0x96, (u8)(~0x80), 0x40); |
|||
|
|||
/* Reg80h[4:0] = 0x0 Termination offset
|
|||
* Reg80h[6:5] = 0x2 Termination additive adjust */ |
|||
set_nbcfg_enable_bits_8(nb_tag, 0x80, (u8)(~0x80), 0x40); |
|||
|
|||
/* Reg80h[14] = 0x1 Enable receiver termination control */ |
|||
set_nbcfg_enable_bits_8(nb_tag, 0x81, (u8)(~0xFF), 0x40); |
|||
|
|||
/* Reg94h[15] = 0x1 Enables HT transmitter advanced features to be turned on
|
|||
* Reg94h[14] = 0x1 Enable drive strength control */ |
|||
set_nbcfg_enable_bits_8(nb_tag, 0x95, (u8)(~0x3F), 0xC4); |
|||
|
|||
/* Reg94h[31:29] = 0x7 Enables HT transmitter de-emphasis */ |
|||
set_nbcfg_enable_bits_8(nb_tag, 0x97, (u8)(~0x1F), 0xE0); |
|||
|
|||
/*Reg8Ch[10:9] = 0x3 Enables Gfx Debug BAR,
|
|||
* force this BAR as mem type in rs780_gfx.c */ |
|||
set_nbcfg_enable_bits_8(nb_tag, 0x8D, (u8)(~0xFF), 0x03); |
|||
|
|||
printk_info("exit rs780_por_pcicfg_init\n"); |
|||
} |
|||
|
|||
|
|||
/*****************************************
|
|||
* Compliant with CIM_33's ATINB_MCIndex_POR_TABLE |
|||
*****************************************/ |
|||
static void rs780_por_mc_index_init(device_t nb_dev) |
|||
{ |
|||
printk_info("enter rs780_por_mc_index_init\n"); |
|||
set_nbmc_enable_bits(nb_dev, 0x7A, ~0xFFFFFF80, 0x0000005F); |
|||
set_nbmc_enable_bits(nb_dev, 0xD8, ~0x00000000, 0x00600060); |
|||
set_nbmc_enable_bits(nb_dev, 0xD9, ~0x00000000, 0x00600060); |
|||
set_nbmc_enable_bits(nb_dev, 0xE0, ~0x00000000, 0x00000000); |
|||
set_nbmc_enable_bits(nb_dev, 0xE1, ~0x00000000, 0x00000000); |
|||
set_nbmc_enable_bits(nb_dev, 0xE8, ~0x00000000, 0x003E003E); |
|||
set_nbmc_enable_bits(nb_dev, 0xE9, ~0x00000000, 0x003E003E); |
|||
printk_info("exit rs780_por_mc_index_init\n"); |
|||
} |
|||
|
|||
/*****************************************
|
|||
* Compliant with CIM_33's ATINB_MISCIND_POR_TABLE |
|||
* Compliant with CIM_33's MISC_INIT_TBL |
|||
*****************************************/ |
|||
static void rs780_por_misc_index_init(device_t nb_dev) |
|||
{ |
|||
printk_info("enter rs780_por_misc_index_init\n"); |
|||
/* NB_MISC_IND_WR_EN + IOC_PCIE_CNTL
|
|||
* Block non-snoop DMA request if PMArbDis is set. |
|||
* Set BMSetDis */ |
|||
set_nbmisc_enable_bits(nb_dev, 0x0B, ~0xFFFF0000, 0x00000180); |
|||
set_nbmisc_enable_bits(nb_dev, 0x01, ~0xFFFFFFFF, 0x00000040); |
|||
|
|||
/* NBCFG (NBMISCIND 0x0): NB_CNTL -
|
|||
* HIDE_NB_AGP_CAP ([0], default=1)HIDE |
|||
* HIDE_P2P_AGP_CAP ([1], default=1)HIDE |
|||
* HIDE_NB_GART_BAR ([2], default=1)HIDE |
|||
* AGPMODE30 ([4], default=0)DISABLE |
|||
* AGP30ENCHANCED ([5], default=0)DISABLE |
|||
* HIDE_AGP_CAP ([8], default=1)ENABLE */ |
|||
set_nbmisc_enable_bits(nb_dev, 0x00, ~0xFFFF0000, 0x00000506); /* set bit 10 for MSI */ |
|||
//lycheng
|
|||
//set_nbmisc_enable_bits(nb_dev, 0x00, ~0xFFFF0000, 0x00000004); /* set bit 10 for MSI */
|
|||
set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 10, 1 << 10); //added by oldtai
|
|||
set_nbmisc_enable_bits(nb_dev, 0x01, 1 << 8, 1 << 8); //added by oldtai
|
|||
|
|||
|
|||
/* NBMISCIND:0x6A[16]= 1 SB link can get a full swing
|
|||
* set_nbmisc_enable_bits(nb_dev, 0x6A, 0ffffffffh, 000010000); |
|||
* NBMISCIND:0x6A[17]=1 Set CMGOOD_OVERRIDE. */ |
|||
set_nbmisc_enable_bits(nb_dev, 0x6A, ~0xffffffff, 0x00020000); |
|||
|
|||
/* NBMISIND:0x40 Bit[8]=1 and Bit[10]=1 following bits are required to set in order to allow LVDS or PWM features to work. */ |
|||
set_nbmisc_enable_bits(nb_dev, 0x40, ~0xffffffff, 0x00000500); |
|||
|
|||
/* NBMISIND:0xC Bit[13]=1 Enable GSM mode for C1e or C3 with pop-up. */ |
|||
set_nbmisc_enable_bits(nb_dev, 0x0C, ~0xffffffff, 0x00002000); |
|||
|
|||
/* Set NBMISIND:0x1F[3] to map NB F2 interrupt pin to INTB# */ |
|||
set_nbmisc_enable_bits(nb_dev, 0x1F, ~0xffffffff, 0x00000008); |
|||
|
|||
/* Compliant with CIM_33's MISC_INIT_TBL, except Hide NB_BAR3_PCIE
|
|||
* Enable access to DEV8 |
|||
* Enable setPower message for all ports |
|||
*/ |
|||
set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, 1 << 6); |
|||
set_nbmisc_enable_bits(nb_dev, 0x0b, 1 << 20, 1 << 20); |
|||
set_nbmisc_enable_bits(nb_dev, 0x51, 1 << 20, 1 << 20); |
|||
set_nbmisc_enable_bits(nb_dev, 0x53, 1 << 20, 1 << 20); |
|||
set_nbmisc_enable_bits(nb_dev, 0x55, 1 << 20, 1 << 20); |
|||
set_nbmisc_enable_bits(nb_dev, 0x57, 1 << 20, 1 << 20); |
|||
set_nbmisc_enable_bits(nb_dev, 0x59, 1 << 20, 1 << 20); |
|||
set_nbmisc_enable_bits(nb_dev, 0x5B, 1 << 20, 1 << 20); |
|||
//VGA lycheng
|
|||
set_nbmisc_enable_bits(nb_dev, 0x5D, 1 << 20, 1 << 20); |
|||
set_nbmisc_enable_bits(nb_dev, 0x5F, 1 << 20, 1 << 20); |
|||
|
|||
set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 7, 1 << 7); |
|||
set_nbmisc_enable_bits(nb_dev, 0x07, 0x000000f0, 0x30); |
|||
/* Disable bus-master trigger event from SB and Enable set_slot_power message to SB */ |
|||
set_nbmisc_enable_bits(nb_dev, 0x0B, 0xffffffff, 0x500180); |
|||
printk_info("exit rs780_por_misc_index_init\n"); |
|||
} |
|||
|
|||
/*****************************************
|
|||
* Compliant with CIM_33's ATINB_HTIUNBIND_POR_TABLE |
|||
*****************************************/ |
|||
static void rs780_por_htiu_index_init(device_t nb_dev) |
|||
{ |
|||
printk_info("enter rs780_por_htiu_index_init\n"); |
|||
//vga lycheng
|
|||
set_htiu_enable_bits(nb_dev, 0x05, (1<<10|1<<9), 1<<10 | 1<<9); |
|||
set_htiu_enable_bits(nb_dev, 0x06, ~0xFFFFFFFE, 0x04203A202); |
|||
|
|||
set_htiu_enable_bits(nb_dev, 0x07, ~0xFFFFFFF9, 0x8001/* | 7 << 8 */); /* fam 10 */ |
|||
|
|||
set_htiu_enable_bits(nb_dev, 0x15, ~0xFFFFFFFF, 1<<31| 1<<30 | 1<<27); |
|||
set_htiu_enable_bits(nb_dev, 0x1C, ~0xFFFFFFFF, 0xFFFE0000); |
|||
|
|||
set_htiu_enable_bits(nb_dev, 0x4B, (1<<11), 1<<11); |
|||
|
|||
set_htiu_enable_bits(nb_dev, 0x0C, ~0xFFFFFFC0, 1<<0|1<<3); |
|||
|
|||
set_htiu_enable_bits(nb_dev, 0x17, (1<<27|1<<1), 0x1<<1); |
|||
set_htiu_enable_bits(nb_dev, 0x17, 0x1 << 30, 0x1<<30); |
|||
|
|||
set_htiu_enable_bits(nb_dev, 0x19, (0xFFFFF+(1<<31)), 0x186A0+(1<<31)); |
|||
|
|||
set_htiu_enable_bits(nb_dev, 0x16, (0x3F<<10), 0x7<<10); |
|||
|
|||
set_htiu_enable_bits(nb_dev, 0x23, 0xFFFFFFF, 1<<28); |
|||
|
|||
set_htiu_enable_bits(nb_dev, 0x1E, 0xFFFFFFFF, 0xFFFFFFFF); |
|||
|
|||
/* here we set lower of top of dram2 to 0x0 and enabled*/ |
|||
printk_info("before lower tom2 is %x, upper tom2 %x\n", |
|||
htiu_read_indexN(nb_dev, 0x30), |
|||
htiu_read_indexN(nb_dev, 0x31)); |
|||
|
|||
htiu_write_indexN(nb_dev, 0x30, 0x01); |
|||
htiu_write_indexN(nb_dev, 0x31, 0x80); |
|||
|
|||
|
|||
/* here we set upper of top of dram2 to 0x0 and enabled, so the top
|
|||
* of dram 2 is 0x80 0000 0000 = 512GB*/ |
|||
printk_info("lower tom2 is %x, upper tom2 %x\n", |
|||
htiu_read_indexN(nb_dev, 0x30), |
|||
htiu_read_indexN(nb_dev, 0x31)); |
|||
|
|||
|
|||
printk_info("exit rs780_por_htiu_index_init\n"); |
|||
} |
|||
|
|||
|
|||
|
|||
void rs780_por_init(device_t nb_tag) |
|||
{ |
|||
/* ATINB_PCICFG_POR_TABLE, initialize the values for rs780 PCI Config registers */ |
|||
rs780_por_pcicfg_init(nb_tag); |
|||
/* ATINB_MCIND_POR_TABLE */ |
|||
rs780_por_mc_index_init(nb_tag); |
|||
|
|||
/* ATINB_MISCIND_POR_TABLE */ |
|||
rs780_por_misc_index_init(nb_tag); |
|||
|
|||
/* ATINB_HTIUNBIND_POR_TABLE */ |
|||
rs780_por_htiu_index_init(nb_tag); |
|||
|
|||
/* ATINB_CLKCFG_PORT_TABLE */ |
|||
/* rs780 A11 SB Link full swing? */ |
|||
} |
|||
|
|||
|
|||
void rs780_early_setup(void) |
|||
{ |
|||
device_t nb_tag; |
|||
nb_tag = _pci_make_tag(0, 0, 0); |
|||
rs780_por_init(nb_tag); |
|||
} |
|||
|
|||
|
|||
#define SMBUS_IO_BASE 0x1000 //ynn
|
|||
|
|||
/* sbDevicesPorInitTable */ |
|||
void sb700_devices_por_init(void) |
|||
{ |
|||
device_t dev; |
|||
u8 byte; |
|||
|
|||
/* SMBus Device, BDF:0-20-0 */ |
|||
|
|||
dev = _pci_make_tag(0, 20, 0); |
|||
|
|||
/* sbPorAtStartOfTblCfg */ |
|||
/* Set A-Link bridge access address. This address is set at device 14h, function 0, register 0xf0.
|
|||
* This is an I/O address. The I/O address must be on 16-byte boundry. */ |
|||
printk_info("set a-link bridge access address\n"); |
|||
//pci_write_config32(dev, 0xf0, AB_INDX);
|
|||
pci_write_config32(dev, 0xf0, 0x00000cd8); |
|||
|
|||
/* To enable AB/BIF DMA access, a specific register inside the BIF register space needs to be configured first. */ |
|||
/*Enables the SB600 to send transactions upstream over A-Link Express interface. */ |
|||
printk_info("To enable ab bif dam access\n"); |
|||
axcfg_reg(0x04, 1 << 2, 1 << 2); |
|||
axindxc_reg(0x21, 0xff, 0); |
|||
|
|||
/* 2.3.5:Enabling Non-Posted Memory Write for the K8 Platform */ |
|||
printk_info("Enabling Non-Posted Memory Write for the K8 Platform\n"); |
|||
axindxc_reg(0x10, 1 << 9, 1 << 9); |
|||
/* END of sbPorAtStartOfTblCfg */ |
|||
|
|||
/* sbDevicesPorInitTables */ |
|||
/* set smbus iobase */ |
|||
printk_info("set smbus iobase\n"); |
|||
//pci_write_config32(dev, 0x10, SMBUS_IO_BASE | 1);
|
|||
//vga lycheng
|
|||
pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1); |
|||
|
|||
/* enable smbus controller interface */ |
|||
printk_info("enable smbus controller interface\n"); |
|||
byte = pci_read_config8(dev, 0xd2); |
|||
byte |= (1 << 0); |
|||
pci_write_config8(dev, 0xd2, byte); |
|||
|
|||
#if 0 |
|||
/* set smbus 1, ASF 2.0 (Alert Standard Format), iobase */ |
|||
printk_info("enable smbus 1, ASF 2.0\n"); |
|||
pci_write_config16(dev, 0x58, SMBUS_IO_BASE | 0x11); |
|||
#endif |
|||
/* TODO: I don't know the useage of followed two lines. I copied them from CIM. */ |
|||
pci_write_config8(dev, 0x0a, 0x1); |
|||
pci_write_config8(dev, 0x0b, 0x6); |
|||
|
|||
/* KB2RstEnable */ |
|||
printk_info("KB2RstEnable\n"); |
|||
pci_write_config8(dev, 0x40, 0xd4); |
|||
|
|||
/* Enable ISA Address 0-960K decoding */ |
|||
printk_info("Enable ISA address decoding\n"); |
|||
pci_write_config8(dev, 0x48, 0x0f); |
|||
|
|||
/* Enable ISA Address 0xC0000-0xDFFFF decode */ |
|||
printk_info("Enable ISA address 0xc0000-0xdffff decode\n"); |
|||
pci_write_config8(dev, 0x49, 0xff); |
|||
|
|||
/* Enable decode cycles to IO C50, C51, C52 GPM controls. */ |
|||
printk_info("Enable decode cycles to IO controls\n"); |
|||
byte = pci_read_config8(dev, 0x41); |
|||
byte &= 0x80; |
|||
byte |= 0x33; |
|||
pci_write_config8(dev, 0x41, byte); |
|||
|
|||
/* Legacy DMA Prefetch Enhancement, CIM masked it. */ |
|||
/* pci_write_config8(dev, 0x43, 0x1); */ |
|||
|
|||
/* Disabling Legacy USB Fast SMI# */ |
|||
printk_info("Disabling Legacy USB Fast SMI\n"); |
|||
byte = pci_read_config8(dev, 0x62); |
|||
byte |= 0x24; |
|||
pci_write_config8(dev, 0x62, byte); |
|||
|
|||
/* Features Enable */ |
|||
printk_info("Features Enable\n"); |
|||
pci_write_config32(dev, 0x64, 0x829E7DBF); /* bit10: Enables the HPET interrupt. */ |
|||
|
|||
/* SerialIrq Control */ |
|||
printk_info("SerialIrq Control\n"); |
|||
pci_write_config8(dev, 0x69, 0x90); |
|||
|
|||
/* Test Mode, PCIB_SReset_En Mask is set. */ |
|||
pci_write_config8(dev, 0x6c, 0x20); |
|||
|
|||
/* IO Address Enable, CIM set 0x78 only and masked 0x79. */ |
|||
printk_info("IO Address Enable\n"); |
|||
/*pci_write_config8(dev, 0x79, 0x4F); */ |
|||
pci_write_config8(dev, 0x78, 0xFF); |
|||
//#ifndef ENABLE_SATA
|
|||
#if 1 |
|||
/* TODO: set ide as primary, if you want to boot from IDE, you'd better set it.Or add a configuration line.*/ |
|||
printk_info("set ide as primary\n"); |
|||
byte = pci_read_config8(dev, 0xAD); |
|||
byte |= 0x1<<3; |
|||
byte &= ~(0x1<<4); |
|||
pci_write_config8(dev, 0xAD, byte); |
|||
|
|||
/* This register is not used on sb700. It came from older chipset. */ |
|||
/*pci_write_config8(dev, 0x95, 0xFF); */ |
|||
#endif |
|||
|
|||
/* Set smbus iospace enable, I don't know why write 0x04 into reg5 that is reserved */ |
|||
printk_info("Set smbus iospace enable\n"); |
|||
pci_write_config16(dev, 0x4, 0x0407); |
|||
#if 1 |
|||
/* clear any lingering errors, so the transaction will run */ |
|||
printk_info("IO Address Enable\n"); |
|||
//OUTB(INB(0xba000000 + SMBUS_IO_BASE + SMBHSTSTAT), 0xba000000 + SMBUS_IO_BASE + SMBHSTSTAT);
|
|||
OUTB(INB(BONITO_PCIIO_BASE_VA + SMBUS_IO_BASE + SMBHSTSTAT), BONITO_PCIIO_BASE_VA + SMBUS_IO_BASE + SMBHSTSTAT); |
|||
#endif |
|||
/* IDE Device, BDF:0-20-1 */ |
|||
printk_info("sb700_devices_por_init(): IDE Device, BDF:0-20-1\n"); |
|||
//dev = pci_locate_device(PCI_ID(0x1002, 0x438C), 0);
|
|||
|
|||
dev = _pci_make_tag(0, 20, 1); |
|||
/* Disable prefetch */ |
|||
printk_info("Disable prefetch\n"); |
|||
byte = pci_read_config8(dev, 0x63); |
|||
byte |= 0x1; |
|||
pci_write_config8(dev, 0x63, byte); |
|||
|
|||
/* LPC Device, BDF:0-20-3 */ |
|||
printk_info("sb700_devices_por_init(): LPC Device, BDF:0-20-3\n"); |
|||
//dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
|
|||
dev = _pci_make_tag(0, 20, 3); |
|||
/* DMA enable */ |
|||
printk_info("DMA enable\n"); |
|||
pci_write_config8(dev, 0x40, 0x04); |
|||
|
|||
/* IO Port Decode Enable */ |
|||
printk_info("IO Port Decode Enable\n"); |
|||
pci_write_config8(dev, 0x44, 0xFF); |
|||
pci_write_config8(dev, 0x45, 0xFF); |
|||
pci_write_config8(dev, 0x46, 0xC3); |
|||
pci_write_config8(dev, 0x47, 0xFF); |
|||
|
|||
/* IO/Mem Port Decode Enable, I don't know why CIM disable some ports.
|
|||
* Disable LPC TimeOut counter, enable SuperIO Configuration Port (2e/2f), |
|||
* Alternate SuperIO Configuration Port (4e/4f), Wide Generic IO Port (64/65). |
|||
* Enable bits for LPC ROM memory address range 1&2 for 1M ROM setting.*/ |
|||
printk_info("IO/Mem Port Decode Enable\n"); |
|||
byte = pci_read_config8(dev, 0x48); |
|||
byte |= (1 << 1) | (1 << 0); /* enable Super IO config port 2e-2h, 4e-4f */ |
|||
byte |= (1 << 3) | (1 << 4); /* enable for LPC ROM address range1&2, Enable 512KB rom access at 0xFFF80000 - 0xFFFFFFFF */ |
|||
byte |= 1 << 6; /* enable for RTC I/O range */ |
|||
pci_write_config8(dev, 0x48, byte); |
|||
pci_write_config8(dev, 0x49, 0xFF); |
|||
/* Enable 0x480-0x4bf, 0x4700-0x470B */ |
|||
byte = pci_read_config8(dev, 0x4A); |
|||
byte |= ((1 << 1) + (1 << 6)); /*0x42, save the configuraion for port 0x80. */ |
|||
pci_write_config8(dev, 0x4A, byte); |
|||
|
|||
/* Set LPC ROM size, it has been done in sb700_lpc_init().
|
|||
* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB; |
|||
* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB |
|||
* pci_write_config16(dev, 0x68, 0x000e) |
|||
* pci_write_config16(dev, 0x6c, 0xfff0);*/ |
|||
|
|||
/* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */ |
|||
printk_info("Enable Tpm12_en and Tpm_legacy\n"); |
|||
pci_write_config8(dev, 0x7C, 0x05); |
|||
|
|||
/* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM,
|
|||
* TODO: I don't know what are their mean? */ |
|||
printk_info("sb700_devices_por_init(): P2P Bridge, BDF:0-20-4\n"); |
|||
//dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
|
|||
dev = _pci_make_tag(0, 20, 4); |
|||
/* I don't know why CIM tried to write into a read-only reg! */ |
|||
/*pci_write_config8(dev, 0x0c, 0x20) */ ; |
|||
|
|||
/* Arbiter enable. */ |
|||
printk_info("Arbiter enable\n"); |
|||
pci_write_config8(dev, 0x43, 0xff); |
|||
|
|||
/* Set PCDMA request into hight priority list. */ |
|||
/* pci_write_config8(dev, 0x49, 0x1) */ ; |
|||
|
|||
pci_write_config8(dev, 0x40, 0x26); |
|||
|
|||
/* I don't know why CIM set reg0x1c as 0x11.
|
|||
* System will block at sdram_initialize() if I set it before call sdram_initialize(). |
|||
* If it is necessary to set reg0x1c as 0x11, please call this function after sdram_initialize(). |
|||
* pci_write_config8(dev, 0x1c, 0x11); |
|||
* pci_write_config8(dev, 0x1d, 0x11);*/ |
|||
|
|||
/*CIM set this register; but I didn't find its description in RPR.
|
|||
On DBM690T platform, I didn't find different between set and skip this register. |
|||
But on Filbert platform, the DEBUG message from serial port on Peanut board can't be displayed |
|||
after the bit0 of this register is set. |
|||
pci_write_config8(dev, 0x04, 0x21); |
|||
*/ |
|||
printk_info("CIM set this register\n"); |
|||
pci_write_config8(dev, 0x0d, 0x40); |
|||
pci_write_config8(dev, 0x1b, 0x40); |
|||
/* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */ |
|||
printk_info("enable pcib_dual_en_up\n"); |
|||
pci_write_config8(dev, 0x50, 0x01); |
|||
#ifdef ENABLE_SATA |
|||
/* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */ |
|||
printk_info("sb700_devices_por_init(): SATA Device, BDF:0-17-0\n"); |
|||
//dev = pci_locate_device(PCI_ID(0x1002, 0x4380), 0);
|
|||
dev = _pci_make_tag(0, 17, 0); |
|||
/*PHY Global Control, we are using A14.
|
|||
* default: 0x2c40 for ASIC revision A12 and below |
|||
* 0x2c00 for ASIC revision A13 and above.*/ |
|||
printk_info("PHY Global Control\n"); |
|||
pci_write_config16(dev, 0x86, 0x2C00); |
|||
#endif |
|||
} |
|||
static void pmio_write(u8 reg, u8 value) |
|||
{ |
|||
OUTB(reg, PM_INDEX); |
|||
OUTB(value, PM_INDEX + 1); |
|||
} |
|||
|
|||
static u8 pmio_read(u8 reg) |
|||
{ |
|||
OUTB(reg, PM_INDEX); |
|||
return INB(PM_INDEX + 1); |
|||
} |
|||
void sb700_pmio_por_init(void) |
|||
{ |
|||
u8 byte; |
|||
|
|||
#if 1 |
|||
printk_info("sb700_pmio_por_init()\n"); |
|||
/* K8KbRstEn, KB_RST# control for K8 system. */ |
|||
byte = pmio_read(0x66); |
|||
byte |= 0x20; |
|||
pmio_write(0x66, byte); |
|||
|
|||
/* RPR2.31 PM_TURN_OFF_MSG during ASF Shutdown. */ |
|||
if (get_sb700_revision() <= 0x12) { |
|||
byte = pmio_read(0x65); |
|||
byte &= ~(1 << 7); |
|||
pmio_write(0x65, byte); |
|||
|
|||
byte = pmio_read(0x75); |
|||
byte &= 0xc0; |
|||
byte |= 0x05; |
|||
pmio_write(0x75, byte); |
|||
|
|||
byte = pmio_read(0x52); |
|||
byte &= 0xc0; |
|||
byte |= 0x08; |
|||
pmio_write(0x52, byte); |
|||
} else { |
|||
byte = pmio_read(0xD7); |
|||
byte |= 1 << 0; |
|||
pmio_write(0xD7, byte); |
|||
|
|||
byte = pmio_read(0x65); |
|||
byte |= 1 << 7; |
|||
pmio_write(0x65, byte); |
|||
|
|||
byte = pmio_read(0x75); |
|||
byte &= 0xc0; |
|||
byte |= 0x01; |
|||
pmio_write(0x75, byte); |
|||
|
|||
byte = pmio_read(0x52); |
|||
byte &= 0xc0; |
|||
byte |= 0x02; |
|||
pmio_write(0x52, byte); |
|||
|
|||
} |
|||
|
|||
pmio_write(0x6c, 0xf0); |
|||
pmio_write(0x6d, 0x00); |
|||
pmio_write(0x6e, 0xc0); |
|||
pmio_write(0x6f, 0xfe); |
|||
|
|||
/* rpr2.19: Enabling Spread Spectrum */ |
|||
printk_info("Enabling Spread Spectrum\n"); |
|||
byte = pmio_read(0x42); |
|||
byte |= 1 << 7; |
|||
pmio_write(0x42, byte); |
|||
/* TODO: Check if it is necessary. IDE reset */ |
|||
byte = pmio_read(0xB2); |
|||
byte |= 1 << 0; |
|||
pmio_write(0xB2, byte); |
|||
#endif |
|||
} |
|||
|
|||
|
|||
/*
|
|||
* Compliant with CIM_48's ATSBPowerOnResetInitJSP |
|||
*/ |
|||
void sb700_por_init(void) |
|||
{ |
|||
/* sbDevicesPorInitTable + sbK8PorInitTable */ |
|||
sb700_devices_por_init(); |
|||
|
|||
/* sbPmioPorInitTable + sbK8PmioPorInitTable */ |
|||
sb700_pmio_por_init(); |
|||
} |
|||
|
|||
void sb700_early_setup(void) |
|||
{ |
|||
sb700_por_init(); |
|||
} |
|||
|
|||
int optimize_link_incoherent_ht(void) |
|||
{ |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
void soft_reset(void) |
|||
{ |
|||
|
|||
} |
|||
|
|||
void rs780_before_pci_fixup(void) |
|||
{ |
|||
|
|||
} |
|||
|
|||
/* Get SB ASIC Revision.*/ |
|||
static u8 get_sb700_revision(void) |
|||
{ |
|||
device_t dev; |
|||
//dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
|
|||
dev = _pci_make_tag(0, 20, 0); |
|||
return pci_read_config8(dev, 0x08); |
|||
} |
|||
|
|||
|
|||
/*
|
|||
* Compliant with CIM_48's sbPciCfg. |
|||
* Add any south bridge setting. |
|||
*/ |
|||
static void sb700_pci_cfg() |
|||
{ |
|||
device_t dev; |
|||
u8 byte; |
|||
|
|||
/* SMBus Device, BDF:0-20-0 */ |
|||
//dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
|
|||
dev = _pci_make_tag(0, 20, 0); |
|||
|
|||
#if 1 |
|||
/* Enable watchdog decode timer */ |
|||
printk_info("enable watchdog decode timer\n"); |
|||
byte = pci_read_config8(dev, 0x41); |
|||
byte |= (1 << 3); |
|||
pci_write_config8(dev, 0x41, byte); |
|||
/* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles)
|
|||
* generated PCIRST#. */ |
|||
byte = pmio_read(0x65); |
|||
byte |= (1 << 4); |
|||
pmio_write(0x65, byte); |
|||
#endif |
|||
/* IDE Device, BDF:0-20-1 */ |
|||
//dev = pci_locate_device(PCI_ID(0x1002, 0x438C), 0);
|
|||
dev = _pci_make_tag(0, 20, 1); |
|||
/* Enable IDE Explicit prefetch, 0x63[0] clear */ |
|||
printk_info("enable IDE explicit prefetch\n"); |
|||
byte = pci_read_config8(dev, 0x63); |
|||
byte &= 0xfe; |
|||
pci_write_config8(dev, 0x63, byte); |
|||
|
|||
/* LPC Device, BDF:0-20-3 */ |
|||
//dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
|
|||
dev = _pci_make_tag(0, 20, 3); |
|||
/* rpr7.2 Enabling LPC DMA function. */ |
|||
printk_info("enabling lpc dma function\n"); |
|||
byte = pci_read_config8(dev, 0x40); |
|||
byte |= (1 << 2); |
|||
pci_write_config8(dev, 0x40, byte); |
|||
/* rpr7.3 Disabling LPC TimeOut. 0x48[7] clear. */ |
|||
printk_info("disable lpc timeout\n"); |
|||
byte = pci_read_config8(dev, 0x48); |
|||
byte &= 0x7f; |
|||
pci_write_config8(dev, 0x48, byte); |
|||
/* rpr7.5 Disabling LPC MSI Capability, 0x78[1] clear. */ |
|||
printk_info("disable LPC MSI Capability\n"); |
|||
byte = pci_read_config8(dev, 0x78); |
|||
byte &= 0xfd; |
|||
pci_write_config8(dev, 0x78, byte); |
|||
#ifdef ENABLE_SATA |
|||
/* SATA Device, BDF:0-18-0, Non-Raid-5 SATA controller */ |
|||
//dev = pci_locate_device(PCI_ID(0x1002, 0x4380), 0);
|
|||
dev = _pci_make_tag(0, 17, 0); |
|||
/* rpr7.12 SATA MSI and D3 Power State Capability.
|
|||
* TODO: We assume S1 is supported. What if it isn't support? */ |
|||
byte = pci_read_config8(dev, 0x40); |
|||
byte |= 1 << 0; |
|||
pci_write_config8(dev, 0x40, byte); |
|||
if (get_sb700_revision() <= 0x12) |
|||
pci_write_config8(dev, 0x34, 0x70); |
|||
else |
|||
pci_write_config8(dev, 0x34, 0x50); |
|||
byte &= ~(1 << 0); |
|||
pci_write_config8(dev, 0x40, byte); |
|||
#endif |
|||
/* TODO: There are several pairs of USB devices.
|
|||
* Two 4396s, two 4397s, two 4398s. |
|||
* The code below only set one of each two. The other |
|||
* will be done in sb700_usb.c after all. |
|||
* So we don't take the trouble to set them both. */ |
|||
/* EHCI Device, BDF:0-19-2, ehci usb controller */ |
|||
//dev = pci_locate_device(PCI_ID(0x1002, 0x4396), 0);
|
|||
dev = _pci_make_tag(0, 19, 2); |
|||
/* rpr6.16 Disabling USB EHCI MSI Capability. 0x50[6]. */ |
|||
byte = pci_read_config8(dev, 0x50); |
|||
byte |= (1 << 6); |
|||
pci_write_config8(dev, 0x50, byte); |
|||
|
|||
//lycheng add disabling usb ohci and ehci msi capability
|
|||
|
|||
/* EHCI Device, BDF:0-18-2, ehci usb controller */ |
|||
//dev = pci_locate_device(PCI_ID(0x1002, 0x4396), 0);
|
|||
dev = _pci_make_tag(0, 18, 2); |
|||
/* rpr6.16 Disabling USB EHCI MSI Capability. 0x50[6]. */ |
|||
byte = pci_read_config8(dev, 0x50); |
|||
byte |= (1 << 6); |
|||
pci_write_config8(dev, 0x50, byte); |
|||
|
|||
|
|||
/* OHCI0 Device, BDF:0-19-0, ohci usb controller #0 */ |
|||
//dev = pci_locate_device(PCI_ID(0x1002, 0x4387), 0);
|
|||
dev = _pci_make_tag(0, 19, 0); |
|||
/* rpr5.11 Disabling USB OHCI MSI Capability. 0x40[12:8]=0x1f. */ |
|||
printk_info("disable USB OHCI MSI Capability\n"); |
|||
byte = pci_read_config8(dev, 0x41); |
|||
byte |= 0x3; |
|||
pci_write_config8(dev, 0x41, byte); |
|||
|
|||
dev = _pci_make_tag(0, 18, 0); |
|||
/* rpr5.11 Disabling USB OHCI MSI Capability. 0x40[12:8]=0x1f. */ |
|||
printk_info("disable USB OHCI MSI Capability\n"); |
|||
byte = pci_read_config8(dev, 0x41); |
|||
byte |= 0x3; |
|||
pci_write_config8(dev, 0x41, byte); |
|||
|
|||
|
|||
/* OHCI0 Device, BDF:0-19-1, ohci usb controller #0 */ |
|||
//dev = pci_locate_device(PCI_ID(0x1002, 0x4398), 0);
|
|||
dev = _pci_make_tag(0, 19, 1); |
|||
byte = pci_read_config8(dev, 0x41); |
|||
byte |= 0x3; |
|||
pci_write_config8(dev, 0x41, byte); |
|||
|
|||
dev = _pci_make_tag(0, 18, 1); |
|||
byte = pci_read_config8(dev, 0x41); |
|||
byte |= 0x3; |
|||
pci_write_config8(dev, 0x41, byte); |
|||
|
|||
|
|||
/* OHCI0 Device, BDF:0-20-5, ohci usb controller #0 */ |
|||
//dev = pci_locate_device(PCI_ID(0x1002, 0x4399), 0);
|
|||
dev = _pci_make_tag(0, 20, 5); |
|||
byte = pci_read_config8(dev, 0x41); |
|||
byte |= 0x3; |
|||
pci_write_config8(dev, 0x41, byte); |
|||
} |
|||
|
|||
void sb700_before_pci_fixup(void){ |
|||
sb700_pci_cfg(); |
|||
} |
|||
|
|||
|
|||
|
|||
/***********************************************
|
|||
* 0:00.0 NBCFG : |
|||
* 0:00.1 CLK : bit 0 of nb_cfg 0x4c : 0 - disable, default |
|||
* 0:01.0 P2P Internal: |
|||
* 0:02.0 P2P : bit 2 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 |
|||
* 0:03.0 P2P : bit 3 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 |
|||
* 0:04.0 P2P : bit 4 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 |
|||
* 0:05.0 P2P : bit 5 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 |
|||
* 0:06.0 P2P : bit 6 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 |
|||
* 0:07.0 P2P : bit 7 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 |
|||
* 0:08.0 NB2SB : bit 6 of nbmiscind 0x00 : 0 - disable, default + 32 * 1 |
|||
* case 0 will be called twice, one is by cpu in hypertransport.c line458, |
|||
* the other is by rs780. |
|||
***********************************************/ |
|||
|
|||
void rs780_enable(device_t dev) |
|||
{ |
|||
device_t nb_dev, sb_dev; |
|||
int dev_ind; |
|||
|
|||
nb_dev = _pci_make_tag(0, 0, 0); |
|||
sb_dev = _pci_make_tag(0, 8, 0); |
|||
|
|||
_pci_break_tag(dev, NULL, &dev_ind, NULL); |
|||
|
|||
switch(dev_ind){ |
|||
case 0: |
|||
printk_info("enable_pcie_bar3\n"); |
|||
enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ |
|||
printk_info("config_gpp_core\n"); |
|||
config_gpp_core(nb_dev, sb_dev); |
|||
printk_info("rs780_gpp_sb_init\n"); |
|||
rs780_gpp_sb_init(nb_dev, sb_dev, 8); |
|||
/* set SB payload size: 64byte */ |
|||
printk_info("set sb payload size:64byte\n"); |
|||
set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPPSB, 3 << 11, 2 << 11); |
|||
|
|||
/* Bus0Dev0Fun1Clock control init, we have to do it here, for dev0 Fun1 doesn't have a vendor or device ID */ |
|||
//rs780_config_misc_clk(nb_dev);
|
|||
{ /* BTDC: NBPOR_InitPOR function. */ |
|||
u8 temp8; |
|||
u16 temp16; |
|||
u32 temp32; |
|||
|
|||
/* BTDC: Program NB PCI table. */ |
|||
printk_info("Program NB PCI table\n"); |
|||
temp16 = pci_read_config16(nb_dev, 0x04); |
|||
printk_debug("BTDC: NB_PCI_REG04 = %x.\n", temp16); |
|||
temp32 = pci_read_config32(nb_dev, 0x84); |
|||
printk_debug("BTDC: NB_PCI_REG84 = %x.\n", temp32); |
|||
|
|||
pci_write_config8(nb_dev, 0x4c, 0x42); |
|||
temp8 = pci_read_config8(nb_dev, 0x4e); |
|||
temp8 |= 0x05; |
|||
pci_write_config8(nb_dev, 0x4e, temp8); |
|||
temp32 = pci_read_config32(nb_dev, 0x4c); |
|||
printk_debug("BTDC: NB_PCI_REG4C = %x.\n", temp32); |
|||
/* BTDC: disable GFX debug. */ |
|||
printk_info("disable gfx debug\n"); |
|||
temp8 = pci_read_config8(nb_dev, 0x8d); |
|||
temp8 &= ~(1<<1); |
|||
pci_write_config8(nb_dev, 0x8d, temp8); |
|||
/* BTDC: set temporary NB TOM to 0x40000000. */ |
|||
//printk_info("set temporary NB TOM to 0xf0000000\n");
|
|||
//pci_write_config32(nb_dev, 0x90, 0x40000000);
|
|||
//pci_write_config32(nb_dev, 0x90, 0xf0000000);
|
|||
printk_info("set temporary NB TOM to 0xffffffff\n"); |
|||
pci_write_config32(nb_dev, 0x90, 0xffffffff); |
|||
/* BTDC: Program NB HTIU table. */ |
|||
printk_info("Program NB HTIU table\n"); |
|||
set_htiu_enable_bits(nb_dev, 0x05, 1<<10 | 1<<9, 1<<10|1<<9); |
|||
set_htiu_enable_bits(nb_dev, 0x06, 1, 0x4203a202); |
|||
set_htiu_enable_bits(nb_dev, 0x07, 1<<1 | 1<<2, 0x8001); |
|||
set_htiu_enable_bits(nb_dev, 0x15, 0, 1<<31 | 1<<30 | 1<<27); |
|||
set_htiu_enable_bits(nb_dev, 0x1c, 0, 0xfffe0000); |
|||
set_htiu_enable_bits(nb_dev, 0x4b, 1<<11, 1<<11); |
|||
set_htiu_enable_bits(nb_dev, 0x0c, 0x3f, 1 | 1<<3); |
|||
set_htiu_enable_bits(nb_dev, 0x17, 1<<1 | 1<<27, 1<<1); |
|||
set_htiu_enable_bits(nb_dev, 0x17, 0, 1<<30); |
|||
set_htiu_enable_bits(nb_dev, 0x19, 0xfffff+(1<<31), 0x186a0+(1<<31)); |
|||
set_htiu_enable_bits(nb_dev, 0x16, 0x3f<<10, 0x7<<10); |
|||
set_htiu_enable_bits(nb_dev, 0x23, 0, 1<<28); |
|||
/* BTDC: Program NB MISC table. */ |
|||
printk_info("set NB MISC table\n"); |
|||
set_nbmisc_enable_bits(nb_dev, 0x0b, 0xffff, 0x00000180); |
|||
set_nbmisc_enable_bits(nb_dev, 0x00, 0xffff, 0x00000106); |
|||
set_nbmisc_enable_bits(nb_dev, 0x51, 0xffffffff, 0x00100100); |
|||
set_nbmisc_enable_bits(nb_dev, 0x53, 0xffffffff, 0x00100100); |
|||
set_nbmisc_enable_bits(nb_dev, 0x55, 0xffffffff, 0x00100100); |
|||
set_nbmisc_enable_bits(nb_dev, 0x57, 0xffffffff, 0x00100100); |
|||
set_nbmisc_enable_bits(nb_dev, 0x59, 0xffffffff, 0x00100100); |
|||
set_nbmisc_enable_bits(nb_dev, 0x5b, 0xffffffff, 0x00100100); |
|||
set_nbmisc_enable_bits(nb_dev, 0x5d, 0xffffffff, 0x00100100); |
|||
set_nbmisc_enable_bits(nb_dev, 0x5f, 0xffffffff, 0x00100100); |
|||
set_nbmisc_enable_bits(nb_dev, 0x20, 1<<1, 0); |
|||
set_nbmisc_enable_bits(nb_dev, 0x37, 1<<11|1<<12|1<<13|1<<26, 0); |
|||
set_nbmisc_enable_bits(nb_dev, 0x68, 1<<5|1<<6, 1<<5); |
|||
set_nbmisc_enable_bits(nb_dev, 0x6b, 1<<22, 1<<10); |
|||
set_nbmisc_enable_bits(nb_dev, 0x67, 1<<26, 1<<14|1<<10); |
|||
set_nbmisc_enable_bits(nb_dev, 0x24, 1<<28|1<<26|1<<25|1<<16, 1<<29|1<<25); |
|||
set_nbmisc_enable_bits(nb_dev, 0x38, 1<<24|1<<25, 1<<24); |
|||
set_nbmisc_enable_bits(nb_dev, 0x36, 1<<29, 1<<29|1<<28); |
|||
set_nbmisc_enable_bits(nb_dev, 0x0c, 0, 1<<13); |
|||
set_nbmisc_enable_bits(nb_dev, 0x34, 1<<22, 1<<10); |
|||
set_nbmisc_enable_bits(nb_dev, 0x39, 1<<10, 1<<30); |
|||
set_nbmisc_enable_bits(nb_dev, 0x22, 1<<3, 0); |
|||
set_nbmisc_enable_bits(nb_dev, 0x68, 1<<19, 0); |
|||
set_nbmisc_enable_bits(nb_dev, 0x24, 1<<16|1<<17, 1<<17); |
|||
set_nbmisc_enable_bits(nb_dev, 0x6a, 1<<22|1<<23, 1<<17|1<<23); |
|||
set_nbmisc_enable_bits(nb_dev, 0x35, 1<<21|1<<22, 1<<22); |
|||
set_nbmisc_enable_bits(nb_dev, 0x01, 0xffffffff, 0x48); |
|||
/* BTDC: the last two step. */ |
|||
set_nbmisc_enable_bits(nb_dev, 0x01, 1<<8, 1<<8); |
|||
set_htiu_enable_bits(nb_dev, 0x2d, 1<<6|1<<4, 1<<6|1<<4); |
|||
} |
|||
break; |
|||
case 1: /* bus0, dev1, APC. */ |
|||
printk_info("Bus-0, Dev-1, Fun-0.\n"); |
|||
rs780_internal_gfx_enable(nb_dev,dev); |
|||
break; |
|||
case 2: |
|||
case 3: |
|||
set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, |
|||
(1 ? 0 : 1) << dev_ind); |
|||
rs780_gfx_init(nb_dev, dev, dev_ind); |
|||
break; |
|||
case 4: /* bus0, dev4-7, four GPP */ |
|||
case 5: |
|||
case 6: |
|||
case 7: |
|||
enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ |
|||
set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, |
|||
(1 ? 0 : 1) << dev_ind); |
|||
rs780_gpp_sb_init(nb_dev, dev, dev_ind); |
|||
break; |
|||
case 8: /* bus0, dev8, SB */ |
|||
set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, |
|||
(1 ? 0 : 1) << dev_ind); |
|||
rs780_gpp_sb_init(nb_dev, dev, dev_ind); |
|||
disable_pcie_bar3(nb_dev); |
|||
break; |
|||
case 9: /* bus 0, dev 9,10, GPP */ |
|||
case 10: |
|||
enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ |
|||
set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind), |
|||
(1 ? 0 : 1) << (7 + dev_ind)); |
|||
rs780_gpp_sb_init(nb_dev, dev, dev_ind); |
|||
break; |
|||
default: |
|||
printk_debug("unknown dev: %s\n", dev_ind); |
|||
} |
|||
} |
|||
|
|||
void rs780_after_pci_fixup(void){ |
|||
device_t dev; |
|||
|
|||
/* bus0, dev0, fun0; */ |
|||
dev = _pci_make_tag(0, 0, 0); |
|||
rs780_enable(dev); |
|||
|
|||
#if 1 |
|||
/* bus0, dev1, APC. */ |
|||
printk_info("Bus-0, Dev-1, Fun-0.\n"); |
|||
dev = _pci_make_tag(0, 1, 0); |
|||
rs780_internal_gfx_init(_pci_make_tag(0,0,0) , _pci_make_tag(0,1,0)); |
|||
rs780_enable(dev); |
|||
|
|||
/* bus0, dev2,3, two GFX */ |
|||
printk_info("Bus-0, Dev-2, Fun-0\n"); |
|||
dev = _pci_make_tag(0, 2, 0); |
|||
rs780_enable(dev); |
|||
printk_info("Bus-0, Dev-3, Fun-0\n"); |
|||
dev = _pci_make_tag(0, 3, 0); |
|||
set_nbmisc_enable_bits(_pci_make_tag(0, 0, 0), 0x0c, 1 << 3,0 << 3); |
|||
rs780_gfx_3_init(_pci_make_tag(0, 0, 0), dev, 3); |
|||
|
|||
/* bus0, dev4-7, four GPPSB */ |
|||
printk_info("Bus-0, Dev-4, Fun-0\n"); |
|||
dev = _pci_make_tag(0, 4, 0); |
|||
rs780_enable(dev); |
|||
printk_info("Bus-0, Dev-5, Fun-0\n"); |
|||
dev = _pci_make_tag(0, 5, 0); |
|||
rs780_enable(dev); |
|||
printk_info("Bus-0, Dev-6, Fun-0\n"); |
|||
dev = _pci_make_tag(0, 6, 0); |
|||
rs780_enable(dev); |
|||
printk_info("Bus-0, Dev-7, Fun-0\n"); |
|||
dev = _pci_make_tag(0, 7, 0); |
|||
rs780_enable(dev); |
|||
|
|||
/* bus 0, dev 9,10, GPP */ |
|||
printk_info("Bus-0, Dev-9, Fun-0\n"); |
|||
dev = _pci_make_tag(0, 9, 0); |
|||
rs780_enable(dev); |
|||
printk_info("Bus-0, Dev-10, Fun-0\n"); |
|||
dev = _pci_make_tag(0, 10, 0); |
|||
rs780_enable(dev); |
|||
/* bus0, dev8, SB */ |
|||
printk_info("Bus-0, Dev-8, Fun-0\n"); |
|||
dev = _pci_make_tag(0, 8, 0); |
|||
rs780_enable(dev); |
|||
#endif |
|||
} |
|||
|
|||
/************
|
|||
* 0:11.0 SATA |
|||
* 0:12.0 OHCI0-USB1 |
|||
* 0:12.1 OHCI1-USB1 |
|||
* 0:12.2 EHCI-USB1 |
|||
* 0:13.0 OHCI0-USB2 |
|||
* 0:13.1 OHCI1-USB2 |
|||
* 0:13.2 EHCI-USB2 |
|||
* 0:14.5 OHCI0-USB3 |
|||
* 0:14.0 SMBUS 0 |
|||
* 0:14.1 IDE 1 |
|||
* 0:14.2 HDA |
|||
* 0:14.3 LPC |
|||
* 0:14.4 PCI |
|||
*************/ |
|||
|
|||
void sb700_after_pci_fixup(void){ |
|||
#ifdef ENABLE_SATA |
|||
printk_info("sata init\n"); |
|||
sata_init(_pci_make_tag(0, 0x11, 0)); |
|||
#endif |
|||
printk_info("OHCI0-USB1 init\n"); |
|||
usb_init(_pci_make_tag(0, 0x12, 0)); |
|||
|
|||
printk_info("OHCI1-USB1 init\n"); |
|||
usb_init(_pci_make_tag(0, 0x12, 1)); |
|||
#if 1 |
|||
//printk_info("EHCI-USB1 init\n");
|
|||
usb_init2(_pci_make_tag(0, 0x12, 2)); |
|||
printk_info("OHCI0-USB2 init\n"); |
|||
usb_init(_pci_make_tag(0, 0x13, 0)); |
|||
printk_info("OHCI1-USB2 init\n"); |
|||
usb_init(_pci_make_tag(0, 0x13, 1)); |
|||
//printk_info("EHCI-USB2 init\n");
|
|||
usb_init2(_pci_make_tag(0, 0x13, 2)); |
|||
printk_info("OHCI0-USB3 init\n"); |
|||
usb_init(_pci_make_tag(0, 0x14, 5)); |
|||
#endif |
|||
printk_info("lpc init\n"); |
|||
lpc_init(_pci_make_tag(0, 0x14, 3)); |
|||
printk_info("ide init\n"); |
|||
ide_init(_pci_make_tag(0, 0x14, 1)); |
|||
//vga test
|
|||
printk_info("pci init\n"); |
|||
pci_init(_pci_make_tag(0, 0x14, 4)); |
|||
printk_info("sm init\n"); |
|||
sm_init(_pci_make_tag(0, 0x14, 0)); |
|||
#ifdef USE_780E_VGA |
|||
printk_info("rs780_internal_gfx_init\n"); |
|||
internal_gfx_pci_dev_init(_pci_make_tag(0,0,0) , _pci_make_tag(1,0x5,0)); |
|||
#endif |
|||
} |
|||
@ -0,0 +1,19 @@ |
|||
#ifndef AMD_780E_H |
|||
#define AMD_780E_H |
|||
|
|||
#include "rs780.h" |
|||
|
|||
void rs780_early_setup(void); |
|||
void sb700_early_setup(void); |
|||
|
|||
int optimize_link_incoherent_ht(void); |
|||
void soft_reset(void); |
|||
|
|||
void rs780_before_pci_fixup(void); |
|||
void sb700_before_pci_fixup(void); |
|||
|
|||
|
|||
void rs780_after_pci_fixup(void); |
|||
void sb700_after_pci_fixup(void); |
|||
|
|||
#endif |
|||
@ -0,0 +1,118 @@ |
|||
/*
|
|||
* cs5536_io.h |
|||
* some basic access of msr read/write and gpio read/write. |
|||
* this access function only suitable before the virtual support module(VSM) |
|||
* working for some simple debugs. |
|||
* |
|||
* Author : jlliu <liujl@lemote.com> |
|||
* Date : 07-07-04 |
|||
* |
|||
*/ |
|||
#include <sys/linux/types.h> |
|||
#include <sys/param.h> |
|||
#include <sys/device.h> |
|||
#include <sys/systm.h> |
|||
#include <sys/malloc.h> |
|||
|
|||
#include <dev/pci/pcivar.h> |
|||
#include <dev/pci/pcireg.h> |
|||
#include <dev/pci/nppbreg.h> |
|||
|
|||
#include <machine/bus.h> |
|||
|
|||
#include <include/bonito.h> |
|||
#include <include/cs5536_pci.h> |
|||
#include <pmon.h> |
|||
|
|||
|
|||
/******************************************************************************/ |
|||
|
|||
/*
|
|||
* rdmsr : read 64bits data from the cs5536 MSR register |
|||
*/ |
|||
void _rdmsr(u32 msr, u32 *hi, u32 *lo) |
|||
{ |
|||
u32 type = 0x00000; |
|||
u32 addr; |
|||
|
|||
addr = (PCI_BUS_CS5536 << 16) | (1 << (PCI_IDSEL_CS5536 + 11) ) | (0 << 8) | 0xf4; |
|||
BONITO_PCICMD |= PCI_STATUS_MASTER_ABORT | PCI_STATUS_MASTER_TARGET_ABORT; |
|||
BONITO_PCIMAP_CFG = (addr >> 16) | type; |
|||
*(volatile pcireg_t *)PHYS_TO_UNCACHED(BONITO_PCICFG_BASE | (addr & 0xfffc)) = msr; |
|||
if (BONITO_PCICMD & PCI_STATUS_MASTER_ABORT) { |
|||
BONITO_PCICMD |= PCI_STATUS_MASTER_ABORT; |
|||
} |
|||
if (BONITO_PCICMD & PCI_STATUS_MASTER_TARGET_ABORT) { |
|||
BONITO_PCICMD |= PCI_STATUS_MASTER_TARGET_ABORT; |
|||
} |
|||
|
|||
addr = (PCI_BUS_CS5536 << 16) | (1 << (PCI_IDSEL_CS5536 + 11) ) | (0 << 8) | 0xf8; |
|||
BONITO_PCICMD |= PCI_STATUS_MASTER_ABORT | PCI_STATUS_MASTER_TARGET_ABORT; |
|||
BONITO_PCIMAP_CFG = (addr >> 16) | type; |
|||
*lo = *(volatile pcireg_t *)PHYS_TO_UNCACHED(BONITO_PCICFG_BASE | (addr & 0xfffc)); |
|||
if (BONITO_PCICMD & PCI_STATUS_MASTER_ABORT) { |
|||
BONITO_PCICMD |= PCI_STATUS_MASTER_ABORT; |
|||
} |
|||
if (BONITO_PCICMD & PCI_STATUS_MASTER_TARGET_ABORT) { |
|||
BONITO_PCICMD |= PCI_STATUS_MASTER_TARGET_ABORT; |
|||
} |
|||
|
|||
addr = (PCI_BUS_CS5536 << 16) | (1 << (PCI_IDSEL_CS5536 + 11) ) | (0 << 8) | 0xfc; |
|||
BONITO_PCICMD |= PCI_STATUS_MASTER_ABORT | PCI_STATUS_MASTER_TARGET_ABORT; |
|||
BONITO_PCIMAP_CFG = (addr >> 16) | type; |
|||
*hi = *(volatile pcireg_t *)PHYS_TO_UNCACHED(BONITO_PCICFG_BASE | (addr & 0xfffc)); |
|||
if (BONITO_PCICMD & PCI_STATUS_MASTER_ABORT) { |
|||
BONITO_PCICMD |= PCI_STATUS_MASTER_ABORT; |
|||
} |
|||
if (BONITO_PCICMD & PCI_STATUS_MASTER_TARGET_ABORT) { |
|||
BONITO_PCICMD |= PCI_STATUS_MASTER_TARGET_ABORT; |
|||
} |
|||
|
|||
return; |
|||
} |
|||
|
|||
/*
|
|||
* wrmsr : write 64bits data to the cs5536 MSR register |
|||
*/ |
|||
void _wrmsr(u32 msr, u32 hi, u32 lo) |
|||
{ |
|||
u32 type = 0x00000; |
|||
u32 addr; |
|||
|
|||
addr = (PCI_BUS_CS5536 << 16) | (1 << (PCI_IDSEL_CS5536 + 11) ) | (0 << 8) | 0xf4; |
|||
BONITO_PCICMD |= PCI_STATUS_MASTER_ABORT | PCI_STATUS_MASTER_TARGET_ABORT; |
|||
BONITO_PCIMAP_CFG = (addr >> 16) | type; |
|||
*(volatile pcireg_t *)PHYS_TO_UNCACHED(BONITO_PCICFG_BASE | (addr & 0xfffc)) = msr; |
|||
if (BONITO_PCICMD & PCI_STATUS_MASTER_ABORT) { |
|||
BONITO_PCICMD |= PCI_STATUS_MASTER_ABORT; |
|||
} |
|||
if (BONITO_PCICMD & PCI_STATUS_MASTER_TARGET_ABORT) { |
|||
BONITO_PCICMD |= PCI_STATUS_MASTER_TARGET_ABORT; |
|||
} |
|||
|
|||
addr = (PCI_BUS_CS5536 << 16) | (1 << (PCI_IDSEL_CS5536 + 11) ) | (0 << 8) | 0xf8; |
|||
BONITO_PCICMD |= PCI_STATUS_MASTER_ABORT | PCI_STATUS_MASTER_TARGET_ABORT; |
|||
BONITO_PCIMAP_CFG = (addr >> 16) | type; |
|||
*(volatile pcireg_t *)PHYS_TO_UNCACHED(BONITO_PCICFG_BASE | (addr & 0xfffc)) = lo; |
|||
if (BONITO_PCICMD & PCI_STATUS_MASTER_ABORT) { |
|||
BONITO_PCICMD |= PCI_STATUS_MASTER_ABORT; |
|||
} |
|||
if (BONITO_PCICMD & PCI_STATUS_MASTER_TARGET_ABORT) { |
|||
BONITO_PCICMD |= PCI_STATUS_MASTER_TARGET_ABORT; |
|||
} |
|||
|
|||
|
|||
addr = (PCI_BUS_CS5536 << 16) | (1 << (PCI_IDSEL_CS5536 + 11) ) | (0 << 8) | 0xfc; |
|||
BONITO_PCICMD |= PCI_STATUS_MASTER_ABORT | PCI_STATUS_MASTER_TARGET_ABORT; |
|||
BONITO_PCIMAP_CFG = (addr >> 16) | type; |
|||
*(volatile pcireg_t *)PHYS_TO_UNCACHED(BONITO_PCICFG_BASE | (addr & 0xfffc)) = hi; |
|||
if (BONITO_PCICMD & PCI_STATUS_MASTER_ABORT) { |
|||
BONITO_PCICMD |= PCI_STATUS_MASTER_ABORT; |
|||
} |
|||
if (BONITO_PCICMD & PCI_STATUS_MASTER_TARGET_ABORT) { |
|||
BONITO_PCICMD |= PCI_STATUS_MASTER_TARGET_ABORT; |
|||
} |
|||
|
|||
|
|||
return; |
|||
} |
|||
@ -0,0 +1,25 @@ |
|||
/*
|
|||
* cs5536_io.h |
|||
* some basic access of msr read/write and gpio read/write. |
|||
* this access function only suitable before the virtual support module(VSM) |
|||
* working for some simple debugs. |
|||
* |
|||
* Author : jlliu <liujl@lemote.com> |
|||
* Date : 07-07-04 |
|||
* |
|||
*/ |
|||
|
|||
#include <sys/linux/types.h> |
|||
|
|||
/******************************************************************************/ |
|||
|
|||
/*
|
|||
* rdmsr : read 64bits data from the cs5536 MSR register |
|||
*/ |
|||
extern void _rdmsr(u32 msr, u32 *hi, u32 *lo); |
|||
|
|||
/*
|
|||
* wrmsr : write 64bits data to the cs5536 MSR register |
|||
*/ |
|||
extern void _wrmsr(u32 msr, u32 hi, u32 lo); |
|||
|
|||
File diff suppressed because it is too large
@ -0,0 +1,278 @@ |
|||
/* $Id: pci_machdep.c,v 1.1.1.1 2006/09/14 01:59:09 root Exp $ */ |
|||
|
|||
/*
|
|||
* Copyright (c) 2001 Opsycon AB (www.opsycon.se) |
|||
* |
|||
* Redistribution and use in source and binary forms, with or without |
|||
* modification, are permitted provided that the following conditions |
|||
* are met: |
|||
* 1. Redistributions of source code must retain the above copyright |
|||
* notice, this list of conditions and the following disclaimer. |
|||
* 2. Redistributions in binary form must reproduce the above copyright |
|||
* notice, this list of conditions and the following disclaimer in the |
|||
* documentation and/or other materials provided with the distribution. |
|||
* 3. All advertising materials mentioning features or use of this software |
|||
* must display the following acknowledgement: |
|||
* This product includes software developed by Opsycon AB, Sweden. |
|||
* 4. The name of the author may not be used to endorse or promote products |
|||
* derived from this software without specific prior written permission. |
|||
* |
|||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS |
|||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
|||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
|||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
|||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
|||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
|||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
|||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
|||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
|||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
|||
* SUCH DAMAGE. |
|||
* |
|||
*/ |
|||
|
|||
#include <sys/param.h> |
|||
#include <sys/device.h> |
|||
#include <sys/systm.h> |
|||
|
|||
#include <sys/malloc.h> |
|||
|
|||
#include <dev/pci/pcivar.h> |
|||
#include <dev/pci/pcireg.h> |
|||
#include <dev/pci/nppbreg.h> |
|||
|
|||
#include <machine/bus.h> |
|||
|
|||
#include "include/bonito.h" |
|||
|
|||
#include <pmon.h> |
|||
|
|||
extern void *pmalloc __P((size_t )); |
|||
#if (PCI_IDSEL_CS5536 != 0) |
|||
#include <include/cs5536_pci.h> |
|||
extern pcireg_t cs5536_pci_conf_readn(int function, int reg, int width); |
|||
extern int cs5536_pci_conf_writen(int function, int reg, int width, pcireg_t value); |
|||
#endif |
|||
extern void *pmalloc __P((size_t )); |
|||
|
|||
extern int _pciverbose; |
|||
|
|||
extern char hwethadr[6]; |
|||
struct pci_device *_pci_bus[16]; |
|||
int _max_pci_bus = 0; |
|||
|
|||
|
|||
/* PCI mem regions in PCI space */ |
|||
|
|||
/* soft versions of above */ |
|||
static pcireg_t pci_local_mem_pci_base; |
|||
|
|||
|
|||
/****************************/ |
|||
/*initial PCI */ |
|||
/****************************/ |
|||
|
|||
int |
|||
_pci_hwinit(initialise, iot, memt) |
|||
int initialise; |
|||
bus_space_tag_t iot; |
|||
bus_space_tag_t memt; |
|||
{ |
|||
/*pcireg_t stat;*/ |
|||
struct pci_device *pd; |
|||
struct pci_bus *pb; |
|||
int newcfg=0; |
|||
if(getenv("newcfg"))newcfg=1; |
|||
|
|||
if (!initialise) { |
|||
return(0); |
|||
} |
|||
|
|||
/*
|
|||
* Allocate and initialize PCI bus heads. |
|||
*/ |
|||
|
|||
/*
|
|||
* PCI Bus 0 |
|||
*/ |
|||
pd = pmalloc(sizeof(struct pci_device)); |
|||
pb = pmalloc(sizeof(struct pci_bus)); |
|||
if(pd == NULL || pb == NULL) { |
|||
printf("pci: can't alloc memory. pci not initialized\n"); |
|||
return(-1); |
|||
} |
|||
|
|||
pd->pa.pa_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; |
|||
pd->pa.pa_iot = pmalloc(sizeof(bus_space_tag_t)); |
|||
pd->pa.pa_iot->bus_reverse = 1; |
|||
pd->pa.pa_iot->bus_base = BONITO_PCIIO_BASE_VA; |
|||
//printf("pd->pa.pa_iot=%p,bus_base=0x%x\n",pd->pa.pa_iot,pd->pa.pa_iot->bus_base);
|
|||
pd->pa.pa_memt = pmalloc(sizeof(bus_space_tag_t)); |
|||
pd->pa.pa_memt->bus_reverse = 1; |
|||
//pd->pa.pa_memt->bus_base = PCI_LOCAL_MEM_PCI_BASE;
|
|||
pd->pa.pa_memt->bus_base = 0xc0000000; |
|||
pd->pa.pa_dmat = &bus_dmamap_tag; |
|||
pd->bridge.secbus = pb; |
|||
_pci_head = pd; |
|||
|
|||
#ifdef LS3_HT /* whd */ |
|||
pb->minpcimemaddr = BONITO_PCILO0_BASE; |
|||
pb->nextpcimemaddr = BONITO_PCILO0_BASE+BONITO_PCILO_SIZE; |
|||
pb->minpciioaddr = PCI_IO_SPACE_BASE+0x0004000; |
|||
pb->nextpciioaddr = PCI_IO_SPACE_BASE+ BONITO_PCIIO_SIZE; |
|||
pb->pci_mem_base = BONITO_PCILO_BASE_VA; |
|||
pb->pci_io_base = BONITO_PCIIO_BASE_VA; |
|||
#else |
|||
if(newcfg) |
|||
{ |
|||
pb->minpcimemaddr = BONITO_PCILO1_BASE;//??????,???ܺ?linux??????ʼ??ַһ??,????xwindow????ʾ??????
|
|||
pb->nextpcimemaddr = BONITO_PCIHI_BASE; |
|||
pd->pa.pa_memt->bus_base = 0xa0000000; |
|||
BONITO_PCIMAP = |
|||
BONITO_PCIMAP_WIN(0, PCI_MEM_SPACE_PCI_BASE+0x00000000) | |
|||
BONITO_PCIMAP_WIN(1, PCI_MEM_SPACE_PCI_BASE+0x14000000) | |
|||
BONITO_PCIMAP_WIN(2, PCI_MEM_SPACE_PCI_BASE+0x18000000) | |
|||
BONITO_PCIMAP_PCIMAP_2; |
|||
} |
|||
else |
|||
{ |
|||
/*pci??ַ??cpu??ַ????,????pci memʱҪioreamapת??,ֱ??or 0xb0000000*/ |
|||
pb->minpcimemaddr = 0x04000000; |
|||
pb->nextpcimemaddr = 0x08000000; |
|||
pd->pa.pa_memt->bus_base = 0xb0000000; |
|||
BONITO_PCIMAP = |
|||
BONITO_PCIMAP_WIN(0, PCI_MEM_SPACE_PCI_BASE+0x00000000) | |
|||
BONITO_PCIMAP_WIN(1, PCI_MEM_SPACE_PCI_BASE+0x04000000) | |
|||
BONITO_PCIMAP_WIN(2, PCI_MEM_SPACE_PCI_BASE+0x08000000) | |
|||
BONITO_PCIMAP_PCIMAP_2; |
|||
} |
|||
pb->minpciioaddr = 0x0004000; |
|||
pb->nextpciioaddr = BONITO_PCIIO_SIZE; |
|||
pb->pci_mem_base = BONITO_PCILO_BASE_VA; |
|||
pb->pci_io_base = BONITO_PCIIO_BASE_VA; |
|||
#endif |
|||
|
|||
pb->max_lat = 255; |
|||
pb->fast_b2b = 1; |
|||
pb->prefetch = 1; |
|||
pb->bandwidth = 4000000; |
|||
pb->ndev = 1; |
|||
_pci_bushead = pb; |
|||
_pci_bus[_max_pci_bus++] = pd; |
|||
|
|||
|
|||
bus_dmamap_tag._dmamap_offs = 0; |
|||
|
|||
/*set pci base0 address and window size*/ |
|||
pci_local_mem_pci_base = 0x80000000; |
|||
#ifdef LS3_HT |
|||
#else |
|||
BONITO_PCIBASE0 = 0x80000000; |
|||
#endif |
|||
return(1); |
|||
} |
|||
|
|||
/*
|
|||
* Called to reinitialise the bridge after we've scanned each PCI device |
|||
* and know what is possible. We also set up the interrupt controller |
|||
* routing and level control registers. |
|||
*/ |
|||
void |
|||
_pci_hwreinit (void) |
|||
{ |
|||
} |
|||
|
|||
void |
|||
_pci_flush (void) |
|||
{ |
|||
} |
|||
|
|||
/*
|
|||
* Map the CPU virtual address of an area of local memory to a PCI |
|||
* address that can be used by a PCI bus master to access it. |
|||
*/ |
|||
vm_offset_t |
|||
_pci_dmamap(va, len) |
|||
vm_offset_t va; |
|||
unsigned int len; |
|||
{ |
|||
#if 0 |
|||
return(VA_TO_PA(va) + bus_dmamap_tag._dmamap_offs); |
|||
#endif |
|||
return(pci_local_mem_pci_base + VA_TO_PA (va)); |
|||
} |
|||
|
|||
|
|||
#if 1 |
|||
/*
|
|||
* Map the PCI address of an area of local memory to a CPU physical |
|||
* address. |
|||
*/ |
|||
vm_offset_t |
|||
_pci_cpumap(pcia, len) |
|||
vm_offset_t pcia; |
|||
unsigned int len; |
|||
{ |
|||
return PA_TO_VA(pcia - pci_local_mem_pci_base); |
|||
} |
|||
#endif |
|||
|
|||
|
|||
/*
|
|||
* Make pci tag from bus, device and function data. |
|||
*/ |
|||
pcitag_t |
|||
_pci_make_tag(bus, device, function) |
|||
int bus; |
|||
int device; |
|||
int function; |
|||
{ |
|||
pcitag_t tag; |
|||
|
|||
tag = (bus << 16) | (device << 11) | (function << 8); |
|||
return(tag); |
|||
} |
|||
|
|||
/*
|
|||
* Break up a pci tag to bus, device function components. |
|||
*/ |
|||
void |
|||
_pci_break_tag(tag, busp, devicep, functionp) |
|||
pcitag_t tag; |
|||
int *busp; |
|||
int *devicep; |
|||
int *functionp; |
|||
{ |
|||
if (busp) { |
|||
*busp = (tag >> 16) & 255; |
|||
} |
|||
if (devicep) { |
|||
*devicep = (tag >> 11) & 31; |
|||
} |
|||
if (functionp) { |
|||
*functionp = (tag >> 8) & 7; |
|||
} |
|||
} |
|||
|
|||
int |
|||
_pci_canscan (pcitag_t tag) |
|||
{ |
|||
int bus, device, function; |
|||
|
|||
_pci_break_tag (tag, &bus, &device, &function); |
|||
if((bus == 0 ) && device == 0) { |
|||
return(0); /* Ignore the Discovery itself */ |
|||
} |
|||
return (1); |
|||
} |
|||
|
|||
void |
|||
pci_sync_cache(p, adr, size, rw) |
|||
void *p; |
|||
vm_offset_t adr; |
|||
size_t size; |
|||
int rw; |
|||
{ |
|||
CPU_IOFlushDCache(adr, size, rw); |
|||
} |
|||
|
|||
@ -0,0 +1,118 @@ |
|||
/* $Id: pci_machdep.h,v 1.1.1.1 2006/09/14 01:59:09 root Exp $ */ |
|||
|
|||
/*
|
|||
* Copyright (c) 2001 Opsycon AB (www.opsycon.se) |
|||
* |
|||
* Redistribution and use in source and binary forms, with or without |
|||
* modification, are permitted provided that the following conditions |
|||
* are met: |
|||
* 1. Redistributions of source code must retain the above copyright |
|||
* notice, this list of conditions and the following disclaimer. |
|||
* 2. Redistributions in binary form must reproduce the above copyright |
|||
* notice, this list of conditions and the following disclaimer in the |
|||
* documentation and/or other materials provided with the distribution. |
|||
* 3. All advertising materials mentioning features or use of this software |
|||
* must display the following acknowledgement: |
|||
* This product includes software developed by Opsycon AB. |
|||
* 4. The name of the author may not be used to endorse or promote products |
|||
* derived from this software without specific prior written permission. |
|||
* |
|||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS |
|||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
|||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
|||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
|||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
|||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
|||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
|||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
|||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
|||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
|||
* SUCH DAMAGE. |
|||
* |
|||
*/ |
|||
|
|||
#include <target/pmon_target.h> |
|||
|
|||
#include <pmon.h> |
|||
|
|||
/*
|
|||
* Types provided to machine-independent PCI code |
|||
*/ |
|||
typedef struct arch_pci_chipset *pci_chipset_tag_t; |
|||
typedef u_long pcitag_t; |
|||
typedef u_long pci_intr_handle_t; |
|||
|
|||
void _pci_flush __P((void)); |
|||
int _pci_hwinit __P((int, bus_space_tag_t, bus_space_tag_t)); |
|||
void _pci_hwreinit __P((void)); |
|||
pcitag_t _pci_make_tag __P((int, int, int)); |
|||
void _pci_break_tag __P((pcitag_t, int *, int *, int *)); |
|||
pcireg_t _pci_conf_readn __P((pcitag_t, int,int)); |
|||
void _pci_conf_writen __P((pcitag_t, int, pcireg_t,int)); |
|||
pcireg_t _pci_conf_read __P((pcitag_t, int)); |
|||
void _pci_conf_write __P((pcitag_t, int, pcireg_t)); |
|||
int _pci_map_port __P((pcitag_t, int, unsigned int *)); |
|||
int _pci_map_io __P((pcitag_t, int, vm_offset_t *, vm_offset_t *)); |
|||
int _pci_map_mem __P((pcitag_t, int, vm_offset_t *, vm_offset_t *)); |
|||
void *_pci_map_int __P((pcitag_t, int, int (*)(void *), void *)); |
|||
void _pci_devinfo __P((pcireg_t, pcireg_t, int *, char *)); |
|||
void _pci_businit __P((int)); |
|||
void _pci_devinit __P((int)); |
|||
vm_offset_t _pci_cpumap __P((vm_offset_t, unsigned int)); |
|||
vm_offset_t _pci_dmamap __P((vm_offset_t, unsigned int)); |
|||
|
|||
void _pci_bdfprintf (int bus, int device, int function, const char *fmt, ...); |
|||
void _pci_tagprintf (pcitag_t tag, const char *fmt, ...); |
|||
int _pci_canscan __P((pcitag_t tag)); |
|||
|
|||
/* sigh... compatibility */ |
|||
#define pci_hwinit _pci_hwinit |
|||
#define pci_hwreinit _pci_hwreinit |
|||
#define pci_make_tag _pci_make_tag |
|||
#define pci_break_tag _pci_break_tag |
|||
#define pci_conf_read(a, b, c) _pci_conf_read(b, c) |
|||
#define pci_conf_write(a, b, c, d) _pci_conf_write(b, c, d) |
|||
#define pci_map_port _pci_map_port |
|||
#define pci_map_io _pci_map_io |
|||
#define pci_map_mem _pci_map_mem |
|||
#define pci_map_int _pci_map_int |
|||
#define pci_devinfo _pci_devinfo |
|||
#define pci_configure _pci_configure |
|||
#define pci_allocate_mem _pci_allocate_mem |
|||
#define pci_allocate_io _pci_allocate_io |
|||
#define vtophys(p) _pci_dmamap((vm_offset_t)p, 1) |
|||
#define pci_decompose_tag(a, b, c, d, e) _pci_break_tag(b, c, d, e) |
|||
|
|||
#define pci_intr_map(a, b, c, d, e) (*e = -1, 0) |
|||
#define pci_intr_string(a,b) ("generic poll") |
|||
#define pci_intr_establish(a, b, c, d, e, f) tgt_poll_register((c), (d), (e)) |
|||
#define pci_attach_hook(parent, self, pba) |
|||
#define pci_bus_maxdevs(c, b) 32 |
|||
|
|||
int pci_ether_hw_addr __P((void *sc, u_int8_t *, u_int8_t, u_int8_t)); |
|||
void pci_sync_cache __P((void *, vm_offset_t, size_t, int)); |
|||
|
|||
#define CACHESYNC(a, l, h) pci_sync_cache((void *)NULL, (vm_offset_t)a, l ,h) |
|||
|
|||
#define NEED_PCI_SYNC_CACHE_FUNC |
|||
|
|||
#define SYNC_R 0 /* Sync caches for reading data */ |
|||
#define SYNC_W 1 /* Sync caches for writing data */ |
|||
|
|||
#define PCI_FIRST_DEVICE 1 /* Which device to scan first */ |
|||
#define PCI_FIRST_BUS 0 |
|||
#define PCI_INT_0 0 |
|||
#define PCI_INT_A 11 |
|||
#define PCI_INT_B 10 |
|||
#define PCI_INT_C 9 |
|||
#define PCI_INT_D 8 |
|||
#define PCI_CACHE_LINE_SIZE 8 /* expressed in 32 bit words */ |
|||
|
|||
#define NEWPCIROOT |
|||
extern struct pci_device *_pci_bus[]; |
|||
|
|||
/*
|
|||
* Any physical to virtual conversion CPU |
|||
*/ |
|||
#define VA_TO_PA(x) UNCACHED_TO_PHYS(x) |
|||
#define PA_TO_VA(x) PHYS_TO_CACHED(x) |
|||
@ -0,0 +1,86 @@ |
|||
#include "rs780.h" |
|||
|
|||
/*****************************************
|
|||
* Compliant with CIM_33's ATINB_MiscClockCtrl |
|||
*****************************************/ |
|||
void static rs780_config_misc_clk(device_t nb_dev) |
|||
{ |
|||
u32 reg; |
|||
u16 word; |
|||
/* u8 byte; */ |
|||
//struct bus pbus; /* fake bus for dev0 fun1 */
|
|||
|
|||
reg = pci_read_config32(nb_dev, 0x4c); |
|||
reg |= 1 << 0; |
|||
pci_write_config32(nb_dev, 0x4c, reg); |
|||
|
|||
word = pci_read_config16(_pci_make_tag(0, 0, 1), 0xf8); |
|||
word &= 0xf00; |
|||
pci_write_config16(_pci_make_tag(0, 0, 1), 0xf8, word); |
|||
|
|||
word = pci_read_config16(_pci_make_tag(0, 0, 1), 0xe8); |
|||
word &= ~((1 << 12) | (1 << 13) | (1 << 14)); |
|||
word |= 1 << 13; |
|||
pci_write_config16(_pci_make_tag(0, 0, 1), 0xe8, word); |
|||
|
|||
reg = pci_read_config32(_pci_make_tag(0, 0, 1), 0x94); |
|||
reg &= ~((1 << 16) | (1 << 24) | (1 << 28)); |
|||
pci_write_config32(_pci_make_tag(0, 0, 1), 0x94, reg); |
|||
|
|||
reg = pci_read_config32(_pci_make_tag(0, 0, 1), 0x8c); |
|||
reg &= ~((1 << 13) | (1 << 14) | (1 << 24) | (1 << 25)); |
|||
reg |= 1 << 13; |
|||
pci_write_config32(_pci_make_tag(0, 0, 1), 0x8c, reg); |
|||
|
|||
reg = pci_read_config32(_pci_make_tag(0, 0, 1), 0xcc); |
|||
reg |= 1 << 24; |
|||
pci_write_config32(_pci_make_tag(0, 0, 1), 0xcc, reg); |
|||
|
|||
reg = nbmc_read_index(nb_dev, 0x7a); |
|||
reg &= ~0x3f; |
|||
reg |= 1 << 2; |
|||
reg &= ~(1 << 6); |
|||
set_htiu_enable_bits(nb_dev, 0x05, 1 << 11, 1 << 11); |
|||
nbmc_write_index(nb_dev, 0x7a, reg); |
|||
/* Powering Down efuse and strap block clocks after boot-up. GFX Mode. */ |
|||
reg = pci_read_config32(_pci_make_tag(0, 0, 1), 0xcc); |
|||
reg &= ~(1 << 23); |
|||
reg |= 1 << 24; |
|||
pci_write_config32(_pci_make_tag(0, 0, 1), 0xcc, reg); |
|||
|
|||
/* BTDC: Programming NB CLK table. */ |
|||
{ |
|||
u8 temp8; |
|||
//temp8 = pci_cf8_conf1.read8(&pbus, 0, 1, 0xe0);
|
|||
temp8 = pci_read_config8(_pci_make_tag(0, 0, 1), 0xe0); |
|||
temp8 |= 0x01; |
|||
//pci_cf8_conf1.write8(&pbus, 0, 1, 0xe0, temp8);
|
|||
pci_write_config8(_pci_make_tag(0, 0, 1), 0xe0, temp8); |
|||
} |
|||
#if 0 |
|||
/* Powerdown reference clock to graphics core PLL in northbridge only mode */ |
|||
reg = pci_read_config32(_pci_make_tag(0, 0, 1), 0x8c); |
|||
reg |= 1 << 21; |
|||
pci_write_config32(_pci_make_tag(0, 0, 1), 0x8c, reg); |
|||
|
|||
/* Powering Down efuse and strap block clocks after boot-up. NB Only Mode. */ |
|||
reg = pci_read_config32(_pci_make_tag(0, 0, 1), 0xcc); |
|||
reg |= (1 << 23) | (1 << 24); |
|||
pci_write_config32(_pci_make_tag(0, 0, 1), 0xcc, reg); |
|||
|
|||
/* Powerdown clock to memory controller in northbridge only mode */ |
|||
byte = pci_read_config8(_pci_make_tag(0, 0, 1), 0xe4); |
|||
byte |= 1 << 0; |
|||
pci_write_config8(_pci_make_tag(0,0, 1), 0xe4, reg); |
|||
|
|||
/* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */ |
|||
/* TODO: */ |
|||
#endif |
|||
|
|||
reg = pci_read_config32(nb_dev, 0x4c); |
|||
reg &= ~(1 << 0); |
|||
pci_write_config32(nb_dev, 0x4c, reg); |
|||
|
|||
set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8); |
|||
} |
|||
|
|||
@ -0,0 +1,237 @@ |
|||
/*
|
|||
* This file is part of the coreboot project. |
|||
* |
|||
* Copyright (C) 2008 Advanced Micro Devices, Inc. |
|||
* |
|||
* This program is free software; you can redistribute it and/or modify |
|||
* it under the terms of the GNU General Public License as published by |
|||
* the Free Software Foundation; version 2 of the License. |
|||
* |
|||
* This program is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* GNU General Public License for more details. |
|||
* |
|||
* You should have received a copy of the GNU General Public License |
|||
* along with this program; if not, write to the Free Software |
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
|||
*/ |
|||
|
|||
#ifndef __RS780_H__ |
|||
#define __RS780_H__ |
|||
|
|||
#include <time.h> |
|||
#include "sb700.h" |
|||
|
|||
#define NBMISC_INDEX 0x60 |
|||
#define NBHTIU_INDEX 0xA8 |
|||
#define NBMC_INDEX 0xE8 |
|||
#define NBPCIE_INDEX 0xE0 |
|||
#define EXT_CONF_BASE_ADDRESS 0x17000000 |
|||
#define TEMP_MMIO_BASE_ADDRESS 0xC0000000 |
|||
|
|||
typedef struct __PCIE_CFG__ { |
|||
u16 Config; |
|||
u8 ResetReleaseDelay; |
|||
u8 Gfx0Width; |
|||
u8 Gfx1Width; |
|||
u8 GfxPayload; |
|||
u8 GppPayload; |
|||
u8 PortDetect; |
|||
u8 PortHp; /* hot plug */ |
|||
u16 DbgConfig; |
|||
u32 DbgConfig2; |
|||
u8 GfxLx; |
|||
u8 GppLx; |
|||
u8 NBSBLx; |
|||
u8 PortSlotInit; |
|||
u8 Gfx0Pwr; |
|||
u8 Gfx1Pwr; |
|||
u8 GppPwr; |
|||
} PCIE_CFG; |
|||
|
|||
/* PCIE config flags */ |
|||
#define PCIE_DUALSLOT_CONFIG (1 << 0) |
|||
#define PCIE_OVERCLOCK_ENABLE (1 << 1) |
|||
#define PCIE_GPP_CLK_GATING (1 << 2) |
|||
#define PCIE_ENABLE_STATIC_DEV_REMAP (1 << 3) |
|||
#define PCIE_OFF_UNUSED_GFX_LANES (1 << 4) |
|||
#define PCIE_OFF_UNUSED_GPP_LANES (1 << 5) |
|||
#define PCIE_DISABLE_HIDE_UNUSED_PORTS (1 << 7) |
|||
#define PCIE_GFX_CLK_GATING (1 << 11) |
|||
#define PCIE_GFX_COMPLIANCE (1 << 14) |
|||
#define PCIE_GPP_COMPLIANCE (1 << 15) |
|||
|
|||
typedef enum _NB_REVISION_ { |
|||
REV_RS780_A11 = 5, |
|||
REV_RS780_A12 = 6, |
|||
REV_RS780_A21 = 7, |
|||
} NB_REVISION; |
|||
|
|||
|
|||
#define PCI_ADDR(BUS, DEV, FN, WHERE) ( \ |
|||
(((BUS) & 0xFF) << 16) | \ |
|||
(((DEV) & 0x1f) << 11) | \ |
|||
(((FN) & 0x07) << 8) | \ |
|||
((WHERE) & 0xFF)) |
|||
|
|||
#define PCI_DEV(BUS, DEV, FN) ( \ |
|||
(((BUS) & 0xFF) << 16) | \ |
|||
(((DEV) & 0x1f) << 11) | \ |
|||
(((FN) & 0x7) << 8)) |
|||
|
|||
/* -------------------- ----------------------
|
|||
* NBMISCIND |
|||
------------------- -----------------------*/ |
|||
#define PCIE_LINK_CFG 0x8 |
|||
#define PCIE_NBCFG_REG7 0x37 |
|||
#define STRAPS_OUTPUT_MUX_7 0x67 |
|||
#define STRAPS_OUTPUT_MUX_A 0x6a |
|||
|
|||
/* -------------------- ----------------------
|
|||
* PCIEIND |
|||
------------------- -----------------------*/ |
|||
#define PCIE_CI_CNTL 0x20 |
|||
#define PCIE_LC_LINK_WIDTH 0xa2 |
|||
#define PCIE_LC_STATE0 0xa5 |
|||
//#define PCIE_VC0_RESOURCE_STATUS 0x11a /* 16bit read only */
|
|||
#define PCIE_VC0_RESOURCE_STATUS 0x12a /* 16bit read only */ |
|||
|
|||
#define PCIE_CORE_INDEX_GFX (0 << 16) /* see 5.2.2 */ |
|||
#define PCIE_CORE_INDEX_GPPSB (1 << 16) |
|||
//add for rs780
|
|||
#define PCIE_CORE_INDEX_GPP (0x02 << 16) |
|||
#define PCIE_CORE_INDEX_BRDCST (0x03 << 16) |
|||
|
|||
/* contents of PCIE_NBCFG_REG7 */ |
|||
#define RECONFIG_GPPSB_EN (1 << 12) |
|||
#define RECONFIG_GPPSB_GPPSB (1 << 14) |
|||
#define RECONFIG_GPPSB_LINK_CONFIG (1 << 15) |
|||
#define RECONFIG_GPPSB_ATOMIC_RESET (1 << 17) |
|||
|
|||
/* contents of PCIE_VC0_RESOURCE_STATUS */ |
|||
#define VC_NEGOTIATION_PENDING (1 << 1) |
|||
|
|||
#define LC_STATE_RECONFIG_GPPSB 0x10 |
|||
|
|||
|
|||
|
|||
/* The Integrated Info Table */ |
|||
#define USHORT u16 |
|||
#define UCHAR u8 |
|||
#define ULONG u32 |
|||
|
|||
typedef struct _ATOM_COMMON_TABLE_HEADER |
|||
{ |
|||
USHORT usStructureSize; |
|||
UCHAR ucTableFormatRevision; |
|||
UCHAR ucTableContentRevision; |
|||
}ATOM_COMMON_TABLE_HEADER; |
|||
|
|||
typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 |
|||
{ |
|||
ATOM_COMMON_TABLE_HEADER sHeader; |
|||
ULONG ulBootUpEngineClock; //in 10kHz unit
|
|||
ULONG ulReserved1[2]; //must be 0x0 for the reserved
|
|||
ULONG ulBootUpUMAClock; //in 10kHz unit
|
|||
ULONG ulBootUpSidePortClock; //in 10kHz unit
|
|||
ULONG ulMinSidePortClock; //in 10kHz unit
|
|||
ULONG ulReserved2[6]; //must be 0x0 for the reserved
|
|||
ULONG ulSystemConfig; |
|||
//[0]=1: PowerExpress mode
|
|||
// =0 Non-PowerExpress mode;
|
|||
//[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will disable other power state in VBIOS table.
|
|||
// =0: system boots up at driver control state. Power state depends on VBIOS PP table.
|
|||
//[2]=1: PWM method is used on NB voltage control.
|
|||
// =0: GPIO method is used.
|
|||
//[3]=1: Only one power state(Performance) will be supported.
|
|||
// =0: Number of power states supported is from VBIOS PP table.
|
|||
//[4]=1: CLMC is supported and enabled on current system.
|
|||
// =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface.
|
|||
//[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement.
|
|||
// =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied.
|
|||
//[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and VBIOS PP table voltage drop/throttling request will be ignored.
|
|||
// =0: Voltage settings is determined by VBIOS PP table.
|
|||
//[7]=1: Enable CLMC Hybird Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue.
|
|||
// =0: Enable regular CLMC mode, CDLD and CILR will be enabled.
|
|||
//[8]=1: CDLF is supported and enabled by fuse //CHP 914
|
|||
// =0: CDLF is not supported and not enabled by fuses
|
|||
ULONG ulBootUpReqDisplayVector; |
|||
ULONG ulOtherDisplayMisc; |
|||
ULONG ulDDISlot1Config; |
|||
ULONG ulDDISlot2Config; |
|||
UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
|
|||
UCHAR ucUMAChannelNumber; |
|||
UCHAR ucDockingPinBit; |
|||
UCHAR ucDockingPinPolarity; |
|||
ULONG ulDockingPinCFGInfo; |
|||
ULONG ulCPUCapInfo; |
|||
USHORT usNumberOfCyclesInPeriod; //usNumberOfCyclesInPeriod[15] = 0 - invert waveform
|
|||
// 1 - non inverted waveform
|
|||
USHORT usMaxNBVoltage; |
|||
USHORT usMinNBVoltage; |
|||
USHORT usBootUpNBVoltage; |
|||
ULONG ulHTLinkFreq; //in 10Khz
|
|||
USHORT usMinHTLinkWidth; // if no CLMC, usMinHTLinkWidth should be equal to usMaxHTLinkWidth??
|
|||
USHORT usMaxHTLinkWidth; |
|||
USHORT usUMASyncStartDelay; // will be same as usK8SyncStartDelay on RS690
|
|||
USHORT usUMADataReturnTime; // will be same as usK8DataReturnTime on RS690
|
|||
USHORT usLinkStatusZeroTime; |
|||
USHORT usReserved; |
|||
ULONG ulHighVoltageHTLinkFreq; // in 10Khz
|
|||
ULONG ulLowVoltageHTLinkFreq; // in 10Khz
|
|||
USHORT usMaxUpStreamHTLinkWidth; |
|||
USHORT usMaxDownStreamHTLinkWidth; |
|||
USHORT usMinUpStreamHTLinkWidth; |
|||
USHORT usMinDownStreamHTLinkWidth; |
|||
ULONG ulReserved3[97]; //must be 0x0
|
|||
} ATOM_INTEGRATED_SYSTEM_INFO_V2; |
|||
|
|||
/* ------------------------------------------------
|
|||
* Global variable |
|||
* ------------------------------------------------- */ |
|||
extern PCIE_CFG AtiPcieCfg; |
|||
|
|||
|
|||
/* ----------------- export funtions ----------------- */ |
|||
u32 nbmisc_read_index(device_t nb_dev, u32 index); |
|||
void nbmisc_write_index(device_t nb_dev, u32 index, u32 data); |
|||
u32 nbpcie_p_read_index(device_t dev, u32 index); |
|||
void nbpcie_p_write_index(device_t dev, u32 index, u32 data); |
|||
u32 nbpcie_ind_read_index(device_t nb_dev, u32 index); |
|||
void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data); |
|||
u32 htiu_read_index(device_t nb_dev, u32 index); |
|||
void htiu_write_index(device_t nb_dev, u32 index, u32 data); |
|||
u32 nbmc_read_index(device_t nb_dev, u32 index); |
|||
void nbmc_write_index(device_t nb_dev, u32 index, u32 data); |
|||
|
|||
#if 0 |
|||
u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg); |
|||
void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg, u32 mask, u32 val); |
|||
#endif |
|||
|
|||
u16 pci_ext_read_config16(device_t nb_dev, device_t dev, u32 reg); |
|||
void pci_ext_write_config16(device_t nb_dev, device_t dev, u32 reg, u32 mask, u32 val); |
|||
|
|||
void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val); |
|||
void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val); |
|||
void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val); |
|||
void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val); |
|||
void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val); |
|||
void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val); |
|||
void rs780_set_tom(device_t nb_dev); |
|||
|
|||
void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add); |
|||
void enable_pcie_bar3(device_t nb_dev); |
|||
void disable_pcie_bar3(device_t nb_dev); |
|||
|
|||
void rs780_enable(device_t dev); |
|||
void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port); |
|||
void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port); |
|||
void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev); |
|||
void config_gpp_core(device_t nb_dev, device_t sb_dev); |
|||
void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port); |
|||
u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port); |
|||
#endif /* RS780_H */ |
|||
|
|||
|
|||
@ -0,0 +1,24 @@ |
|||
#ifndef _RS780_CHIP_H_ |
|||
#define _RS780_CHIP_H_ |
|||
|
|||
#include <sys/linux/types.h> |
|||
|
|||
|
|||
struct southbridge_amd_rs780_config |
|||
{ |
|||
u32 vga_rom_address; /* The location that the VGA rom has been appened. */ |
|||
u8 gppsb_configuration; /* The configuration of General Purpose Port, A/B/C/D/E. */ |
|||
u8 gpp_configuration; /* The configuration of General Purpose Port, C/D. */ |
|||
//u8 gpp_configuration; /* The configuration of General Purpose Port, A/B/C/D/E. */
|
|||
u16 port_enable; /* Which port is enabled? GFX(2,3), GPP(4,5,6,7) */ |
|||
u8 gfx_dev2_dev3; /* for GFX Core initialization REFCLK_SEL */ |
|||
u8 gfx_dual_slot; /* Is it dual graphics slots */ |
|||
u8 gfx_lane_reversal; /* Single/Dual slot lan reversal */ |
|||
u8 gfx_tmds; /* whether support TMDS? */ |
|||
u8 gfx_compliance; /* whether support compliance? */ |
|||
u8 gfx_reconfiguration; /* Dynamic Lind Width Control */ |
|||
u8 gfx_link_width; /* Desired width of lane 2 */ |
|||
}; |
|||
|
|||
#endif |
|||
|
|||
@ -0,0 +1,617 @@ |
|||
/*
|
|||
* This file is part of the coreboot project. |
|||
* |
|||
* Copyright (C) 2008 Advanced Micro Devices, Inc. |
|||
* |
|||
* This program is free software; you can redistribute it and/or modify |
|||
* it under the terms of the GNU General Public License as published by |
|||
* the Free Software Foundation; version 2 of the License. |
|||
* |
|||
* This program is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* GNU General Public License for more details. |
|||
* |
|||
* You should have received a copy of the GNU General Public License |
|||
* along with this program; if not, write to the Free Software |
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
|||
*/ |
|||
#include <time.h> |
|||
#include "rs780.h" |
|||
#include "rs780_cmn.h" |
|||
|
|||
#define HT_CONF_TYPE0_ADDR 0x90000efdfe000000 |
|||
//#define HT_MAP_TYPE0_CONF_ADDR 0xbfe80000
|
|||
#define HT_MAP_TYPE0_CONF_ADDR BONITO_PCICFG0_BASE_VA |
|||
|
|||
|
|||
typedef unsigned long long u64; |
|||
u32 pci_read_type0_config32(u32 dev, u32 func, u32 reg){ |
|||
//u64 addr = 0x90000efdfe000000;
|
|||
u32 addr = HT_MAP_TYPE0_CONF_ADDR; |
|||
|
|||
//printk("addr=%x,dev=%x, fn=%x, reg=%x\n", addr, dev, func, reg);
|
|||
|
|||
addr |= (dev << 11 | func << 8 | reg); |
|||
|
|||
return *((u32 *) addr); |
|||
} |
|||
|
|||
void pci_write_type0_config32(u32 dev, u32 func, u32 reg, u32 val){ |
|||
//u64 addr = 0x90000efdfe000000;
|
|||
u32 addr = HT_MAP_TYPE0_CONF_ADDR; |
|||
|
|||
//printk("addr=%x,dev=%x, fn=%x, reg=%x\n", addr, dev, func, reg);
|
|||
|
|||
addr |= (dev << 11 | func << 8 | reg); |
|||
|
|||
*((u32 *) addr) = val; |
|||
|
|||
} |
|||
|
|||
|
|||
#define HT_CONF_TYPE1_ADDR 0x90000efdff000000 |
|||
//#define HT_MAP_TYPE1_CONF_ADDR 0xbe000000
|
|||
#define HT_MAP_TYPE1_CONF_ADDR BONITO_PCICFG1_BASE_VA |
|||
|
|||
u32 pci_read_type1_config32(u32 bus, u32 dev, u32 func, u32 reg){ |
|||
//u64 addr = 0x90000efdff000000;
|
|||
u32 addr = HT_MAP_TYPE1_CONF_ADDR; |
|||
|
|||
//printk("addr=%x,bus=%x,dev=%x, fn=%x, reg=%x\n", addr, bus, dev, func, reg);
|
|||
|
|||
addr |= (bus << 16 | dev << 11 | func << 8 | reg); |
|||
|
|||
return *((u32 *) addr); |
|||
} |
|||
|
|||
void pci_write_type1_config32(u32 bus, u32 dev, u32 func, u32 reg, u32 val){ |
|||
//u64 addr = 0x90000efdff000000;
|
|||
u32 addr = HT_MAP_TYPE1_CONF_ADDR; |
|||
|
|||
|
|||
//printk("addr=%x,bus=%x,dev=%x, fn=%x, reg=%x\n", addr, bus, dev, func, reg);
|
|||
|
|||
addr |= (bus << 16 | dev << 11 | func << 8 | reg); |
|||
|
|||
*((u32 *) addr) = val; |
|||
} |
|||
|
|||
u32 _pci_conf_read(device_t tag,int reg) |
|||
{ |
|||
return _pci_conf_readn(tag,reg,4); |
|||
} |
|||
|
|||
|
|||
u32 _pci_conf_read32(device_t tag,int reg) |
|||
{ |
|||
return _pci_conf_readn(tag,reg,4); |
|||
} |
|||
|
|||
|
|||
u8 _pci_conf_read8(device_t tag,int reg) |
|||
{ |
|||
u32 data; |
|||
u32 offset; |
|||
u32 new_reg; |
|||
|
|||
new_reg = reg & 0xfc; |
|||
data = _pci_conf_readn(tag,new_reg,4); |
|||
offset = reg & 3; |
|||
data = data >> (offset * 8); |
|||
data &= 0xff; |
|||
|
|||
return (u8)data; |
|||
} |
|||
|
|||
u16 _pci_conf_read16(device_t tag,int reg) |
|||
{ |
|||
u32 data; |
|||
u32 offset; |
|||
u32 new_reg; |
|||
|
|||
new_reg = reg & 0xfc; |
|||
data = _pci_conf_readn(tag,new_reg,4); |
|||
offset = reg & 2; |
|||
data = data >> (offset << 3); |
|||
data &= 0xffff; |
|||
|
|||
return (u16)data; |
|||
} |
|||
|
|||
|
|||
|
|||
u32 _pci_conf_readn(device_t tag, int reg, int width) |
|||
{ |
|||
int bus, device, function; |
|||
|
|||
if ((width != 4) || (reg & 3) || reg < 0 || reg >= 0x100) { |
|||
printk("_pci_conf_readn: bad reg 0x%x, tag 0x%x, width 0x%x\n", reg, tag, width); |
|||
return ~0; |
|||
} |
|||
|
|||
_pci_break_tag (tag, &bus, &device, &function); |
|||
if (bus == 0) { |
|||
/* Type 0 configuration on onboard PCI bus */ |
|||
if (device > 31 || function > 7) |
|||
{ |
|||
printk("_pci_conf_readn: bad device 0x%x, function 0x%x\n", device, function); |
|||
return ~0; /* device out of range */ |
|||
} |
|||
return pci_read_type0_config32(device, function, reg); |
|||
} |
|||
else { |
|||
/* Type 1 configuration on offboard PCI bus */ |
|||
if (bus > 255 || device > 31 || function > 7) |
|||
{ |
|||
printk("_pci_conf_readn: bad bus 0x%x, device 0x%x, function 0x%x\n", bus, device, function); |
|||
return ~0; /* device out of range */ |
|||
} |
|||
return pci_read_type1_config32(bus, device, function, reg); |
|||
} |
|||
|
|||
} |
|||
void |
|||
_pci_conf_write(device_t tag, int reg, u32 data) |
|||
{ |
|||
return _pci_conf_writen(tag,reg,data,4); |
|||
} |
|||
|
|||
void |
|||
_pci_conf_write32(device_t tag, int reg, u32 data) |
|||
{ |
|||
return _pci_conf_writen(tag,reg,data,4); |
|||
} |
|||
|
|||
void |
|||
_pci_conf_write8(device_t tag, int reg, u8 data) |
|||
{ |
|||
return _pci_conf_writen(tag,reg,data,1); |
|||
} |
|||
|
|||
void |
|||
_pci_conf_write16(device_t tag, int reg, u16 data) |
|||
{ |
|||
return _pci_conf_writen(tag,reg,data,2); |
|||
} |
|||
|
|||
|
|||
|
|||
void _pci_conf_writen(device_t tag, int reg, u32 data,int width) |
|||
{ |
|||
int bus, device, function; |
|||
u32 ori; |
|||
u32 mask = 0x0; |
|||
|
|||
if ((reg & (width -1)) || reg < 0 || reg >= 0x100) { |
|||
printk("_pci_conf_writen: bad reg 0x%x, tag 0x%x, width 0x%x\n", reg, tag, width); |
|||
return; |
|||
} |
|||
|
|||
_pci_break_tag (tag, &bus, &device, &function); |
|||
|
|||
if (bus == 0) { |
|||
/* Type 0 configuration on onboard PCI bus */ |
|||
if (device > 31 || function > 7) |
|||
{ |
|||
printk("_pci_conf_writen: bad device 0x%x, function 0x%x\n", device, function); |
|||
return; /* device out of range */ |
|||
} |
|||
} |
|||
else { |
|||
/* Type 1 configuration on offboard PCI bus */ |
|||
if (bus > 255 || device > 31 || function > 7) |
|||
{ |
|||
printk("_pci_conf_writen: bad bus 0x%x, device 0x%x, function 0x%x\n", bus, device, function); |
|||
return; /* device out of range */ |
|||
} |
|||
} |
|||
|
|||
ori = _pci_conf_read(tag, reg & 0xfc); |
|||
if(width == 2){ |
|||
if(reg & 2){ |
|||
mask = 0xffff; |
|||
} |
|||
else{ |
|||
mask = 0xffff0000; |
|||
} |
|||
} |
|||
else if(width == 1){ |
|||
if ((reg & 3) == 1) { |
|||
mask = 0xffff00ff; |
|||
}else if ((reg & 3) == 2) { |
|||
mask = 0xff00ffff; |
|||
}else if ((reg & 3) == 3) { |
|||
mask = 0x00ffffff; |
|||
}else{ |
|||
mask = 0xffffff00; |
|||
} |
|||
} |
|||
|
|||
data = data << ((reg & 3) * 8); |
|||
data = (ori & mask) | data; |
|||
|
|||
|
|||
if (bus == 0) { |
|||
return pci_write_type0_config32(device, function, reg & 0xfc, data); |
|||
} |
|||
else { |
|||
return pci_write_type1_config32(bus, device, function, reg & 0xfc, data); |
|||
} |
|||
} |
|||
|
|||
static u32 nb_read_index(device_t tag, u32 index_reg, u32 index) |
|||
{ |
|||
pci_write_config32(tag, index_reg, index); |
|||
return pci_read_config32(tag, index_reg + 0x4); |
|||
} |
|||
|
|||
static void nb_write_index(device_t tag, u32 index_reg, u32 index, u32 data) |
|||
{ |
|||
|
|||
pci_write_config32(tag, index_reg, index); |
|||
pci_write_config32(tag, index_reg + 0x4, data); |
|||
|
|||
} |
|||
|
|||
#if 0 |
|||
|
|||
/* extension registers */ |
|||
u32 pci_ext_read_config32(device_t nb_tag, device_t tag, u32 reg) |
|||
{ |
|||
int bus, device, function; |
|||
/*get BAR3 base address for nbcfg0x1c */ |
|||
u32 addr = pci_read_config32(nb_tag, 0x1c) & ~0xF; |
|||
//_pci_tagprintf (nb_tag, "pci_ext_read_config32: addr=%x\n", addr);
|
|||
_pci_break_tag (tag, &bus, &device, &function); |
|||
addr |= bus << 20 | device << 15 | function << 12 | reg; |
|||
return *((u32 *) addr); |
|||
} |
|||
|
|||
void pci_ext_write_config32(device_t nb_tag, device_t tag, u32 reg_pos, u32 mask, u32 val) |
|||
{ |
|||
u32 reg_old, reg; |
|||
int bus, device, function; |
|||
|
|||
/*get BAR3 base address for nbcfg0x1c */ |
|||
u32 addr = pci_read_config32(nb_tag, 0x1c) & ~0xF; |
|||
|
|||
_pci_break_tag (tag, &bus, &device, &function); |
|||
addr |= bus << 20 | device << 15 | function << 12 | reg_pos; |
|||
|
|||
reg = reg_old = *((u32 *) addr); |
|||
reg &= ~mask; |
|||
reg |= val; |
|||
if (reg != reg_old) { |
|||
*((u32 *) addr) = val; |
|||
} |
|||
} |
|||
|
|||
#endif |
|||
|
|||
|
|||
/* extension registers */ |
|||
u16 pci_ext_read_config16(device_t nb_tag, device_t tag, u32 reg) |
|||
{ |
|||
u32 bus, dev, func, addr; |
|||
device_t bar3_tag = _pci_make_tag(0, 0, 0); |
|||
|
|||
_pci_break_tag(tag, &bus, &dev, &func); |
|||
|
|||
/*get BAR3 base address for nbcfg0x1c */ |
|||
addr = (_pci_conf_read(bar3_tag, 0x1c) & ~(0x0f))| 0x80000000; |
|||
addr |= bus << 20 | dev << 15 | func << 12 | reg; |
|||
addr |= 0x0e000000; //added by oldtai for the cpu win changed maybe cause ide not passing
|
|||
//printf("ext =========== addr=%x,bus=%x,dev=%x, fn=%x\n", addr, bus, dev, func);
|
|||
|
|||
return *((volatile u16 *) addr); |
|||
} |
|||
|
|||
void pci_ext_write_config16(device_t nb_tag, device_t tag, u32 reg_pos, u32 mask, u32 val) |
|||
{ |
|||
u32 bus, dev, func, addr; |
|||
device_t bar3_tag = _pci_make_tag(0, 0, 0); |
|||
|
|||
_pci_break_tag(tag, &bus, &dev, &func); |
|||
|
|||
/*get BAR3 base address for nbcfg0x1c */ |
|||
addr = (_pci_conf_read(bar3_tag, 0x1c) & ~(0x0f))| 0x80000000; |
|||
addr |= bus << 20 | dev << 15 | func << 12 | reg_pos; |
|||
addr |= 0x0e000000; //added by oldtai for the cpu win changed
|
|||
//printf("addr=%x,bus=%x,dev=%x, fn=%x\n", addr, bus, dev, func);
|
|||
*((volatile u16 *) addr) = val; |
|||
|
|||
} |
|||
|
|||
|
|||
u32 nbmisc_read_index(device_t nb_dev, u32 index) |
|||
{ |
|||
return nb_read_index((nb_dev), NBMISC_INDEX, (index)); |
|||
} |
|||
|
|||
void nbmisc_write_index(device_t nb_dev, u32 index, u32 data) |
|||
{ |
|||
nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data)); |
|||
} |
|||
|
|||
u32 nbpcie_p_read_index(device_t dev, u32 index) |
|||
{ |
|||
return nb_read_index((dev), NBPCIE_INDEX, (index)); |
|||
} |
|||
|
|||
void nbpcie_p_write_index(device_t dev, u32 index, u32 data) |
|||
{ |
|||
nb_write_index((dev), NBPCIE_INDEX, (index), (data)); |
|||
} |
|||
|
|||
u32 nbpcie_ind_read_index(device_t nb_dev, u32 index) |
|||
{ |
|||
return nb_read_index((nb_dev), NBPCIE_INDEX, (index)); |
|||
} |
|||
|
|||
void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data) |
|||
{ |
|||
nb_write_index((nb_dev), NBPCIE_INDEX, (index), (data)); |
|||
} |
|||
|
|||
u32 htiu_read_index(device_t nb_dev, u32 index) |
|||
{ |
|||
return nb_read_index((nb_dev), NBHTIU_INDEX, (index)); |
|||
} |
|||
|
|||
void htiu_write_index(device_t nb_dev, u32 index, u32 data) |
|||
{ |
|||
nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data)); |
|||
} |
|||
|
|||
u32 htiu_read_indexN(device_t nb_dev, u32 index) |
|||
{ |
|||
return nb_read_index((nb_dev), 0x94, (index)); |
|||
} |
|||
|
|||
void htiu_write_indexN(device_t nb_dev, u32 index, u32 data) |
|||
{ |
|||
nb_write_index((nb_dev), 0x94, ((index) | 0x100), (data)); |
|||
} |
|||
|
|||
u32 nbmc_read_index(device_t nb_dev, u32 index) |
|||
{ |
|||
return nb_read_index((nb_dev), NBMC_INDEX, (index)); |
|||
} |
|||
|
|||
void nbmc_write_index(device_t nb_dev, u32 index, u32 data) |
|||
{ |
|||
nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data)); |
|||
} |
|||
|
|||
void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val) |
|||
{ |
|||
u32 reg_old, reg; |
|||
reg = reg_old = pci_read_config32(nb_dev, reg_pos); |
|||
reg &= ~mask; |
|||
reg |= val; |
|||
if (reg != reg_old) { |
|||
pci_write_config32(nb_dev, reg_pos, reg); |
|||
} |
|||
} |
|||
|
|||
void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val) |
|||
{ |
|||
u8 reg_old, reg; |
|||
reg = reg_old = pci_read_config8(nb_dev, reg_pos); |
|||
reg &= ~mask; |
|||
reg |= val; |
|||
if (reg != reg_old) { |
|||
pci_write_config8(nb_dev, reg_pos, reg); |
|||
} |
|||
} |
|||
|
|||
void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val) |
|||
{ |
|||
u32 reg_old, reg; |
|||
reg = reg_old = nbmc_read_index(nb_dev, reg_pos); |
|||
reg &= ~mask; |
|||
reg |= val; |
|||
if (reg != reg_old) { |
|||
nbmc_write_index(nb_dev, reg_pos, reg); |
|||
} |
|||
} |
|||
|
|||
void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val) |
|||
{ |
|||
u32 reg_old, reg; |
|||
reg = reg_old = htiu_read_index(nb_dev, reg_pos); |
|||
reg &= ~mask; |
|||
reg |= val; |
|||
if (reg != reg_old) { |
|||
htiu_write_index(nb_dev, reg_pos, reg); |
|||
} |
|||
} |
|||
|
|||
void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val) |
|||
{ |
|||
u32 reg_old, reg; |
|||
reg = reg_old = nbmisc_read_index(nb_dev, reg_pos); |
|||
reg &= ~mask; |
|||
reg |= val; |
|||
if (reg != reg_old) { |
|||
nbmisc_write_index(nb_dev, reg_pos, reg); |
|||
} |
|||
} |
|||
|
|||
void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val) |
|||
{ |
|||
u32 reg_old, reg; |
|||
reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos); |
|||
reg &= ~mask; |
|||
reg |= val; |
|||
if (reg != reg_old) { |
|||
nb_write_index(dev, NBPCIE_INDEX, reg_pos, reg); |
|||
} |
|||
} |
|||
|
|||
void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port) |
|||
{ |
|||
switch (port) { |
|||
case 2: /* GFX, bit4-5 */ |
|||
case 3: |
|||
set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, |
|||
1 << (port + 2), 0 << (port + 2)); |
|||
break; |
|||
case 4: /* GPP, bit20-24 */ |
|||
case 5: |
|||
case 6: |
|||
case 7: |
|||
set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, |
|||
1 << (port + 17), 0 << (port + 17)); |
|||
break; |
|||
case 9: /* GPP, bit 4,5 of miscind 0x2D */ |
|||
case 10: |
|||
set_nbmisc_enable_bits(nb_dev, 0x2D, |
|||
1 << (port - 5), 0 << (port - 5)); |
|||
break; |
|||
} |
|||
} |
|||
|
|||
void set_pcie_dereset() |
|||
{ |
|||
u16 word; |
|||
device_t sm_dev; |
|||
|
|||
sm_dev = _pci_make_tag(0, 0x14, 0); |
|||
|
|||
word = pci_read_config16(sm_dev, 0xA8); |
|||
word |= (1 << 0) | (1 << 2); /* Set Gpio6,4 as output */ |
|||
word &= ~((1 << 8) | (1 << 10)); |
|||
//pci_write_config16(sm_dev, word, 0xA8);
|
|||
pci_write_config16(sm_dev, 0xA8, word); |
|||
} |
|||
|
|||
|
|||
void set_pcie_reset() |
|||
{ |
|||
u16 word; |
|||
device_t sm_dev; |
|||
|
|||
sm_dev = _pci_make_tag(0, 0x14, 0); |
|||
|
|||
word = pci_read_config16(sm_dev, 0xA8); |
|||
word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */ |
|||
word &= ~((1 << 8) | (1 << 10)); |
|||
pci_write_config16(sm_dev, 0xA8, word); |
|||
|
|||
} |
|||
|
|||
/********************************************************************************************************
|
|||
* Output: |
|||
* 0: no device is present. |
|||
* 1: device is present and is trained. |
|||
********************************************************************************************************/ |
|||
u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) |
|||
{ |
|||
u16 count = 5000; |
|||
u32 lc_state, reg; |
|||
u8 current, res = 0; |
|||
u32 gfx_gpp_sb_sel; |
|||
u32 current_link_width; |
|||
u32 lane_mask; |
|||
|
|||
//void set_pcie_dereset();
|
|||
//void set_pcie_reset();
|
|||
|
|||
switch (port) { |
|||
case 2 ... 3: |
|||
gfx_gpp_sb_sel = PCIE_CORE_INDEX_GFX; |
|||
break; |
|||
case 4 ... 7: |
|||
gfx_gpp_sb_sel = PCIE_CORE_INDEX_GPPSB; |
|||
break; |
|||
case 9 ... 10: |
|||
gfx_gpp_sb_sel = PCIE_CORE_INDEX_GPP; |
|||
break; |
|||
} |
|||
|
|||
while (count--) { |
|||
/* 5.7.5.21 step 2, delay 200us */ |
|||
udelay(300); |
|||
lc_state = nbpcie_p_read_index(dev, 0xa5); /* lc_state */ |
|||
printk_debug("PcieLinkTraining port=%x:lc current state=%x\n", |
|||
port, lc_state); |
|||
current = lc_state & 0x3f; /* get LC_CURRENT_STATE, bit0-5 */ |
|||
|
|||
switch (current) { |
|||
case 0x00: /* 0x00-0x04 means no device is present */ |
|||
case 0x01: |
|||
case 0x02: |
|||
case 0x03: |
|||
case 0x04: |
|||
res = 0; |
|||
count = 0; |
|||
break; |
|||
case 0x06: |
|||
/* read back current link width [6:4]. */ |
|||
current_link_width = (nbpcie_p_read_index(dev, 0xA2) >> 4) & 0x7; |
|||
/* 4 means 7:4 and 15:12
|
|||
* 3 means 7:2 and 15:10 |
|||
* 2 means 7:1 and 15:9 |
|||
* egnoring the reversal case |
|||
*/ |
|||
lane_mask = (0xFF << (current_link_width - 2) * 2) & 0xFF; |
|||
reg = nbpcie_ind_read_index(nb_dev, 0x65 | gfx_gpp_sb_sel); |
|||
reg |= lane_mask << 8 | lane_mask; |
|||
reg = 0xE0E0; /* TODO: See the comments in rs780_pcie.c, at about line 145. */ |
|||
nbpcie_ind_write_index(nb_dev, 0x65 | gfx_gpp_sb_sel, reg); |
|||
printk_debug("link_width=%x, lane_mask=%x", |
|||
current_link_width, lane_mask); |
|||
set_pcie_reset(); |
|||
delay(1); |
|||
set_pcie_dereset(); |
|||
break; |
|||
case 0x07: /* device is in compliance state (training sequence is doen). Move to train the next device */ |
|||
res = 1; /* TODO: CIM sets it to 0 */ |
|||
count = 0; |
|||
break; |
|||
case 0x10: |
|||
printk_info("PcieTrainPort reg\n"); |
|||
|
|||
/*
|
|||
* If access the pci_e express configure reg, should be |
|||
* enable the bar3 before, and close it when access done. |
|||
*/ |
|||
enable_pcie_bar3(nb_dev); |
|||
reg = pci_ext_read_config16(nb_dev, dev,PCIE_VC0_RESOURCE_STATUS); |
|||
disable_pcie_bar3(nb_dev); |
|||
printk_info("PcieTrainPort reg=0x%x\n", reg); |
|||
#if 0 |
|||
reg = |
|||
pci_ext_read_config32(nb_dev, dev, |
|||
PCIE_VC0_RESOURCE_STATUS); |
|||
printk_debug("PcieTrainPort reg=0x%x\n", reg); |
|||
#endif |
|||
/* check bit1 */ |
|||
if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ |
|||
/* set bit8=1, bit0-2=bit4-6 */ |
|||
u32 tmp; |
|||
reg = |
|||
nbpcie_p_read_index(dev, |
|||
PCIE_LC_LINK_WIDTH); |
|||
tmp = (reg >> 4) && 0x3; /* get bit4-6 */ |
|||
reg &= 0xfff8; /* clear bit0-2 */ |
|||
reg += tmp; /* merge */ |
|||
reg |= 1 << 8; |
|||
count++; /* CIM said "keep in loop"? */ |
|||
} else { |
|||
res = 1; |
|||
count = 0; |
|||
} |
|||
break; |
|||
default: /* reset pcie */ |
|||
res = 0; |
|||
count = 0; /* break loop */ |
|||
break; |
|||
} |
|||
} |
|||
return res; |
|||
} |
|||
|
|||
|
|||
@ -0,0 +1,73 @@ |
|||
#ifndef __RS780_CMN_H__ |
|||
#define __RS780_CMN_H__ |
|||
|
|||
#include <include/bonito.h> |
|||
#include "rs780.h" |
|||
|
|||
#define pci_read_config32(t, r) _pci_conf_read32((t), (r)) |
|||
#define pci_read_config16(t, r) _pci_conf_read16((t), (r)) |
|||
#define pci_read_config8(t, r) _pci_conf_read8((t), (r)) |
|||
|
|||
#define pci_write_config32(t, r, d) _pci_conf_write32((t), (r), (d)) |
|||
#define pci_write_config16(t, r, d) _pci_conf_write16((t), (r), (d)) |
|||
#define pci_write_config8(t, r, d) _pci_conf_write8((t), (r), (d)) |
|||
|
|||
extern void delay(int usec); |
|||
|
|||
#define udelay(m) delay(m) |
|||
|
|||
u32 pci_read_type0_config32(u32 dev, u32 func, u32 reg); |
|||
void pci_write_type0_config32(u32 dev, u32 func, u32 reg, u32 val); |
|||
u32 pci_read_type1_config32(u32 bus, u32 dev, u32 func, u32 reg); |
|||
void pci_write_type1_config32(u32 bus, u32 dev, u32 func, u32 reg, u32 val); |
|||
|
|||
u32 _pci_conf_read(device_t tag,int reg); |
|||
u32 _pci_conf_read32(device_t tag,int reg); |
|||
u16 _pci_conf_read16(device_t tag,int reg); |
|||
u8 _pci_conf_read8(device_t tag,int reg); |
|||
u32 _pci_conf_readn(device_t tag, int reg, int width); |
|||
|
|||
void _pci_conf_write(device_t tag, int reg, u32 data); |
|||
void _pci_conf_write32(device_t tag, int reg, u32 data); |
|||
void _pci_conf_write16(device_t tag, int reg, u16 data); |
|||
void _pci_conf_write8(device_t tag, int reg, u8 data); |
|||
void _pci_conf_writen(device_t tag, int reg, u32 data,int width); |
|||
|
|||
#define PM_INDEX (BONITO_PCIIO_BASE_VA + 0x0cd6) |
|||
#define PM_DATA (BONITO_PCIIO_BASE_VA + 0x0cd7) |
|||
#define PM2_INDEX (BONITO_PCIIO_BASE_VA + 0x0cd0) |
|||
#define PM2_DATA (BONITO_PCIIO_BASE_VA + 0x0cd1) |
|||
#define AB_INDX (BONITO_PCIIO_BASE_VA + 0x0CD8) |
|||
#define AB_DATA (AB_INDX + 4) |
|||
|
|||
|
|||
extern int printf (const char *fmt, ...); |
|||
|
|||
#define DAWNINGBLADE_DEBUG |
|||
#ifdef DAWNINGBLADE_DEBUG |
|||
#define printk_emerg(fmt, arg...) printf(fmt, ##arg) |
|||
#define printk_alert(fmt, arg...) printf(fmt, ##arg) |
|||
#define printk_crit(fmt, arg...) printf(fmt, ##arg) |
|||
#define printk_err(fmt, arg...) printf(fmt, ##arg) |
|||
#define printk_warning(fmt, arg...) printf(fmt, ##arg) |
|||
#define printk_notice(fmt, arg...) printf(fmt, ##arg) |
|||
#define printk_info(fmt, arg...) printf(fmt, ##arg) |
|||
#define printk_debug(fmt, arg...) printf(fmt, ##arg) |
|||
#define printk_spew(fmt, arg...) printf(fmt, ##arg) |
|||
#define printk(fmt, arg...) printf(fmt, ##arg) |
|||
#else |
|||
#define printk_emerg(fmt, arg...) |
|||
#define printk_alert(fmt, arg...) |
|||
#define printk_crit(fmt, arg...) |
|||
#define printk_err(fmt, arg...) |
|||
#define printk_warning(fmt, arg...) |
|||
#define printk_notice(fmt, arg...) |
|||
#define printk_info(fmt, arg...) |
|||
//#define printk_debug(fmt, arg...)
|
|||
/*notice:the printk_debug is important for the discrete card, don`t close it*/ |
|||
#define printk_debug(fmt, arg...) printf(fmt, ##arg) |
|||
#define printk_spew(fmt, arg...) |
|||
#define printk(fmt, arg...) |
|||
#endif |
|||
|
|||
#endif |
|||
File diff suppressed because it is too large
@ -0,0 +1,550 @@ |
|||
#include <unistd.h> |
|||
#include "rs780.h" |
|||
#include "rs780_chip.h" |
|||
|
|||
/*------------------------------------------------
|
|||
* Global variable |
|||
------------------------------------------------*/ |
|||
PCIE_CFG AtiPcieCfg = { |
|||
PCIE_ENABLE_STATIC_DEV_REMAP, /* Config */ |
|||
0, /* ResetReleaseDelay */ |
|||
0, /* Gfx0Width */ |
|||
0, /* Gfx1Width */ |
|||
0, /* GfxPayload */ |
|||
0, /* GppPayload */ |
|||
0, /* PortDetect, filled by GppSbInit */ |
|||
0, /* PortHp */ |
|||
0, /* DbgConfig */ |
|||
0, /* DbgConfig2 */ |
|||
0, /* GfxLx */ |
|||
0, /* GppLx */ |
|||
0, /* NBSBLx */ |
|||
0, /* PortSlotInit */ |
|||
0, /* Gfx0Pwr */ |
|||
0, /* Gfx1Pwr */ |
|||
0 /* GppPwr */ |
|||
}; |
|||
//get from mainboard\amd\mahogany\Config.lb
|
|||
struct southbridge_amd_rs780_config chip_info = { |
|||
0xfff0000, |
|||
4, |
|||
3, |
|||
0x6fc, |
|||
1, |
|||
1, |
|||
0, |
|||
0, |
|||
0, |
|||
1, |
|||
0 |
|||
}; |
|||
|
|||
static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port); |
|||
static void ValidatePortEn(device_t nb_dev); |
|||
|
|||
static void ValidatePortEn(device_t nb_dev) |
|||
{ |
|||
} |
|||
|
|||
#define PCIE_OFF_UNUSED_GPP_LANES (1 << 5) |
|||
#define PCIE_DISABLE_HIDE_UNUSED_PORTS (1 << 7) |
|||
#define PCIE_GFX_COMPLIANCE (1 << 14) |
|||
|
|||
|
|||
/*****************************************************************
|
|||
* Compliant with CIM_33's PCIEPowerOffGppPorts |
|||
* Power off unused GPP lines |
|||
*****************************************************************/ |
|||
static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port) |
|||
{ |
|||
u32 reg; |
|||
u16 state_save; |
|||
struct southbridge_amd_rs780_config *cfg = |
|||
// (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
|
|||
&chip_info; |
|||
u16 state = cfg->port_enable; |
|||
|
|||
if (!(AtiPcieCfg.Config & PCIE_DISABLE_HIDE_UNUSED_PORTS)) |
|||
state &= AtiPcieCfg.PortDetect; |
|||
state = ~state; |
|||
state &= (1 << 4) + (1 << 5) + (1 << 6) + (1 << 7); |
|||
state_save = state << 17; |
|||
state &= !(AtiPcieCfg.PortHp); |
|||
reg = nbmisc_read_index(nb_dev, 0x0c); |
|||
reg |= state; |
|||
nbmisc_write_index(nb_dev, 0x0c, reg); |
|||
|
|||
reg = nbmisc_read_index(nb_dev, 0x08); |
|||
reg |= state_save; |
|||
nbmisc_write_index(nb_dev, 0x08, reg); |
|||
|
|||
if ((AtiPcieCfg.Config & PCIE_OFF_UNUSED_GPP_LANES) |
|||
&& !(AtiPcieCfg. |
|||
Config & (PCIE_DISABLE_HIDE_UNUSED_PORTS + |
|||
PCIE_GFX_COMPLIANCE))) { |
|||
} |
|||
/* step 3 Power Down Control for Southbridge */ |
|||
printk_info("Power Down Control for Southbridge\n"); |
|||
reg = nbpcie_p_read_index(dev, 0xa2); |
|||
|
|||
switch ((reg >> 4) & 0x7) { /* get bit 4-6, LC_LINK_WIDTH_RD */ |
|||
case 1: |
|||
nbpcie_ind_write_index(nb_dev, 0x65, 0x0e0e); |
|||
break; |
|||
case 2: |
|||
nbpcie_ind_write_index(nb_dev, 0x65, 0x0c0c); |
|||
break; |
|||
default: |
|||
break; |
|||
} |
|||
} |
|||
|
|||
/**********************************************************************
|
|||
**********************************************************************/ |
|||
static void switching_gppsb_configurations(device_t nb_dev, device_t sb_dev) |
|||
{ |
|||
u32 reg; |
|||
struct southbridge_amd_rs780_config *cfg = |
|||
&chip_info; |
|||
/* 5.5.7.1-3 enables GPP reconfiguration */ |
|||
printk_info("enable GPP reconfiguration\n"); |
|||
reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7); |
|||
reg |= |
|||
(RECONFIG_GPPSB_EN + RECONFIG_GPPSB_LINK_CONFIG + |
|||
RECONFIG_GPPSB_ATOMIC_RESET); |
|||
nbmisc_write_index(nb_dev, PCIE_NBCFG_REG7, reg); |
|||
printk_info("De-asserts STRAP)BIF_all_valid for PCIE-GPPSB core\n"); |
|||
/* 5.5.7.4a. De-asserts STRAP_BIF_all_valid for PCIE-GPPSB core */ |
|||
reg = nbmisc_read_index(nb_dev, 0x66); |
|||
reg |= 1 << 31; |
|||
nbmisc_write_index(nb_dev, 0x66, reg); |
|||
printk_info("sets desired GPPSB configurations\n"); |
|||
/* 5.5.7.4b. sets desired GPPSB configurations, bit4-7 */ |
|||
reg = nbmisc_read_index(nb_dev, 0x67); |
|||
reg &= 0xFFFFff0f; /* clean */ |
|||
reg |= cfg->gppsb_configuration << 4; |
|||
nbmisc_write_index(nb_dev, 0x67, reg); |
|||
#if 1 |
|||
/* NOTE:
|
|||
* In CIMx 4.5.0 and RPR, 4c is done before 5 & 6. But in this way, |
|||
* a x4 device in port B (dev 4) of Configuration B can only be detected |
|||
* as x1, instead of x4. When the port B is being trained, the |
|||
* LC_CURRENT_STATE is 6 and the LC_LINK_WIDTH_RD is 1. We have |
|||
* to set the PCIEIND:0x65 as 0xE0E0 and reset the slot. Then the card |
|||
* seems to work in x1 mode. |
|||
* In the 2nd way below, we do the 5 & 6 before 4c. it conforms the |
|||
* CIMx 4.3.0. It conflicts with RPR. But based on the test result I've |
|||
* made so far, I haven't found any mistake. A coworker from Shanghai |
|||
* said it can not detect the x1 card when it first boots. I haven't got |
|||
* the result like this. |
|||
* The x4 device can work in both way, dont worry about it. We are just waiting |
|||
* for the chipset team to solve this problem. |
|||
*/ |
|||
/* 5.5.7.4c. Asserts STRAP_BIF_all_valid for PCIE-GPPSB core */ |
|||
printk_info("Asserts STRAP_BIF_all_valid for PCIE-GPPSB core\n"); |
|||
reg = nbmisc_read_index(nb_dev, 0x66); |
|||
reg &= ~(1 << 31); |
|||
nbmisc_write_index(nb_dev, 0x66, reg); |
|||
/* 5.5.7.5-6. read bit14 and write back its inverst value */ |
|||
printk_info("read bit14 and write back its inverst value\n"); |
|||
reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7); |
|||
reg ^= RECONFIG_GPPSB_GPPSB; |
|||
nbmisc_write_index(nb_dev, PCIE_NBCFG_REG7, reg); |
|||
#else |
|||
/* 5.5.7.5-6. read bit14 and write back its inverst value */ |
|||
reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7); |
|||
reg ^= RECONFIG_GPPSB_GPPSB; |
|||
nbmisc_write_index(nb_dev, PCIE_NBCFG_REG7, reg); |
|||
/* 5.5.7.4c. Asserts STRAP_BIF_all_valid for PCIE-GPPSB core */ |
|||
reg = nbmisc_read_index(nb_dev, 0x66); |
|||
reg &= ~(1 << 31); |
|||
nbmisc_write_index(nb_dev, 0x66, reg); |
|||
#endif |
|||
/* 5.5.7.7. delay 1ms */ |
|||
delay(1); |
|||
/* 5.5.7.8. waits until SB has trained to L0, poll for bit0-5 = 0x10 */ |
|||
printk_info("waits until SB has trained to L0, poll for bit0-5 = 0x10\n"); |
|||
do { |
|||
reg = nbpcie_p_read_index(sb_dev, PCIE_LC_STATE0); |
|||
reg &= 0x3f; /* remain LSB [5:0] bits */ |
|||
} while (LC_STATE_RECONFIG_GPPSB != reg); |
|||
#if 0 |
|||
/* 5.5.7.9.ensures that virtual channel negotiation is completed. poll for bit1 = 0 */ |
|||
printk_info("ensures that virtual channel negotiation is completed. poll for bit1 = 0\n"); |
|||
do { |
|||
reg = |
|||
pci_ext_read_config32(nb_dev, sb_dev, |
|||
PCIE_VC0_RESOURCE_STATUS); |
|||
} while (reg & VC_NEGOTIATION_PENDING); |
|||
#endif |
|||
|
|||
#if 1 |
|||
/* 5.5.7.9.ensures that virtual channel negotiation is completed. poll for bit1 = 0 */ |
|||
printk_info("ensures that virtual channel negotiation is completed. poll for bit1 = 0\n"); |
|||
do { |
|||
reg = |
|||
pci_ext_read_config16(nb_dev, sb_dev, |
|||
PCIE_VC0_RESOURCE_STATUS); |
|||
} while (reg & VC_NEGOTIATION_PENDING); |
|||
#endif |
|||
|
|||
} |
|||
|
|||
|
|||
|
|||
/**********************************************************************
|
|||
**********************************************************************/ |
|||
static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev) |
|||
{ |
|||
u32 reg; |
|||
struct southbridge_amd_rs780_config *cfg = |
|||
//(struct southbridge_amd_rs690_config *)nb_dev->chip_info;
|
|||
&chip_info; |
|||
/* 5.6.2.1. De-asserts STRAP_BIF_all_valid for PCIE-GPP core */ |
|||
printk("De-asserts STRAP_BIF_all_valid for PCIE-GPP core\n"); |
|||
reg = nbmisc_read_index(nb_dev, 0x22); |
|||
reg |= 1 << 14; |
|||
nbmisc_write_index(nb_dev, 0x22, reg); |
|||
printk("sets desired GPPSB configurations, bit4-7\n"); |
|||
/* 5.6.2.2. sets desired GPPSB configurations, bit4-7 */ |
|||
reg = nbmisc_read_index(nb_dev, 0x2D); |
|||
reg &= ~(0xF << 7); /* clean */ |
|||
reg |= cfg->gpp_configuration << 7; |
|||
nbmisc_write_index(nb_dev, 0x2D, reg); |
|||
printk("Asserts STRAP_BIF_all_valid for PCIE-GPP core\n"); |
|||
/* 5.6.2.3. Asserts STRAP_BIF_all_valid for PCIE-GPP core */ |
|||
reg = nbmisc_read_index(nb_dev, 0x22); |
|||
reg &= ~(1 << 14); |
|||
nbmisc_write_index(nb_dev, 0x22, reg); |
|||
} |
|||
|
|||
|
|||
|
|||
|
|||
/*****************************************************************
|
|||
* The rs690 uses NBCONFIG:0x1c (BAR3) to map the PCIE Extended Configuration |
|||
* Space to a 256MB range within the first 4GB of addressable memory. |
|||
*****************************************************************/ |
|||
void enable_pcie_bar3(device_t nb_dev) |
|||
{ |
|||
set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register. */ |
|||
set_nbcfg_enable_bits(nb_dev, 0x84, 7 << 16, 0 << 16); |
|||
|
|||
pci_write_config32(nb_dev, 0x1C, EXT_CONF_BASE_ADDRESS); /* PCIEMiscInit */ |
|||
pci_write_config32(nb_dev, 0x20, 0x00000000); |
|||
set_htiu_enable_bits(nb_dev, 0x32, 1 << 28, 1 << 28); /* PCIEMiscInit */ |
|||
} |
|||
|
|||
/*****************************************************************
|
|||
* We should disable bar3 when we want to exit rs690_enable, because bar3 will be |
|||
* remapped in set_resource later. |
|||
*****************************************************************/ |
|||
void disable_pcie_bar3(device_t nb_dev) |
|||
{ |
|||
printk_info("clear BAR3 address\n"); |
|||
pci_write_config32(nb_dev, 0x1C, 0); /* clear BAR3 address */ |
|||
printk_info("Disable writes to the BAR3\n"); |
|||
set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30); /* Disable writes to the BAR3. */ |
|||
} |
|||
|
|||
/*****************************************
|
|||
* Compliant with CIM_33's PCIEGPPInit |
|||
* nb_dev: |
|||
* root bridge struct |
|||
* dev: |
|||
* p2p bridge struct |
|||
* port: |
|||
* p2p bridge number, 4-8 |
|||
*****************************************/ |
|||
void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) |
|||
{ |
|||
u8 reg8; |
|||
u16 reg16; |
|||
device_t sb_dev; |
|||
//add for rs780
|
|||
u32 gfx_gpp_sb_sel; |
|||
|
|||
struct southbridge_amd_rs780_config *cfg = |
|||
//(struct southbridge_amd_rs690_config *)nb_dev->chip_info;
|
|||
&chip_info; |
|||
//add for rs780
|
|||
gfx_gpp_sb_sel = port >= 4 && port <= 8 ? |
|||
PCIE_CORE_INDEX_GPPSB : /* 4,5,6,7,8 */ |
|||
PCIE_CORE_INDEX_GPP; /* 9,10 */ |
|||
/* init GPP core */ |
|||
printk_info("init GPP core\n"); |
|||
printk_info("Disable slave ordering logic\n"); |
|||
set_pcie_enable_bits(nb_dev, 0x20 | gfx_gpp_sb_sel, 1 << 8, |
|||
1 << 8); |
|||
/* PCIE initialization 5.10.2: rpr 2.12*/ |
|||
printk_info("PCIE initialization\n"); |
|||
set_pcie_enable_bits(nb_dev, 0x02 | gfx_gpp_sb_sel, 1 << 0, 1 << 0); /* no description in datasheet. */ |
|||
|
|||
/* init GPPSB port. rpr 5.10.8 */ |
|||
/* 5.10.8.1-5.10.8.2. Sets RCB timeout to be 100ms/4=25ms by setting bits[18:16] to 3 h4
|
|||
* and shortens the enumeration timer by setting bit[19] to 1 |
|||
*/ |
|||
printk_info("init GPPSB port.\n"); |
|||
set_pcie_enable_bits(dev, 0x70, 0xF << 16, 0x4 << 16 | 1 << 19); |
|||
/* 5.10.8.4. Sets DMA payload size to 64 bytes. */ |
|||
printk_info("Sets DMA payload size to 64 bytes\n"); |
|||
set_pcie_enable_bits(nb_dev, 0x10 | gfx_gpp_sb_sel, 7 << 10, 4 << 10); |
|||
/* 5.10.8.6. Disable RC ordering logic */ |
|||
printk_info("Disable RC ordering logic\n"); |
|||
set_pcie_enable_bits(nb_dev, 0x20 | gfx_gpp_sb_sel, 1 << 9, 1 << 9); |
|||
/* 5.10.8.7. Ignores DLLs druing L1 */ |
|||
printk_info("Ignores DLLs druing L1\n"); |
|||
set_pcie_enable_bits(nb_dev, 0x02 | gfx_gpp_sb_sel, 1 << 0, 1 << 0); |
|||
/* 5.10.8.8. Prevents LCto go from L0 to Rcv_L0s if L1 is armed. */ |
|||
printk_info("Prevents LCto go from L0 to Rcv_L0s if L1 is armed\n"); |
|||
set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11); |
|||
/* 5.10.8.9. Sets timer in Config state from 20us to 1us.
|
|||
* 5.10.8.10. De-asserts RX_EN in L0s |
|||
* 5.10.8.11. Enables de-assertion of PG2RX_CR_EN to lock clock recovery parameter when .. */ |
|||
printk_info("Sets timer in Config state from 20us to 1us\n"); |
|||
set_pcie_enable_bits(dev, 0xB1, 1 << 23 | 1 << 19 | 1 << 28, 1 <<23 | 1 << 19 | 1 << 28); |
|||
/* 5.10.8.12. Turns off offset calibration */ |
|||
/* 5.10.8.13. Enables Rx Clock gating in CDR */ |
|||
printk_info("Turns off offset calibration\n"); |
|||
if (gfx_gpp_sb_sel == PCIE_CORE_INDEX_GPPSB) |
|||
set_nbmisc_enable_bits(nb_dev, 0x67, 1 << 14 | 1 << 26, 1 << 14 | 1 << 26); /* 4,5,6,7 */ |
|||
else |
|||
set_nbmisc_enable_bits(nb_dev, 0x24, 1 << 29 | 1 << 28, 1 << 29 | 1 << 28); /* 9,10 */ |
|||
/* 5.10.8.14. Sets number of TX Clocks to drain TX Pipe to 3 */ |
|||
printk_info("Sets number of TX Clocks to drain TX Pipe to 3\n"); |
|||
set_pcie_enable_bits(dev, 0xA0, 0xF << 4, 0x3 << 4); |
|||
/* 5.10.8.15. empty */ |
|||
/* 5.10.8.16. P_ELEC_IDLE_MODE */ |
|||
printk_info("empty\n"); |
|||
set_pcie_enable_bits(nb_dev, 0x40 | gfx_gpp_sb_sel, 0x3 << 14, 0x2 << 14); |
|||
/* 5.10.8.17. LC_BLOCK_EL_IDLE_IN_L0 */ |
|||
printk_info("LC_BLOCK_EL_IDLE_IN_L0\n"); |
|||
set_pcie_enable_bits(dev, 0xB1, 1 << 20, 1 << 20); |
|||
/* 5.10.8.18. LC_DONT_GO_TO_L0S_IFL1_ARMED */ |
|||
printk_info("LC_DONT_GO_TO_L0S_IFL1_ARMED\n"); |
|||
set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11); |
|||
/* 5.10.8.19. RXP_REALIGN_ON_EACH_TSX_OR_SKP */ |
|||
printk_info("RXP_REALIGN_ON_EACH_TSX_OR_SKP\n"); |
|||
set_pcie_enable_bits(nb_dev, 0x40 | gfx_gpp_sb_sel, 1 << 28, 0 << 28); |
|||
/* 5.10.8.20. Bypass lane de-skew logic if in x1 */ |
|||
printk_info("Bypass lane de-skew logic if in x1\n"); |
|||
set_pcie_enable_bits(nb_dev, 0xC2 | gfx_gpp_sb_sel, 1 << 14, 1 << 14); |
|||
/* 5.10.8.21. sets electrical idle threshold. */ |
|||
printk_info("sets electrical idle threshold\n"); |
|||
if (gfx_gpp_sb_sel == PCIE_CORE_INDEX_GPPSB) |
|||
set_nbmisc_enable_bits(nb_dev, 0x6A, 3 << 22, 2 << 22); |
|||
else |
|||
set_nbmisc_enable_bits(nb_dev, 0x24, 3 << 16, 2 << 16); |
|||
/* 5.10.8.22. Disable GEN2 */ |
|||
/* TODO: should be 2 seperated cases. */ |
|||
printk_info("Disable GEN2\n"); |
|||
set_nbmisc_enable_bits(nb_dev, 0x39, 1 << 31, 0 << 31); |
|||
set_nbmisc_enable_bits(nb_dev, 0x22, 1 << 5, 0 << 5); |
|||
set_nbmisc_enable_bits(nb_dev, 0x34, 1 << 31, 0 << 31); |
|||
set_nbmisc_enable_bits(nb_dev, 0x37, 7 << 5, 0 << 5); |
|||
/* 5.10.8.23. Disables GEN2 capability of the device. RPR says enable? No! */ |
|||
printk_info("Disables GEN2 capability of the device\n"); |
|||
set_pcie_enable_bits(dev, 0xA4, 1 << 0, 0 << 0); |
|||
/* 5.10.8.24. Disable advertising upconfigure support. */ |
|||
printk_info("Disable advertising upconfigure support\n"); |
|||
set_pcie_enable_bits(dev, 0xA2, 1 << 13, 1 << 13); |
|||
/* 5.10.8.25-26. STRAP_BIF_DSN_EN */ |
|||
printk_info("STRAP_BIF_DSN_EN\n"); |
|||
if (gfx_gpp_sb_sel == PCIE_CORE_INDEX_GPPSB) |
|||
set_nbmisc_enable_bits(nb_dev, 0x68, 1 << 19, 0 << 19); |
|||
else |
|||
set_nbmisc_enable_bits(nb_dev, 0x22, 1 << 3, 0 << 3); |
|||
/* 5.10.8.27-28. */ |
|||
printk_info(" 5.10.8.27-28\n"); |
|||
set_pcie_enable_bits(nb_dev, 0xC1 | gfx_gpp_sb_sel, 1 << 0 | 1 << 2, 1 << 0 | 0 << 2); |
|||
/* 5.10.8.29. Uses the bif_core de-emphasis strength by default. */ |
|||
printk_info("Uses the bif_core de-emphasis strength by default\n"); |
|||
if (gfx_gpp_sb_sel == PCIE_CORE_INDEX_GPPSB) { |
|||
set_nbmisc_enable_bits(nb_dev, 0x67, 1 << 10, 1 << 10); |
|||
set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 29, 1 << 29); |
|||
} |
|||
else { |
|||
set_nbmisc_enable_bits(nb_dev, 0x39, 1 << 30, 1 << 30); |
|||
} |
|||
/* 5.10.8.30. Set TX arbitration algorithm to round robin. */ |
|||
printk_info("Set TX arbitration algorithm to round robin\n"); |
|||
set_pcie_enable_bits(nb_dev, 0x1C | gfx_gpp_sb_sel, |
|||
1 << 0 | 0x1F << 1 | 0x1F << 6, |
|||
1 << 0 | 0x04 << 1 | 0x04 << 6); |
|||
/* check compliance rpr step 2.1*/ |
|||
printk_info("check compliance\n"); |
|||
if (AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE) { |
|||
u32 tmp; |
|||
tmp = nbmisc_read_index(nb_dev, 0x67); |
|||
tmp |= 1 << 3; |
|||
nbmisc_write_index(nb_dev, 0x67, tmp); |
|||
} |
|||
|
|||
/* step 5: dynamic slave CPL buffer allocation. Disable it, otherwise linux hangs. Why? */ |
|||
/* set_pcie_enable_bits(nb_dev, 0x20 | gfx_gpp_sb_sel, 1 << 11, 1 << 11); */ |
|||
/* step 5a: Training for GPP devices */ |
|||
/* init GPP */ |
|||
switch (port) { |
|||
case 4: /* GPP */ |
|||
case 5: |
|||
case 6: |
|||
case 7: |
|||
case 9: |
|||
case 10: |
|||
/* 5.10.8.5. Blocks DMA traffic during C3 state */ |
|||
printk_info("Blocks DMA traffic during C3 state\n"); |
|||
set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0); |
|||
/* Enabels TLP flushing */ |
|||
printk_info("Enabels TLP flushing\n"); |
|||
set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19); |
|||
/* check port enable */ |
|||
printk_info("check port enable\n"); |
|||
if (cfg->port_enable & (1 << port)) { |
|||
// if(1){
|
|||
PcieReleasePortTraining(nb_dev, dev, port); |
|||
if (!(AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE)) { |
|||
u8 res = PcieTrainPort(nb_dev, dev, port); |
|||
printk_debug("PcieTrainPort port=0x%x result=%d\n", port, res); |
|||
if (res) { |
|||
AtiPcieCfg.PortDetect |= 1 << port; |
|||
} |
|||
} |
|||
} |
|||
break; |
|||
case 8: /* SB */ |
|||
break; |
|||
} |
|||
PciePowerOffGppPorts(nb_dev, dev, port); |
|||
/* step 5b: GFX devices in a GPP slot */ |
|||
#if 0 |
|||
/* step 6a: VCI */ |
|||
sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0)); |
|||
if (port == 8) { |
|||
/* Clear bits 7:1 */ |
|||
pci_ext_write_config32(nb_dev, sb_dev, 0x114, 0x3f << 1, 0 << 1); |
|||
/* Maps Traffic Class 1-7 to VC1 */ |
|||
pci_ext_write_config32(nb_dev, sb_dev, 0x120, 0x7f << 1, 0x7f << 1); |
|||
/* Assigns VC ID to 1 */ |
|||
pci_ext_write_config32(nb_dev, sb_dev, 0x120, 7 << 24, 1 << 24); |
|||
/* Enables VC1 */ |
|||
pci_ext_write_config32(nb_dev, sb_dev, 0x120, 1 << 31, 1 << 31); |
|||
#if 0 |
|||
do { |
|||
reg16 = pci_ext_read_config32(nb_dev, sb_dev, 0x124); |
|||
reg16 &= 0x2; |
|||
} while (reg16); /*bit[1] = 0 means VC1 flow control initialization is successful */ |
|||
#endif |
|||
} |
|||
#endif |
|||
#if 0 |
|||
/* step 6b: L0s for the southbridge link */ |
|||
/* To enalbe L0s in the southbridage*/ |
|||
/* step 6c: L0s for the GPP link(s) */ |
|||
/* To eable L0s in the RS780 for the GPP port(s) */ |
|||
printk_info("To enalbe L0s in the southbridage\n"); |
|||
set_pcie_enable_bits(nb_dev, 0xf9, 3 << 13, 2 << 13); |
|||
set_pcie_enable_bits(dev, 0xa0, 0xf << 8, 0x9 << 8); |
|||
reg16 = pci_read_config16(dev, 0x68); |
|||
reg16 |= 1 << 0; |
|||
pci_write_config16(dev, 0x68, reg16); |
|||
/* step 6d: ASPM L1 for the southbridge link */ |
|||
/* To enalbe L1s in the southbridage*/ |
|||
/* step 6e: ASPM L1 for GPP link(s) */; |
|||
printk_info("To enalbe L1s in the southbridage\n"); |
|||
set_pcie_enable_bits(nb_dev, 0xf9, 3 << 13, 2 << 13); |
|||
set_pcie_enable_bits(dev, 0xa0, 3 << 12, 3 << 12); |
|||
set_pcie_enable_bits(dev, 0xa0, 0xf << 4, 3 << 4); |
|||
reg16 = pci_read_config16(dev, 0x68); |
|||
reg16 &= ~0xff; |
|||
reg16 |= 1 << 1; |
|||
pci_write_config16(dev, 0x68, reg16); |
|||
/* step 6f: Turning off PLL during L1/L23 */ |
|||
printk_info("Turning off PLL during L1/L23\n"); |
|||
set_pcie_enable_bits(nb_dev, 0x40, 1 << 3, 1 << 3); |
|||
set_pcie_enable_bits(nb_dev, 0x40, 1 << 9, 1 << 9); |
|||
/* step 6g: TXCLK clock gating */ |
|||
set_nbmisc_enable_bits(nb_dev, 0x7, 3 << 4, 3 << 4); |
|||
set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 22, 1 << 22); |
|||
set_pcie_enable_bits(nb_dev, 0x11, 0xf << 4, 0xc << 4); |
|||
#endif |
|||
/* step 6h: LCLK clock gating, done in rs780_config_misc_clk() */ |
|||
} |
|||
|
|||
|
|||
/*****************************************
|
|||
* Compliant with CIM_33's PCIEConfigureGPPCore |
|||
*****************************************/ |
|||
void config_gpp_core(device_t nb_dev, device_t sb_dev) |
|||
{ |
|||
u32 reg; |
|||
struct southbridge_amd_rs780_config *cfg = |
|||
//(struct southbridge_amd_rs690_config *)nb_dev->chip_info;
|
|||
&chip_info; |
|||
printk_info("enter config_gpp_core\n"); |
|||
reg = nbmisc_read_index(nb_dev, 0x20); |
|||
if (AtiPcieCfg.Config & PCIE_ENABLE_STATIC_DEV_REMAP) |
|||
reg &= 0xfffffffd; /* set bit1 = 0 */ |
|||
else |
|||
reg |= 0x2; /* set bit1 = 1 */ |
|||
nbmisc_write_index(nb_dev, 0x20, reg); |
|||
|
|||
printk_info("get STRAP_BIF_LINK_CONFIG_GPPSB\n"); |
|||
reg = nbmisc_read_index(nb_dev, 0x67); /* get STRAP_BIF_LINK_CONFIG_GPPSB at bit 4-7 */ |
|||
if (cfg->gppsb_configuration != ((reg >> 4) & 0xf)) |
|||
//switching_gpp_configurations(nb_dev, sb_dev);
|
|||
switching_gppsb_configurations(nb_dev, sb_dev); |
|||
printk_info("get STRAP_BIF_LINK_CONFIG_GPP\n"); |
|||
reg = nbmisc_read_index(nb_dev, 0x2D); /* get STRAP_BIF_LINK_CONFIG_GPP at bit 7-10 */ |
|||
if (cfg->gpp_configuration != ((reg >> 7) & 0xf)) |
|||
switching_gpp_configurations(nb_dev, sb_dev); |
|||
ValidatePortEn(nb_dev); |
|||
printk_info("exit config_gpp_core\n"); |
|||
} |
|||
|
|||
/*****************************************
|
|||
* Compliant with CIM_33's PCIEMiscClkProg |
|||
*****************************************/ |
|||
void pcie_config_misc_clk(device_t nb_dev) |
|||
{ |
|||
u32 reg; |
|||
//struct bus pbus; /* fake bus for dev0 fun1 */
|
|||
|
|||
reg = pci_read_config32(nb_dev, 0x4c); |
|||
reg |= 1 << 0; |
|||
pci_write_config32(nb_dev, 0x4c, reg); |
|||
|
|||
if (AtiPcieCfg.Config & PCIE_GFX_CLK_GATING) { |
|||
/* TXCLK Clock Gating */ |
|||
set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 0, 3 << 0); |
|||
set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 22, 1 << 22); |
|||
set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GFX, (3 << 6) | (~0xf), 3 << 6); |
|||
|
|||
/* LCLK Clock Gating */ |
|||
//reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
|
|||
reg = pci_read_config32(_pci_make_tag(0, 0, 1), 0x94); |
|||
reg &= ~(1 << 16); |
|||
//pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
|
|||
pci_write_config32(_pci_make_tag(0, 0, 1), 0x94, reg); |
|||
} |
|||
|
|||
if (AtiPcieCfg.Config & PCIE_GPP_CLK_GATING) { |
|||
/* TXCLK Clock Gating */ |
|||
set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 4, 3 << 4); |
|||
set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 22, 1 << 22); |
|||
set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GPPSB, (3 << 6) | (~0xf), 3 << 6); |
|||
|
|||
/* LCLK Clock Gating */ |
|||
//reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
|
|||
reg = pci_read_config32(_pci_make_tag(0, 0, 1), 0x94); |
|||
reg &= ~(1 << 24); |
|||
//pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
|
|||
pci_write_config32(_pci_make_tag(0, 0, 1), 0x94, reg); |
|||
} |
|||
|
|||
reg = pci_read_config32(nb_dev, 0x4c); |
|||
reg &= ~(1 << 0); |
|||
pci_write_config32(nb_dev, 0x4c, reg); |
|||
} |
|||
|
|||
|
|||
|
|||
@ -0,0 +1,180 @@ |
|||
#include "sb700.h" |
|||
#include "rs780_cmn.h" |
|||
|
|||
#define NULL (void*)0 |
|||
|
|||
void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val) |
|||
{ |
|||
u32 reg_old, reg; |
|||
reg = reg_old = pci_read_config32(sm_dev, reg_pos); |
|||
reg &= ~mask; |
|||
reg |= val; |
|||
if (reg != reg_old) { |
|||
pci_write_config32(sm_dev, reg_pos, reg); |
|||
} |
|||
} |
|||
|
|||
static void pmio_write_index(u32 port_base, u8 reg, u8 value) |
|||
{ |
|||
OUTB(reg, port_base); |
|||
OUTB(value, port_base + 1); |
|||
} |
|||
|
|||
static u8 pmio_read_index(u32 port_base, u8 reg) |
|||
{ |
|||
OUTB(reg, port_base); |
|||
return INB(port_base + 1); |
|||
} |
|||
|
|||
void pm_iowrite(u8 reg, u8 value) |
|||
{ |
|||
printk_info("pm_iowrite\n"); |
|||
pmio_write_index(PM_INDEX, reg, value); |
|||
} |
|||
|
|||
u8 pm_ioread(u8 reg) |
|||
{ |
|||
printk_info("pm_ioread\n"); |
|||
return pmio_read_index(PM_INDEX, reg); |
|||
} |
|||
|
|||
void pm2_iowrite(u8 reg, u8 value) |
|||
{ |
|||
printk_info("pm2_iowrite\n"); |
|||
pmio_write_index(PM2_INDEX, reg, value); |
|||
} |
|||
|
|||
u8 pm2_ioread(u8 reg) |
|||
{ |
|||
printk_info("pm2_ioread\n"); |
|||
return pmio_read_index(PM2_INDEX, reg); |
|||
} |
|||
|
|||
static void set_pmio_enable_bits(device_t sm_dev, u32 reg_pos, |
|||
u32 mask, u32 val) |
|||
{ |
|||
u8 reg_old, reg; |
|||
reg = reg_old = pm_ioread(reg_pos); |
|||
reg &= ~mask; |
|||
reg |= val; |
|||
if (reg != reg_old) { |
|||
pm_iowrite(reg_pos, reg); |
|||
} |
|||
} |
|||
|
|||
void sb700_sata(int enabled) |
|||
{ |
|||
device_t sm_dev; |
|||
int index = 8; |
|||
|
|||
sm_dev = _pci_make_tag(0, 0x14, 0); |
|||
set_sm_enable_bits(sm_dev, 0xac, 1 << index, (enabled ? 1 : 0) << index); |
|||
} |
|||
|
|||
|
|||
void sb700_usb(device_t usb_dev, int enabled, int index) |
|||
{ |
|||
device_t sm_dev; |
|||
//int index;
|
|||
//int function;
|
|||
|
|||
//_pci_break_tag(usb_dev, NULL, NULL, &function);
|
|||
//index = (function + 1) % 6;
|
|||
|
|||
sm_dev = _pci_make_tag(0, 0x14, 0); |
|||
set_sm_enable_bits(sm_dev, 0x68, 1 << index, (enabled ? 1 : 0) << index); |
|||
} |
|||
|
|||
void sb700_hda(int enabled) |
|||
{ |
|||
device_t sm_dev; |
|||
int index = 3; |
|||
|
|||
sm_dev = _pci_make_tag(0, 0x14, 0); |
|||
set_pmio_enable_bits(sm_dev, 0x59, 1 << index, (enabled ? 1 : 0) << index); |
|||
} |
|||
|
|||
|
|||
void sb700_lpc(int enabled) |
|||
{ |
|||
device_t sm_dev; |
|||
int index = 20; |
|||
|
|||
sm_dev = _pci_make_tag(0, 0x14, 0); |
|||
set_sm_enable_bits(sm_dev, 0x64, 1 << index, (enabled ? 1 : 0) << index); |
|||
} |
|||
|
|||
void sb700_aci(device_t dev, int enabled) |
|||
{ |
|||
device_t sm_dev; |
|||
int index; |
|||
int function; |
|||
|
|||
_pci_break_tag(dev, NULL, NULL, &function); |
|||
index = function - 5; |
|||
sm_dev = _pci_make_tag(0, 0x14, 0); |
|||
set_pmio_enable_bits(sm_dev, 0x59, 1 << index, (enabled ? 1 : 0) << index); |
|||
} |
|||
|
|||
|
|||
void sb700_mci(device_t dev, int enabled) |
|||
{ |
|||
device_t sm_dev; |
|||
int index; |
|||
int function; |
|||
|
|||
_pci_break_tag(dev, NULL, NULL, &function); |
|||
index = function - 5; |
|||
sm_dev = _pci_make_tag(0, 0x14, 0); |
|||
set_pmio_enable_bits(sm_dev, 0x59, 1 << index, (enabled ? 1 : 0) << index); |
|||
} |
|||
|
|||
|
|||
|
|||
void sb700_enable() |
|||
{ |
|||
/*
|
|||
* 0:11.0 SATA bit 8 of sm_dev 0xac : 1 - enable, default + 32 * 3 |
|||
* 0:12.0 OHCI0-USB1 bit 0 of sm_dev 0x68 |
|||
* 0:12.1 OHCI1-USB1 bit 1 of sm_dev 0x68 |
|||
* 0:12.2 EHCI-USB1 bit 2 of sm_dev 0x68 |
|||
* 0:13.0 OHCI0-USB2 bit 4 of sm_dev 0x68 |
|||
* 0:13.1 OHCI1-USB2 bit 5 of sm_dev 0x68 |
|||
* 0:13.2 EHCI-USB2 bit 6 of sm_dev 0x68 |
|||
* 0:14.5 OHCI0-USB3 bit 7 of sm_dev 0x68 |
|||
* 0:14.0 SMBUS 0 |
|||
* 0:14.1 IDE 1 |
|||
* 0:14.2 HDA bit 3 of pm_io 0x59 : 1 - enable, default + 32 * 4 |
|||
* 0:14.3 LPC bit 20 of sm_dev 0x64 : 0 - disable, default + 32 * 1 |
|||
* 0:14.4 PCI 4 |
|||
*/ |
|||
#ifdef ENABLE_SATA |
|||
printk_info("enable_sata\n"); |
|||
sb700_sata(1); |
|||
#endif |
|||
|
|||
printk_info("enable usb0\n"); |
|||
sb700_usb(_pci_make_tag(0, 0x12, 0), 1, 0); |
|||
|
|||
printk_info("enable usb1\n"); |
|||
sb700_usb(_pci_make_tag(0, 0x12, 1), 1, 1); |
|||
#if 1 |
|||
//printk_info("enable usb2\n");
|
|||
//sb700_usb(_pci_make_tag(0, 0x12, 2), 1, 2);
|
|||
printk_info("enable usb4\n"); |
|||
sb700_usb(_pci_make_tag(0, 0x13, 0), 1, 4); |
|||
printk_info("enable usb5\n"); |
|||
sb700_usb(_pci_make_tag(0, 0x13, 1), 1, 5); |
|||
//printk_info("enable usb6\n");
|
|||
//sb700_usb(_pci_make_tag(0, 0x13, 2), 1, 6);
|
|||
printk_info("enable usb7\n"); |
|||
sb700_usb(_pci_make_tag(0, 0x14, 5), 1, 7); |
|||
#endif |
|||
//printk_info("enable hda\n");
|
|||
//sb700_hda(1);
|
|||
printk_info("enable lpc\n"); |
|||
sb700_lpc(1); |
|||
//sb700_aci(_pci_make_tag(0, 0x14, 5), 1);
|
|||
//sb700_mci(_pci_make_tag(0, 0x14, 6), 1);
|
|||
} |
|||
|
|||
@ -0,0 +1,42 @@ |
|||
#ifndef _SB700_H_ |
|||
#define _SB700_H_ |
|||
|
|||
#include "sb700_chip.h" |
|||
|
|||
//#define NULL (void*)0
|
|||
|
|||
typedef unsigned long device_t; |
|||
|
|||
#if 1 |
|||
#define INB(addr) (*(volatile unsigned char *) (addr)) |
|||
#define INW(addr) (*(volatile unsigned short *) (addr)) |
|||
#define INL(addr) (*(volatile unsigned int *) (addr)) |
|||
|
|||
#define OUTB(b,addr) (*(volatile unsigned char *) (addr) = (b)) |
|||
#define OUTW(b,addr) (*(volatile unsigned short *) (addr) = (b)) |
|||
#define OUTL(b,addr) (*(volatile unsigned int *) (addr) = (b)) |
|||
|
|||
#define WRITEB(val, addr) (*(volatile u8*)(addr) = (val)) |
|||
#define WRITEW(val, addr) (*(volatile u16*)(addr) = (val)) |
|||
#define WRITEL(val, addr) (*(volatile u32*)(addr) = (val)) |
|||
#define READB(addr) (*(volatile u8*)(addr)) |
|||
#define READW(addr) (*(volatile u16*)(addr)) |
|||
#define READL(addr) (*(volatile u32*)(addr)) |
|||
|
|||
#endif |
|||
|
|||
//typedef unsigned long pcitag_t;
|
|||
|
|||
extern device_t _pci_make_tag(int, int, int); |
|||
extern void _pci_break_tag(device_t, int *, int *, int *); |
|||
|
|||
extern void pm_iowrite(u8 reg, u8 value); |
|||
extern u8 pm_ioread(u8 reg); |
|||
extern void pm2_iowrite(u8 reg, u8 value); |
|||
extern u8 pm2_ioread(u8 reg); |
|||
extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val); |
|||
|
|||
extern void sb700_enable(); |
|||
|
|||
|
|||
#endif |
|||
@ -0,0 +1,16 @@ |
|||
#ifndef _SB700_CHIP_H_ |
|||
#define _SB700_CHIP_H_ |
|||
|
|||
#include <sys/linux/types.h> |
|||
|
|||
|
|||
|
|||
struct southbridge_amd_sb700_config |
|||
{ |
|||
u32 ide0_enable : 1; |
|||
u32 sata0_enable : 1; |
|||
u32 hda_viddid; |
|||
}; |
|||
|
|||
#endif |
|||
|
|||
@ -0,0 +1,45 @@ |
|||
#include "sb700.h" |
|||
#include "rs780_cmn.h" |
|||
|
|||
static void ide_init(device_t dev) |
|||
{ |
|||
/* Enable ide devices so the linux ide driver will work */ |
|||
u32 dword; |
|||
u8 byte; |
|||
|
|||
/* RPR10.1 disable MSI */ |
|||
printk_info("disable MSI\n"); |
|||
dword = pci_read_config32(dev, 0x70); |
|||
dword &= ~(1 << 16); |
|||
pci_write_config32(dev, 0x70, dword); |
|||
#if 1 |
|||
/* Ultra DMA mode */ |
|||
/* enable UDMA */ |
|||
printk_info("enable UDMA\n"); |
|||
byte = pci_read_config8(dev, 0x54); |
|||
byte |= 1 << 0; |
|||
pci_write_config8(dev, 0x54, byte); |
|||
#endif |
|||
/* Enable I/O Access&& Bus Master */ |
|||
printk_info("enable I/O Access bus master"); |
|||
dword = pci_read_config16(dev, 0x4); |
|||
//dword |= ((1 << 2)|(1 << 0));
|
|||
dword |= (1 << 2); |
|||
pci_write_config16(dev, 0x4, dword); |
|||
#if 0 |
|||
/* Set a default latency timer. */ |
|||
pci_write_config8(dev, 0x0d, 0x40); //PCI_LATENCY_TIMER
|
|||
|
|||
byte = pci_read_config8(dev, 0x3d); //PCI_INTERRUPT_PIN
|
|||
if (byte) { |
|||
pci_write_config8(dev, 0x3c, 0); //PCI_INTERRUPT_LINE
|
|||
} |
|||
/* Set the cache line size, so far 64 bytes is good for everyone. */ |
|||
pci_write_config8(dev, 0x0c, 64 >> 2); //PCI_CACHE_LINE_SIZE
|
|||
#endif |
|||
//#if CONFIG_PCI_ROM_RUN == 1
|
|||
// pci_dev_init(dev);
|
|||
//#endif
|
|||
|
|||
} |
|||
|
|||
@ -0,0 +1,88 @@ |
|||
#include "sb700.h" |
|||
#include "rs780_cmn.h" |
|||
|
|||
|
|||
#define DMA1_RESET_REG 0x0D /* Master Clear (w) */ |
|||
|
|||
#define DMA2_RESET_REG 0xDA /* Master Clear (w) */ |
|||
#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ |
|||
#define DMA2_MODE_REG 0xD6 /* mode register (w) */ |
|||
|
|||
#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ |
|||
|
|||
#define INB(addr) (*(volatile unsigned char *) (addr)) |
|||
#define INW(addr) (*(volatile unsigned short *) (addr)) |
|||
#define INL(addr) (*(volatile unsigned int *) (addr)) |
|||
|
|||
#define OUTB(b,addr) (*(volatile unsigned char *) (addr) = (b)) |
|||
#define OUTW(b,addr) (*(volatile unsigned short *) (addr) = (b)) |
|||
#define OUTL(b,addr) (*(volatile unsigned int *) (addr) = (b)) |
|||
|
|||
|
|||
static void isa_dma_init(void) |
|||
{ |
|||
/* slave at 0x00 - 0x0f */ |
|||
/* master at 0xc0 - 0xdf */ |
|||
/* 0x80 - 0x8f DMA page registers */ |
|||
/* DMA: 0x00, 0x02, 0x4, 0x06 base address for DMA channel */ |
|||
OUTB(0, DMA1_RESET_REG); |
|||
OUTB(0, DMA2_RESET_REG); |
|||
OUTB(DMA_MODE_CASCADE, DMA2_MODE_REG); |
|||
OUTB(0, DMA2_MASK_REG); |
|||
} |
|||
|
|||
|
|||
static void lpc_init(device_t dev) |
|||
{ |
|||
u8 byte; |
|||
u32 dword; |
|||
device_t sm_dev; |
|||
|
|||
/* Enable the LPC Controller */ |
|||
printk_info("Enable the LPC Controller\n"); |
|||
//sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
|
|||
sm_dev = _pci_make_tag(0, 0x14, 0); |
|||
dword = pci_read_config32(sm_dev, 0x64); |
|||
dword |= 1 << 20; |
|||
pci_write_config32(sm_dev, 0x64, dword); |
|||
|
|||
/* Initialize isa dma */ |
|||
//printk_info("Initialize isa dma\n");
|
|||
//isa_dma_init();
|
|||
|
|||
/* RPR 7.2 Enable DMA transaction on the LPC bus */ |
|||
printk_info("Enable DMA transaction on the LPC bus\n"); |
|||
byte = pci_read_config8(dev, 0x40); |
|||
byte |= (1 << 2); |
|||
pci_write_config8(dev, 0x40, byte); |
|||
|
|||
/* RPR 7.3 Disable the timeout mechanism on LPC */ |
|||
printk_info("Disable the timeout mechanism on LPC\n"); |
|||
byte = pci_read_config8(dev, 0x48); |
|||
byte &= ~(1 << 7); |
|||
pci_write_config8(dev, 0x48, byte); |
|||
|
|||
/* RPR 7.5 Disable LPC MSI Capability */ |
|||
printk_info("Disable LPC MSI Capability\n"); |
|||
byte = pci_read_config8(dev, 0x78); |
|||
byte &= ~(1 << 1); |
|||
pci_write_config8(dev, 0x78, byte); |
|||
#if 0
|
|||
//add by lycheng
|
|||
printk_info("IO/Mem Decoding\n"); |
|||
byte = pci_read_config8(dev, 0xbb); |
|||
byte |= ((1<<3)|(1<<6)|(1<<7)); |
|||
pci_write_config8(dev, 0xbb, byte); |
|||
|
|||
/* Set a default latency timer. */ |
|||
pci_write_config8(dev, 0x0d, 0x40); //PCI_LATENCY_TIMER
|
|||
|
|||
byte = pci_read_config8(dev, 0x3d); //PCI_INTERRUPT_PIN
|
|||
if (byte) { |
|||
pci_write_config8(dev, 0x3c, 0); //PCI_INTERRUPT_LINE
|
|||
} |
|||
/* Set the cache line size, so far 64 bytes is good for everyone. */ |
|||
pci_write_config8(dev, 0x0c, 64 >> 2); //PCI_CACHE_LINE_SIZE
|
|||
#endif |
|||
} |
|||
|
|||
@ -0,0 +1,113 @@ |
|||
#include "sb700.h" |
|||
#include "rs780_cmn.h" |
|||
|
|||
static void pci_init(device_t dev) |
|||
{ |
|||
u32 dword; |
|||
u16 word; |
|||
u8 byte; |
|||
|
|||
/* RPR 5.1 Enables the PCI-bridge subtractive decode */ |
|||
/* This setting is strongly recommended since it supports some legacy PCI add-on cards,such as BIOS debug cards */ |
|||
printk_info("Enables the PCI-bridge subtractive decode\n"); |
|||
byte = pci_read_config8(dev, 0x4B); |
|||
byte |= 1 << 7; |
|||
pci_write_config8(dev, 0x4B, byte); |
|||
byte = pci_read_config8(dev, 0x40); |
|||
byte |= 1 << 5; |
|||
pci_write_config8(dev, 0x40, byte); |
|||
|
|||
//vga pci card support //lycheng
|
|||
/* PCI Command: Enable IO response */ |
|||
byte = pci_read_config8(dev, 0x04); |
|||
byte |= (1 << 0)|(1 << 5)|(1 << 1)|(1 << 2); |
|||
pci_write_config8(dev, 0x04, byte); |
|||
/* PCI Command: VGA enable */ |
|||
byte = pci_read_config8(dev, 0x3e); |
|||
byte |= (1 << 3); |
|||
pci_write_config8(dev, 0x3e, byte); |
|||
//end vga pci card support
|
|||
|
|||
|
|||
/* RPR5.2 PCI-bridge upstream dual address window */ |
|||
/* this setting is applicable if the system memory is more than 4GB,and the PCI device can support dual address access */ |
|||
printk_info("PCI-bridge upstream dual address window\n"); |
|||
byte = pci_read_config8(dev, 0x50); |
|||
//byte |= 1 << 0;
|
|||
byte &= ~(1 << 0); |
|||
pci_write_config8(dev, 0x50, byte); |
|||
|
|||
/* RPR 5.3 PCI bus 64-byte DMA read access */ |
|||
/* Enhance the PCI bus DMA performance */ |
|||
printk_info("PCI bus 64-byte DMA read access\n"); |
|||
byte = pci_read_config8(dev, 0x4B); |
|||
byte |= 1 << 4; |
|||
pci_write_config8(dev, 0x4B, byte); |
|||
|
|||
/* RPR 5.4 Enables the PCIB writes to be cacheline aligned. */ |
|||
/* The size of the writes will be set in the Cacheline Register */ |
|||
printk_info("Enables the PCIB writes to be cacheline aligned.\n"); |
|||
byte = pci_read_config8(dev, 0x40); |
|||
byte |= 1 << 1; |
|||
pci_write_config8(dev, 0x40, byte); |
|||
|
|||
/* RPR 5.5 Enables the PCIB to retain ownership of the bus on the Primary side and on the Secondary side when GNT# is deasserted */ |
|||
printk_info("Enables the PCIB to retain ownership of the bus\n"); |
|||
pci_write_config8(dev, 0x0D, 0x40); |
|||
pci_write_config8(dev, 0x1B, 0x40); |
|||
|
|||
/* RPR 5.6 Enable the command matching checking function on "Memory Read" & "Memory Read Line" commands */ |
|||
printk_info("Enable the command matching checking function\n"); |
|||
byte = pci_read_config8(dev, 0x4B); |
|||
byte |= 1 << 6; |
|||
pci_write_config8(dev, 0x4B, byte); |
|||
|
|||
/* RPR 5.7 When enabled, the PCI arbiter checks for the Bus Idle before asserting GNT# */ |
|||
printk_info("the PCI arbiter checks for the Bus Idle before asserting GNT#\n"); |
|||
byte = pci_read_config8(dev, 0x4B); |
|||
byte |= 1 << 0; |
|||
pci_write_config8(dev, 0x4B, byte); |
|||
|
|||
/* RPR 5.8 Adjusts the GNT# de-assertion time */ |
|||
printk_info("Adjusts the GNT# de-assertion time\n"); |
|||
word = pci_read_config16(dev, 0x64); |
|||
word |= 1 << 12; |
|||
pci_write_config16(dev, 0x64, word); |
|||
|
|||
/* RPR 5.9 Fast Back to Back transactions support */ |
|||
printk_info("Fast Back to Back transactions support\n"); |
|||
byte = pci_read_config8(dev, 0x48); |
|||
byte |= 1 << 2; |
|||
/* pci_write_config8(dev, 0x48, byte); */ |
|||
|
|||
/* RPR 5.10 Enable Lock Operation */ |
|||
/* byte = pci_read_config8(dev, 0x48); */ |
|||
byte |= 1 << 3; |
|||
pci_write_config8(dev, 0x48, byte); |
|||
|
|||
/* RPR 5.11 Enable additional optional PCI clock */ |
|||
printk_info("Enable additional optional PCI clock\n"); |
|||
word = pci_read_config16(dev, 0x64); |
|||
word |= 1 << 8; |
|||
pci_write_config16(dev, 0x64, word); |
|||
|
|||
/* RPR 5.12 Enable One-Prefetch-Channel Mode */ |
|||
printk_info("Enable One-Prefetch-Channel Mode\n"); |
|||
dword = pci_read_config32(dev, 0x64); |
|||
dword |= 1 << 20; |
|||
pci_write_config32(dev, 0x64, dword); |
|||
|
|||
/* RPR 5.13 Disable PCIB MSI Capability */ |
|||
printk_info("Disable PCIB MSI Capability\n"); |
|||
byte = pci_read_config8(dev, 0x40); |
|||
byte &= ~(1 << 3); |
|||
pci_write_config8(dev, 0x40, byte); |
|||
|
|||
/* rpr5.14 Adjusting CLKRUN# */ |
|||
printk_info("Adjusting CLKRUN\n"); |
|||
dword = pci_read_config32(dev, 0x64); |
|||
dword |= (1 << 15); |
|||
pci_write_config32(dev, 0x64, dword); |
|||
} |
|||
|
|||
|
|||
@ -0,0 +1,290 @@ |
|||
#include "sb700.h" |
|||
#include "rs780_cmn.h" |
|||
|
|||
#if 0 |
|||
#define writeb(val, addr) (*(volatile u8*)(addr) = (val)) |
|||
#define writew(val, addr) (*(volatile u16*)(addr) = (val)) |
|||
#define writel(val, addr) (*(volatile u32*)(addr) = (val)) |
|||
#define readb(addr) (*(volatile u8*)(addr)) |
|||
#define readw(addr) (*(volatile u16*)(addr)) |
|||
#define readl(addr) (*(volatile u32*)(addr)) |
|||
#endif |
|||
|
|||
extern struct southbridge_ati_sb700_config conf_info; |
|||
|
|||
|
|||
#if 0 |
|||
static sata_drive_detect(int portnum, u32 iobar) |
|||
{ |
|||
u8 byte, byte2; |
|||
int i = 0; |
|||
OUTB(0xA0 + 0x10 * (portnum % 2), iobar + 0x6); |
|||
while (byte = INB(iobar + 0x6), byte2 = INB(iobar + 0x7), |
|||
(byte != (0xA0 + 0x10 * (portnum % 2))) || |
|||
((byte2 & 0x88) != 0)) { |
|||
printk_spew("0x6=%x, 0x7=%x\n", byte, byte2); |
|||
if (byte != (0xA0 + 0x10 * (portnum % 2))) { |
|||
/* This will happen at the first iteration of this loop
|
|||
* if the first SATA port is unpopulated and the |
|||
* second SATA port is poulated. |
|||
*/ |
|||
printk_debug("drive no longer selected after %d ms, " |
|||
"retrying init\n", i * 10); |
|||
return 1; |
|||
} else |
|||
printk_spew("drive detection not yet completed, " |
|||
"waiting...\n"); |
|||
udelay(10000); |
|||
i++; |
|||
} |
|||
printk_spew("drive detection done after %d ms\n", i * 10); |
|||
return 0; |
|||
} |
|||
#endif |
|||
|
|||
static void sata_init(device_t dev) |
|||
{ |
|||
u8 byte; |
|||
u16 word; |
|||
u32 dword; |
|||
u32 sata_bar5; |
|||
u32 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4; |
|||
int i, j; |
|||
u8 rev_id; |
|||
|
|||
struct southbridge_ati_sb700_config *conf = &conf_info; |
|||
|
|||
device_t sm_dev; |
|||
/* SATA SMBus Disable */ |
|||
/* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */ |
|||
//sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
|
|||
sm_dev = _pci_make_tag(0, 0x14, 0); |
|||
|
|||
/* Disable SATA SMBUS */ |
|||
printk_info("Disable SATA SMBUS\n"); |
|||
byte = pci_read_config8(sm_dev, 0xad); |
|||
byte |= (1 << 1); |
|||
//pci_write_config8(sm_dev, 0xad, byte); //coreboot didn't do write action
|
|||
|
|||
/* Enable SATA and power saving */ |
|||
printk_info("Enable SATA and power saving\n"); |
|||
byte = pci_read_config8(sm_dev, 0xad); |
|||
byte |= (1 << 0); |
|||
byte |= (1 << 5); |
|||
pci_write_config8(sm_dev, 0xad, byte); |
|||
/* Set the interrupt Mapping to INTG# */ |
|||
printk_info("Set the interrupt Mapping to INTG#\n"); |
|||
byte = pci_read_config8(sm_dev, 0xaf); |
|||
byte = 0x6 << 2; |
|||
pci_write_config8(sm_dev, 0xaf, byte); |
|||
|
|||
//add for sb700
|
|||
/* get rev_id */ |
|||
rev_id = pci_read_config8(sm_dev, 0x08) - 0x28; |
|||
|
|||
/* get base addresss */ |
|||
printk_info("get base address\n"); |
|||
sata_bar5 = (pci_read_config32(dev, 0x24) & ~0x3FF); |
|||
sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7; |
|||
sata_bar1 = pci_read_config16(dev, 0x14) & ~0x7; |
|||
sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7; |
|||
sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x7; |
|||
sata_bar4 = pci_read_config16(dev, 0x20) & ~0x7; |
|||
|
|||
printk_spew("sata_bar0=%x\n", sata_bar0); /* 3030 */ |
|||
printk_spew("sata_bar1=%x\n", sata_bar1); /* 3070 */ |
|||
printk_spew("sata_bar2=%x\n", sata_bar2); /* 3040 */ |
|||
printk_spew("sata_bar3=%x\n", sata_bar3); /* 3080 */ |
|||
printk_spew("sata_bar4=%x\n", sata_bar4); /* 3000 */ |
|||
printk_spew("sata_bar5=%x\n", sata_bar5); /* e0309000 */ |
|||
|
|||
#if 0 /* All SATA(six) interfaces work correctly in combined mode,
|
|||
* other didn't. |
|||
*/ |
|||
//add for sb700
|
|||
/* disable combined mode to */ |
|||
printk_info("disable combined mode to\n"); |
|||
byte = pci_read_config8(sm_dev, 0xAD); |
|||
byte &= ~(1 << 3); |
|||
pci_write_config8(sm_dev, 0xAD, byte); |
|||
#endif |
|||
|
|||
/* Program the 2C to 0x43801002 */ |
|||
printk_info("Program the 2C to 0x43801002\n"); |
|||
dword = 0x43801002; |
|||
pci_write_config32(dev, 0x2c, dword); |
|||
|
|||
/* SERR-Enable */ |
|||
printk_info("serr-enable\n"); |
|||
word = pci_read_config16(dev, 0x04); |
|||
word |= (1 << 8); |
|||
pci_write_config16(dev, 0x04, word); |
|||
|
|||
/* Dynamic power saving */ |
|||
printk_info("Dynamic power saving\n"); |
|||
byte = pci_read_config8(dev, 0x40); |
|||
byte |= (1 << 2); |
|||
pci_write_config8(dev, 0x40, byte); |
|||
|
|||
/* Set SATA Operation Mode, Set to IDE mode */ |
|||
printk("Set SATA operation mode, set to IDE mode\n"); |
|||
byte = pci_read_config8(dev, 0x40); |
|||
byte |= (1 << 0); |
|||
byte |= (1 << 4); |
|||
pci_write_config8(dev, 0x40, byte); |
|||
|
|||
dword = 0x01018f00; //bit[8]:1, Native PCI-mode, 0, Compability mode; bit[10]:1, Native PCI-mode, 0, Compability mode
|
|||
//dword = 0x01018a00;
|
|||
pci_write_config32(dev, 0x8, dword); |
|||
|
|||
byte = pci_read_config8(dev, 0x40); |
|||
byte &= ~(1 << 0); |
|||
pci_write_config8(dev, 0x40, byte); |
|||
|
|||
/* Enable the SATA watchdog counter */ |
|||
printk_info("Enable the SATA watchdog counter\n"); |
|||
byte = pci_read_config8(dev, 0x44); |
|||
byte |= (1 << 0); |
|||
pci_write_config8(dev, 0x44, byte); |
|||
|
|||
//add for sb700
|
|||
/* Set bit 29 and 24 for A12 */ |
|||
dword = pci_read_config32(dev, 0x40); |
|||
if (rev_id < 0x14) /* before A12 */ |
|||
dword |= (1 << 29); |
|||
else |
|||
dword &= ~(1 << 29); /* A14 and above */ |
|||
pci_write_config32(dev, 0x40, dword); |
|||
/* set bit 21 for A12 */ |
|||
dword = pci_read_config32(dev, 0x48); |
|||
if (rev_id < 0x14) /* before A12 */ |
|||
dword |= 1 << 24 | 1 << 21; |
|||
else { |
|||
dword &= ~(1 << 24 | 1 << 21); /* A14 and above */ |
|||
dword &= ~0xFF80; /* 15:7 */ |
|||
dword |= 1 << 15 | 0x7F << 7; |
|||
} |
|||
pci_write_config32(dev, 0x48, dword); |
|||
|
|||
|
|||
/* Program the watchdog counter to 0x10 */ |
|||
printk_info("Program the watchdog counter to 0x10\n"); |
|||
byte = 0x10; |
|||
pci_write_config8(dev, 0x46, byte); |
|||
|
|||
/* RPR6.5 Program the PHY Global Control to 0x2C00 for A13 */ |
|||
printk_info("Program the PHY Global Control to 0x2C00 for A13\n"); |
|||
word = 0x2c00; |
|||
pci_write_config16(dev, 0x86, word); |
|||
/* RPR7.6.2 SATA GENI PHY ports setting */ |
|||
printk_info("sata geni phy ports setting\n"); |
|||
pci_write_config32(dev, 0x88, 0x01B48017); |
|||
pci_write_config32(dev, 0x8c, 0x01B48016); |
|||
pci_write_config32(dev, 0x90, 0x01B48016); |
|||
pci_write_config32(dev, 0x94, 0x01B48016); |
|||
pci_write_config32(dev, 0x98, 0x01B48016); |
|||
pci_write_config32(dev, 0x9C, 0x01B48016); |
|||
|
|||
/* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */ |
|||
printk_info("sata gen II PHY port setting for port\n"); |
|||
pci_write_config16(dev, 0xA0, 0xA09A); |
|||
pci_write_config16(dev, 0xA2, 0xA09A); |
|||
pci_write_config16(dev, 0xA4, 0xA07A); |
|||
pci_write_config16(dev, 0xA6, 0xA07A); |
|||
pci_write_config16(dev, 0xA8, 0xA07A); |
|||
pci_write_config16(dev, 0xAA, 0xA07A); |
|||
|
|||
/* Enable the I/O, MM, BusMaster access for SATA */ |
|||
printk_info("Enable the I/O, MM, BusMaster access for SATA\n"); |
|||
byte = pci_read_config8(dev, 0x4); |
|||
byte |= 7 << 0; |
|||
pci_write_config8(dev, 0x4, byte); |
|||
/* RPR6.6 SATA drive detection. */ |
|||
/* Use BAR5+0x128,BAR0 for Primary Slave */ |
|||
/* Use BAR5+0x1A8,BAR0 for Primary Slave */ |
|||
/* Use BAR5+0x228,BAR2 for Secondary Master */ |
|||
/* Use BAR5+0x2A8,BAR2 for Secondary Slave */ |
|||
#ifdef EANBLE_SATA |
|||
|
|||
sata_bar5 = sata_bar5 | 0x80000000; |
|||
sata_bar0 = sata_bar0 | 0xb8000000; |
|||
sata_bar2 = sata_bar2 | 0xb8000000; |
|||
for (i = 0; i < 4; i++) { |
|||
byte = READB(sata_bar5 + 0x128 + 0x80 * i); |
|||
printk_spew("SATA port %d status = %x\n", i, byte); |
|||
byte &= 0xF; |
|||
|
|||
if( byte == 0x1 ) { |
|||
/* If the drive status is 0x1 then we see it but we aren't talking to it. */ |
|||
/* Try to do something about it. */ |
|||
printk_spew("SATA device detected but not talking. Trying lower speed.\n"); |
|||
|
|||
/* Read in Port-N Serial ATA Control Register */ |
|||
byte = READB(sata_bar5 + 0x12C + 0x80 * i); |
|||
|
|||
/* Set Reset Bit and 1.5g bit */ |
|||
byte |= 0x11; |
|||
WRITEB(byte, (sata_bar5 + 0x12C + 0x80 * i)); |
|||
|
|||
/* Wait 1ms */ |
|||
delay(1 * 1000); |
|||
|
|||
/* Clear Reset Bit */ |
|||
byte &= ~0x01; |
|||
WRITEB(byte, (sata_bar5 + 0x12C + 0x80 * i)); |
|||
|
|||
/* Wait 1ms */ |
|||
delay(1 * 1000); |
|||
|
|||
/* Reread status */ |
|||
byte = READB(sata_bar5 + 0x128 + 0x80 * i); |
|||
printk_spew("SATA port %d status = %x\n", i, byte); |
|||
byte &= 0xF; |
|||
} |
|||
|
|||
if (byte == 0x3) { |
|||
for (j = 0; j < 10; j++) { |
|||
if (!sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2)) |
|||
break; |
|||
} |
|||
printk_debug("%s %s device is %sready after %d tries\n", |
|||
(i / 2) ? "Secondary" : "Primary", |
|||
(i % 2 ) ? "Slave" : "Master", |
|||
(j == 10) ? "not " : "", |
|||
(j == 10) ? j : j + 1); |
|||
} else { |
|||
printk_debug("No %s %s SATA drive on Slot%d\n", |
|||
(i / 2) ? "Secondary" : "Primary", |
|||
(i % 2 ) ? "Slave" : "Master", i); |
|||
} |
|||
} |
|||
#endif |
|||
|
|||
#if 0 |
|||
/* Below is CIM InitSataLateFar */ |
|||
/* Enable interrupts from the HBA */ |
|||
printk_info("Enable interrupts from the HBA\n"); |
|||
byte = READB(sata_bar5 + 0x4); |
|||
byte |= 1 << 1; |
|||
WRITEB(byte, (sata_bar5 + 0x4)); |
|||
/* Clear error status */ |
|||
printk_info("Clear error status\n"); |
|||
WRITEL(0xFFFFFFFF, (sata_bar5 + 0x130)); |
|||
WRITEL(0xFFFFFFFF, (sata_bar5 + 0x1b0)); |
|||
WRITEL(0xFFFFFFFF, (sata_bar5 + 0x230)); |
|||
WRITEL(0xFFFFFFFF, (sata_bar5 + 0x2b0)); |
|||
WRITEL(0xFFFFFFFF, (sata_bar5 + 0x330)); |
|||
WRITEL(0xFFFFFFFF, (sata_bar5 + 0x3b0)); |
|||
#endif |
|||
|
|||
/* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */ |
|||
/* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */ |
|||
|
|||
/* word = 0x0000; */ |
|||
/* word = pm_ioread(0x28); */ |
|||
/* byte = pm_ioread(0x29); */ |
|||
/* word |= byte<<8; */ |
|||
/* printk_debug("AcpiGpe0Blk addr = %x\n", word); */ |
|||
/* writel(0x80000000 , word); */ |
|||
} |
|||
|
|||
@ -0,0 +1,257 @@ |
|||
#include "sb700.h" |
|||
#include "rs780_cmn.h" |
|||
|
|||
#include "sb700_smbus.c" |
|||
|
|||
/*
|
|||
* SB600 enables all USB controllers by default in SMBUS Control. |
|||
* SB600 enables SATA by default in SMBUS Control. |
|||
*/ |
|||
static void sm_init(device_t dev) |
|||
{ |
|||
u8 byte; |
|||
u8 byte_old; |
|||
u32 dword; |
|||
u32 ioapic_base; |
|||
u32 on; |
|||
u32 nmi_option; |
|||
|
|||
printk_info("sm_init().\n"); |
|||
|
|||
//ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0); /* some like mem resource, but does not have enable bit */
|
|||
//setup_ioapic(ioapic_base);
|
|||
|
|||
dword = pci_read_config8(dev, 0x62); |
|||
dword |= 1 << 2; |
|||
pci_write_config8(dev, 0x62, dword); |
|||
|
|||
printk_info("enable 0xCD6 0xCD7\n"); |
|||
dword = pci_read_config32(dev, 0x78); |
|||
dword |= 1 << 9; |
|||
pci_write_config32(dev, 0x78, dword); /* enable 0xCD6 0xCD7 */ |
|||
#if 0 |
|||
//add by lycheng
|
|||
printk_info("clear sata and ide controller into combined mode\n"); |
|||
printk_info("PATA is primary\n"); |
|||
dword = pci_read_config32(dev, 0xAD); |
|||
dword |= (1 << 4); |
|||
dword &= ~(1 << 3); |
|||
pci_write_config32(dev, 0xAD, dword); |
|||
#endif |
|||
/* bit 10: MultiMediaTimerIrqEn */ |
|||
printk_info("MultiMediaTimerIrqEn\n"); |
|||
dword = pci_read_config8(dev, 0x64); |
|||
dword |= 1 << 10; |
|||
pci_write_config8(dev, 0x64, dword); |
|||
|
|||
/* enable serial irq */ |
|||
printk_info("enable serial irq\n"); |
|||
byte = pci_read_config8(dev, 0x69); |
|||
byte |= 1 << 7; /* enable serial irq function */ |
|||
byte &= ~(0xF << 2); |
|||
byte |= 4 << 2; /* set NumSerIrqBits=4 */ |
|||
pci_write_config8(dev, 0x69, byte); |
|||
#if 1 |
|||
printk_info("Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7\n"); |
|||
byte = pm_ioread(0x61); |
|||
byte |= 1 << 1; /* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */ |
|||
pm_iowrite(0x61, byte); |
|||
|
|||
/* disable SMI */ |
|||
printk_info("disable SMI\n"); |
|||
byte = pm_ioread(0x53); |
|||
byte |= 1 << 3; |
|||
pm_iowrite(0x53, byte); |
|||
|
|||
/* power after power fail */ |
|||
//on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
|
|||
//get_option(&on, "power_on_after_fail");
|
|||
printk_info("power after power fail\n"); |
|||
on = 0; |
|||
byte = pm_ioread(0x74); |
|||
byte &= ~0x03; |
|||
if (on) { |
|||
byte |= 2; |
|||
} |
|||
byte |= 1 << 2; |
|||
pm_iowrite(0x74, byte); |
|||
printk_info("set power %s after power fail\n", on ? "on" : "off"); |
|||
#endif |
|||
#if 1 |
|||
printk_info("1\n"); |
|||
byte = pm_ioread(0x68); |
|||
byte &= ~(1 << 1); |
|||
/* 2.6 */ |
|||
byte |= 1 << 2; |
|||
pm_iowrite(0x68, byte); |
|||
|
|||
/* 2.6 */ |
|||
printk_info("2\n"); |
|||
byte = pm_ioread(0x65); |
|||
byte &= ~(1 << 7); |
|||
pm_iowrite(0x65, byte); |
|||
#endif |
|||
#if 1 |
|||
/* 2.16 */ |
|||
printk_info("2.16\n"); |
|||
byte = pm_ioread(0x55); |
|||
byte |= 1 << 5; |
|||
pm_iowrite(0x55, byte); |
|||
byte = pm_ioread(0xD7); |
|||
byte |= 1 << 6 | 1 << 1;; |
|||
pm_iowrite(0xD7, byte); |
|||
/* 2.15 */ |
|||
printk_info("2.15\n"); |
|||
byte = pm_ioread(0x42); |
|||
byte &= ~(1 << 2); |
|||
pm_iowrite(0x42, byte); |
|||
#if 0 |
|||
/* Set up NMI on errors */ |
|||
printk_info("set up NMI on errors\n"); |
|||
byte = INB(0xba000070); /* RTC70 */ |
|||
byte_old = byte; |
|||
//nmi_option = NMI_OFF;
|
|||
nmi_option = 0; |
|||
//get_option(&nmi_option, "nmi");
|
|||
if (nmi_option) { |
|||
byte &= ~(1 << 7); /* set NMI */ |
|||
printk_info("++++++++++set NMI+++++\n"); |
|||
} else { |
|||
byte |= (1 << 7); /* Can not mask NMI from PCI-E and NMI_NOW */ |
|||
printk_info("++++++++++no set NMI+++++\n"); |
|||
} |
|||
byte &= ~(1 << 7); |
|||
if (byte != byte_old) { |
|||
OUTB(byte, 0xba000070); |
|||
} |
|||
#endif |
|||
#endif |
|||
/* 2.10 IO Trap Settings */ |
|||
//try move later
|
|||
printk_info("IO Trap Setting\n"); |
|||
abcfg_reg(0x10090, 1 << 16, 1 << 16); |
|||
|
|||
/* ab index */ |
|||
printk_info("ab index\n"); |
|||
//pci_write_config32(dev, 0xF0, AB_INDX);
|
|||
pci_write_config32(dev, 0xF0, 0x00000cd8); |
|||
/* Initialize the real time clock */ |
|||
//rtc_init(0);
|
|||
|
|||
|
|||
/* 4.3 Enabling Upstream DMA Access */ |
|||
printk_info("Enabling Upstream DMA Access\n"); |
|||
axcfg_reg(0x04, 1 << 2, 1 << 2); //780
|
|||
|
|||
/*3.4 Enabling IDE/PCIB Prefetch for Performance Enhancement */ |
|||
printk_info("Enabling IDE/PCIB Prefetch for Performance Enhancement\n"); |
|||
abcfg_reg(0x10060, 9 << 17, 9 << 17); |
|||
abcfg_reg(0x10064, 9 << 17, 9 << 17); |
|||
|
|||
/* 3.5 Enabling OHCI Prefetch for Performance Enhancement */ |
|||
printk_info("Enabling OHCI Prefetch for Performance Enhancement\n"); |
|||
abcfg_reg(0x80, 1 << 0, 1<< 0); |
|||
|
|||
/* 3.6 B-Link Client's Credit Variable Settings for the Downstream Arbitration Equation */ |
|||
/* 3.7 Enabling Additional Address Bits Checking in Downstream */ |
|||
//abcfg_reg(0x9c, 3 << 0, 3 << 0);
|
|||
printk_info("Enabling Additional Address Bits Checking in Downstream\n"); |
|||
abcfg_reg(0x9c, 3 << 0 | 1 << 8, 3 << 0 | 1 << 8); |
|||
|
|||
/* Fix the bug of A-Link deadlock when operating in the extreme-stress test environment */ |
|||
abcfg_reg(0x9c, 1 << 8, 0 << 8); |
|||
|
|||
/* 3.8 Set B-Link Prefetch Mode */ |
|||
printk_info("Set B-Link Prefetch Mode\n"); |
|||
abcfg_reg(0x80, 3 << 1, 3 << 1); |
|||
|
|||
|
|||
/* 3.9 Enabling Detection of Upstream Interrupts */ |
|||
printk_info("Enabling Detection of Upstream Interrupts\n"); |
|||
abcfg_reg(0x94, 1 << 20 | 0x7FFFF,1 << 20 | 0x00FEE); |
|||
|
|||
/* 3.10: Enabling Downstream Posted Transactions to Pass Non-Posted
|
|||
* Transactions for the K8 Platform (for All Revisions) */ |
|||
printk_info("Enabling Downstream Posted Transactions to Pass Non-Posted\n"); |
|||
//try
|
|||
abcfg_reg(0x10090, 1 << 8, 1 << 8); |
|||
|
|||
/* 3.11:Programming Cycle Delay for AB and BIF Clock Gating */ |
|||
/* 3.12: Enabling AB and BIF Clock Gating */ |
|||
abcfg_reg(0x10054, 0xFFFF0000, 0x1040000); |
|||
abcfg_reg(0x54, 0xFF << 16, 4 << 16); |
|||
printk_info("3.11, ABCFG:0x54\n"); |
|||
abcfg_reg(0x54, 1 << 24, 1 << 24); |
|||
printk_info("3.12, ABCFG:0x54\n"); |
|||
abcfg_reg(0x98, 0x0000FF00, 0x00004700); |
|||
#if 0 |
|||
//lycheng
|
|||
abcfg_reg(0x10056, 0xFF << 0, 4 << 0); |
|||
printk_info("3.11, ABCFG:0x10056\n"); |
|||
abcfg_reg(0x10056, 1 << 8, 1 << 8); |
|||
printk_info("Set A-Link Prefetch Mode\n"); |
|||
abcfg_reg(0x1006c, 3 << 1, 3 << 1); |
|||
axindxc_reg(0x10, 9 << 1, 9 << 1); |
|||
axindxc_reg(0x21, 1 << 0, 1 << 0); |
|||
abcfg_reg(0x10050, 1 << 2, 1 << 2); |
|||
//end
|
|||
#endif |
|||
/* 4.13:Enabling AB Int_Arbiter Enhancement (for All Revisions) */ |
|||
printk_info("Enabling AB Int_Arbiter Enhancement\n"); |
|||
abcfg_reg(0x10054, 0x0000FFFF, 0x07FF); |
|||
#if 1 |
|||
/* 4.14:Enabling Requester ID for upstream traffic. */ |
|||
printk_info("Enabling Requester ID for upstream traffic\n"); |
|||
abcfg_reg(0x98, 1 << 16, 0 << 16); |
|||
#endif |
|||
|
|||
#if 1 |
|||
/* 9.2: Enableing IDE Data Bus DD7 Pull Down Resistor */ |
|||
printk_info("Enableing IDE Data Bus DD7 Pull Down Resistor\n"); |
|||
byte = pm2_ioread(0xE5); |
|||
byte |= 1 << 2; |
|||
pm2_iowrite(0xE5, byte); |
|||
/* Enable IDE controller. */ |
|||
printk_info("Enable IDE controller.\n"); |
|||
byte = pm_ioread(0x59); |
|||
byte &= ~(1 << 1); |
|||
pm_iowrite(0x59, byte); |
|||
#endif |
|||
|
|||
#if 1 |
|||
/* Enable NbSb virtual channel */ |
|||
printk_info("Enable NbSb virtual channel\n"); |
|||
axcfg_reg(0x114, 0x3f << 1, 0 << 1); |
|||
axcfg_reg(0x120, 0x7f << 1, 0x7f << 1); |
|||
axcfg_reg(0x120, 7 << 24, 1 << 24); |
|||
axcfg_reg(0x120, 1 << 31, 1 << 31); |
|||
abcfg_reg(0x50, 1 << 3, 1 << 3); |
|||
#endif |
|||
|
|||
//lycheng for debug 8259 interrupt
|
|||
#if 0 |
|||
printk_info("Shadow PIC register enable\n"); |
|||
dword = pci_read_config32(dev, 0x48); |
|||
dword |= 1 << 23; |
|||
pci_write_config32(dev, 0x48, dword); |
|||
#endif |
|||
printk_info("K8 INTR enable\n"); |
|||
dword = pci_read_config32(dev, 0x60); |
|||
dword |= 1 << 19; |
|||
pci_write_config32(dev, 0x60, dword); |
|||
|
|||
printk_info("Features enable\n"); |
|||
dword = pci_read_config32(dev, 0x64); |
|||
dword |= ((1 << 0)); |
|||
dword &= ~((1 << 3)|(1 << 7)); |
|||
pci_write_config32(dev, 0x64, dword); |
|||
|
|||
printk_info("INTAFix\n"); |
|||
dword = pci_read_config32(dev, 0xe0); |
|||
dword |= 1 << 11; |
|||
pci_write_config32(dev, 0xe0, dword); |
|||
//end lycheng
|
|||
|
|||
printk_info("sm_init() end\n"); |
|||
} |
|||
|
|||
@ -0,0 +1,68 @@ |
|||
/*
|
|||
* This file is part of the coreboot project. |
|||
* |
|||
* Copyright (C) 2008 Advanced Micro Devices, Inc. |
|||
* |
|||
* This program is free software; you can redistribute it and/or modify |
|||
* it under the terms of the GNU General Public License as published by |
|||
* the Free Software Foundation; version 2 of the License. |
|||
* |
|||
* This program is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* GNU General Public License for more details. |
|||
* |
|||
* You should have received a copy of the GNU General Public License |
|||
* along with this program; if not, write to the Free Software |
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
|||
*/ |
|||
|
|||
#include "sb700_smbus.h" |
|||
|
|||
static void alink_ab_indx(u32 reg_space, u32 reg_addr, |
|||
u32 mask, u32 val) |
|||
{ |
|||
u32 tmp; |
|||
|
|||
OUTL((reg_space & 0x3) << 30 | reg_addr, AB_INDX); |
|||
tmp = INL(AB_DATA); |
|||
|
|||
//add for sb700
|
|||
reg_addr & 0x10000 ? OUTL(0, AB_INDX) : NULL; |
|||
|
|||
tmp &= ~mask; |
|||
tmp |= val; |
|||
|
|||
/* printk_debug("about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */ |
|||
OUTL((reg_space & 0x3) << 30 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ |
|||
OUTL(tmp, AB_DATA); |
|||
|
|||
//add for sb700
|
|||
reg_addr & 0x10000 ? OUTL(0, AB_INDX) : NULL; |
|||
} |
|||
|
|||
/* space = 0: AX_INDXC, AX_DATAC
|
|||
* space = 1: AX_INDXP, AX_DATAP |
|||
*/ |
|||
static void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, |
|||
u32 mask, u32 val) |
|||
{ |
|||
u32 tmp; |
|||
|
|||
/* read axindc to tmp */ |
|||
OUTL(space << 30 | space << 3 | 0x30, AB_INDX); |
|||
OUTL(axindc, AB_DATA); |
|||
OUTL(space << 30 | space << 3 | 0x34, AB_INDX); |
|||
tmp = INL(AB_DATA); |
|||
|
|||
tmp &= ~mask; |
|||
tmp |= val; |
|||
|
|||
/* write tmp */ |
|||
OUTL(space << 30 | space << 3 | 0x30, AB_INDX); |
|||
OUTL(axindc, AB_DATA); |
|||
OUTL(space << 30 | space << 3 | 0x34, AB_INDX); |
|||
OUTL(tmp, AB_DATA); |
|||
} |
|||
|
|||
|
|||
@ -0,0 +1,60 @@ |
|||
/*
|
|||
* This file is part of the coreboot project. |
|||
* |
|||
* Copyright (C) 2008 Advanced Micro Devices, Inc. |
|||
* |
|||
* This program is free software; you can redistribute it and/or modify |
|||
* it under the terms of the GNU General Public License as published by |
|||
* the Free Software Foundation; version 2 of the License. |
|||
* |
|||
* This program is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* GNU General Public License for more details. |
|||
* |
|||
* You should have received a copy of the GNU General Public License |
|||
* along with this program; if not, write to the Free Software |
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
|||
*/ |
|||
|
|||
#ifndef SB700_SMBUS_H |
|||
#define SB700_SMBUS_H |
|||
|
|||
//#include <stdint.h>
|
|||
|
|||
#define SMBHSTSTAT 0x0 |
|||
#define SMBSLVSTAT 0x1 |
|||
#define SMBHSTCTRL 0x2 |
|||
#define SMBHSTCMD 0x3 |
|||
#define SMBHSTADDR 0x4 |
|||
#define SMBHSTDAT0 0x5 |
|||
#define SMBHSTDAT1 0x6 |
|||
#define SMBHSTBLKDAT 0x7 |
|||
|
|||
#define SMBSLVCTRL 0x8 |
|||
#define SMBSLVCMD_SHADOW 0x9 |
|||
#define SMBSLVEVT 0xa |
|||
#define SMBSLVDAT 0xc |
|||
|
|||
#define AX_INDXC 0 |
|||
#define AX_INDXP 1 |
|||
#define AXCFG 2 |
|||
#define ABCFG 3 |
|||
|
|||
/* Between 1-10 seconds, We should never timeout normally
|
|||
* Longer than this is just painful when a timeout condition occurs. |
|||
*/ |
|||
#define SMBUS_TIMEOUT (100*1000*10) |
|||
|
|||
#define abcfg_reg(reg, mask, val) \ |
|||
alink_ab_indx((ABCFG), (reg), (mask), (val)) |
|||
#define axcfg_reg(reg, mask, val) \ |
|||
alink_ab_indx((AXCFG), (reg), (mask), (val)) |
|||
#define axindxc_reg(reg, mask, val) \ |
|||
alink_ax_indx(0, (reg), (mask), (val)) |
|||
#define axindxp_reg(reg, mask, val) \ |
|||
alink_ax_indx(1, (reg), (mask), (val)) |
|||
|
|||
|
|||
#endif |
|||
|
|||
@ -0,0 +1,149 @@ |
|||
#include "sb700.h" |
|||
#include "rs780_cmn.h" |
|||
|
|||
|
|||
static void usb_init(device_t dev) |
|||
{ |
|||
u8 byte; |
|||
u16 word; |
|||
u32 dword; |
|||
device_t sm_dev; |
|||
//lycheng do in tgt_devinit()
|
|||
#if 1 |
|||
/* Enable OHCI0-4 and EHCI Controllers */ |
|||
printk_info("Enable OHCI0-4 and EHCI Controllers\n"); |
|||
//sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
|
|||
sm_dev = _pci_make_tag(0, 0x14, 0); |
|||
byte = pci_read_config8(sm_dev, 0x68); |
|||
//byte |= 0x3F;
|
|||
byte |= 0xFF; |
|||
pci_write_config8(sm_dev, 0x68, byte); |
|||
#endif |
|||
|
|||
#if 0 |
|||
#if 1 |
|||
/* RPR 5.2 Enables the USB PME Event,Enable USB resume support */ |
|||
byte = pm_ioread(0x61); |
|||
byte |= 1 << 6; |
|||
pm_iowrite(0x61, byte); |
|||
byte = pm_ioread(0x65); |
|||
byte |= 1 << 2; |
|||
pm_iowrite(0x65, byte); |
|||
|
|||
/* RPR 5.3 Support USB device wakeup from the S4/S5 state */ |
|||
byte = pm_ioread(0x65); |
|||
byte &= ~(1 << 0); |
|||
pm_iowrite(0x65, byte); |
|||
|
|||
/* RPR 5.6 Enable the USB controller to get reset by any software that generate a PCIRst# condition */ |
|||
byte = pm_ioread(0x65); |
|||
byte |= (1 << 4); |
|||
pm_iowrite(0x65, byte); |
|||
#endif |
|||
/* RPR 5.11 Disable OHCI MSI Capability */ |
|||
printk_info("Disable OHCI MSI Capability\n"); |
|||
word = pci_read_config16(dev, 0x40); |
|||
//word |= (0x1F << 8);
|
|||
word |= (0x3 << 8); |
|||
pci_write_config16(dev, 0x40, word); |
|||
|
|||
/* RPR 5.8 Disable the OHCI Dynamic Power Saving feature */ |
|||
printk("Disable the OHCI Dynamic Power Saving feature\n"); |
|||
dword = pci_read_config32(dev, 0x50); |
|||
//dword &= ~(1 << 16);
|
|||
dword |= (1 << 31); |
|||
pci_write_config32(dev, 0x50, dword); |
|||
#if 0 |
|||
/* Set a default latency timer. */ |
|||
pci_write_config8(dev, 0x0d, 0x40); //PCI_LATENCY_TIMER
|
|||
|
|||
byte = pci_read_config8(dev, 0x3d); //PCI_INTERRUPT_PIN
|
|||
if (byte) { |
|||
pci_write_config8(dev, 0x3c, 0); //PCI_INTERRUPT_LINE
|
|||
} |
|||
/* Set the cache line size, so far 64 bytes is good for everyone. */ |
|||
pci_write_config8(dev, 0x0c, 64 >> 2); //PCI_CACHE_LINE_SIZE
|
|||
/*enable io/memory space*/ |
|||
pci_write_config8(dev, 0x04, (1<<0|1<<1|1<<2)); |
|||
#endif |
|||
#endif |
|||
} |
|||
|
|||
static void usb_init2(device_t dev) |
|||
{ |
|||
u8 byte; |
|||
u16 word; |
|||
u32 dword; |
|||
u8 *usb2_bar0; |
|||
|
|||
#if 1 //because of disable usb, lycheng
|
|||
usb2_bar0 = (u8 *) (pci_read_config32(dev, 0x10) & ~0xFF); |
|||
printk_info("usb2_bar0=%p\n", usb2_bar0); |
|||
|
|||
/* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */ |
|||
dword = 0x00020F00; |
|||
WRITEL(dword, usb2_bar0 + 0xC0); |
|||
|
|||
/* RPR5.5 Sets In/OUT FIFO threshold for best performance */ |
|||
//dword = 0x00200040;
|
|||
dword = 0x00400040; |
|||
WRITEL(dword, usb2_bar0 + 0xA4); |
|||
#endif |
|||
/* RPR5.10 Disable EHCI MSI support */ |
|||
printk_info("Disable EHCI MSI support\n"); |
|||
byte = pci_read_config8(dev, 0x50); |
|||
byte |= (1 << 6); |
|||
pci_write_config8(dev, 0x50, byte); |
|||
|
|||
/* EHCI Dynamic Clock gating feature */ |
|||
dword = READL(usb2_bar0 + 0xbc); |
|||
dword &= ~(1 << 12); |
|||
WRITEL(dword, usb2_bar0 + 0xbc); |
|||
|
|||
|
|||
dword = pci_read_config32(dev, 0x50); |
|||
dword |= (1 << 7); |
|||
pci_write_config32(dev, 0x50, dword); |
|||
|
|||
/* RPR6.15 EHCI Async Park Mode */ |
|||
printk_info("EHCI Async Park Mode\n"); |
|||
dword = pci_read_config32(dev, 0x50); |
|||
dword |= (1 << 23); |
|||
pci_write_config32(dev, 0x50, dword); |
|||
|
|||
/* RPR6.11 Disabling EHCI Advance Asynchronous Enhancement */ |
|||
dword = pci_read_config32(dev, 0x50); |
|||
dword |= (1 << 3); |
|||
pci_write_config32(dev, 0x50, dword); |
|||
dword = pci_read_config32(dev, 0x50); |
|||
dword &= ~(1 << 28); |
|||
pci_write_config32(dev, 0x50, dword); |
|||
|
|||
/* USB Periodic cache setting */ |
|||
dword = pci_read_config32(dev, 0x50); |
|||
dword |= (1 << 8); |
|||
pci_write_config32(dev, 0x50, dword); |
|||
dword = pci_read_config32(dev, 0x50); |
|||
dword &= ~(1 << 27); |
|||
pci_write_config32(dev, 0x50, dword); |
|||
|
|||
#if 0 //because of disable usb, lycheng
|
|||
/* RPR6.17 Disable the EHCI Dynamic Power Saving feature */ |
|||
word = READL(usb2_bar0 + 0xBC); |
|||
word &= ~(1 << 12); |
|||
WRITEW(word, usb2_bar0 + 0xBC); |
|||
|
|||
/* Set a default latency timer. */ |
|||
pci_write_config8(dev, 0x0d, 0x40); //PCI_LATENCY_TIMER
|
|||
|
|||
byte = pci_read_config8(dev, 0x3d); //PCI_INTERRUPT_PIN
|
|||
if (byte) { |
|||
pci_write_config8(dev, 0x3c, 0); //PCI_INTERRUPT_LINE
|
|||
} |
|||
/* Set the cache line size, so far 64 bytes is good for everyone. */ |
|||
pci_write_config8(dev, 0x0c, 64 >> 2); //PCI_CACHE_LINE_SIZE
|
|||
/*enable io/memory space*/ |
|||
pci_write_config8(dev, 0x04, (1<<0|1<<1|1<<2)); |
|||
#endif |
|||
} |
|||
|
|||
@ -0,0 +1 @@ |
|||
zloader |
|||
@ -0,0 +1,7 @@ |
|||
TARGET=Bonito3a8780e |
|||
TARGETEL=Bonito |
|||
START=start.o |
|||
MEMSIZE=128 |
|||
ZLOADER_OPTIONS=-mips3 |
|||
|
|||
include Makefile.inc |
|||
Loading…
Reference in new issue