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1. Fix 3cserver fixup.S, delete no use one Fix a NODE2 windows problem that may cause core in NODE2 dead in speculation 

2. Fix 3Bserver fixup.S
   Set the HT0 link frequency to 800MHz
   Fix a NODE2 windows problem that may cause core in NODE2 dead in speculation
master
Wang Huandong 12 years ago
committed by wanghongmei
parent
e9e7f13130
commit
1b3cc3ff04
3 changed files with 4 additions and 290 deletions
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  1. 49
      Targets/Bonito3bserver/Bonito/loongson3_fixup_3b.S
  2. 200
      Targets/Bonito3cserver/Bonito/loongson3_fixup.S
  3. 45
      Targets/Bonito3cserver/Bonito/loongson3_fixup_3b.S

49
Targets/Bonito3bserver/Bonito/loongson3_fixup_3b.S
View File

@ -87,7 +87,7 @@
sw a1, 0x44(a0) sw a1, 0x44(a0)
###################### HT@CPU0 ###################### HT@CPU0
dli a0, 0x90000ffdfb000000 dli a0, 0x90000efdfb000000
//set 800 Mhz HT HOST //set 800 Mhz HT HOST
lw a1, 0x48(a0) lw a1, 0x48(a0)
li a2, 0x500 ##800Mhz li a2, 0x500 ##800Mhz
@ -103,7 +103,7 @@
sw a1, 0x44(a0) sw a1, 0x44(a0)
###################### Disconnect ###################### Disconnect
dli a0, 0x90000ffdfb000000 dli a0, 0x90000efdfb000000
//Disconnect HT BUS //Disconnect HT BUS
lw a1, 0x50(a0) lw a1, 0x50(a0)
li a2, 0x40000000 li a2, 0x40000000
@ -123,14 +123,6 @@
1: 1:
####### Unused HT0 port ######################### ####### Unused HT0 port #########################
#if 0
dli t0, 0x0000200000000000
sd t0, 0x28(t2)
dli t0, 0x0000200000000000
sd t0, 0x68(t2)
dli t0, 0x00002000000000f7
sd t0, 0xa8(t2)
#endif
dli t0, 0x00000c0000000000 dli t0, 0x00000c0000000000
sd t0, 0x30(t2) sd t0, 0x30(t2)
@ -158,14 +150,6 @@
dli t0, 0x00000c00000000f7 dli t0, 0x00000c00000000f7
sd t0, 0xa8(t2) sd t0, 0xa8(t2)
#if 0
dli t0, 0x0000200000000000
sd t0, 0x30(t2)
dli t0, 0x0000200000000000
sd t0, 0x70(t2)
dli t0, 0x00002000000000f7
sd t0, 0xb0(t2)
#endif
daddiu t2, t2, 0x100 daddiu t2, t2, 0x100
bne t2, t1, 1b bne t2, t1, 1b
@ -184,20 +168,11 @@
####### Unused HT0 port ######################### ####### Unused HT0 port #########################
dli t0, 0x00002c0000000000 dli t0, 0x00002c0000000000
sd t0, 0x28(t2) sd t0, 0x28(t2)
dli t0, 0xfffffc0000000000 dli t0, 0x00003c0000000000
sd t0, 0x68(t2) sd t0, 0x68(t2)
dli t0, 0x00003c00000000f4 dli t0, 0x00003c00000000f4
sd t0, 0xa8(t2) sd t0, 0xa8(t2)
#if 0
dli t0, 0x0000200000000000
sd t0, 0x30(t2)
dli t0, 0x0000200000000000
sd t0, 0x70(t2)
dli t0, 0x00002000000000f7
sd t0, 0xb0(t2)
#endif
daddiu t2, t2, 0x100 daddiu t2, t2, 0x100
bne t2, t1, 1b bne t2, t1, 1b
nop nop
@ -215,24 +190,6 @@
dli t0, 0x00002c00000000f7 dli t0, 0x00002c00000000f7
sd t0, 0xa8(t2) sd t0, 0xa8(t2)
/*
dli t0, 0x00000c0000000000
sd t0, 0x38(t2)
dli t0, 0x00000c0000000000
sd t0, 0x38(t2)
dli t0, 0x00001c00000000f4
sd t0, 0x38(t2)
*/
#if 0
dli t0, 0x0000200000000000
sd t0, 0x30(t2)
dli t0, 0x0000200000000000
sd t0, 0x70(t2)
dli t0, 0x00002000000000f7
sd t0, 0xb0(t2)
#endif
daddiu t2, t2, 0x100 daddiu t2, t2, 0x100
bne t2, t1, 1b bne t2, t1, 1b
nop nop

200
Targets/Bonito3cserver/Bonito/loongson3_fixup.S
View File

@ -1,200 +0,0 @@
/*whd : loongson3_fixup.S
used to fix up the potential addressing miss
caused by speculated execution
*/
#if 0
#set XBAR to route all the DMA request to Scache0
/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
THIS CONFIGURATION WILL AFFECT the Scache initilization,
The Scache init MUST BE rewrite when reconfiguared
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */
#define SINGLE_SCACHE
#ifdef SINGLE_SCACHE
dli a0,0xf #using 37:36
#else
dli a0,0x2 #using 11:10
#endif
dli t0,0x900000003ff00400
sd a0,0x0(t0)
#if 1//config L1 xbar cpu port
dli t2, 0x900000003ff02000
dli t1, 0x900000003ff02800
TTYDBG("Using Scache 0 \r\n")
1:
dli t0, 0x0000000000000000
sd t0, 0x38(t2)
dli t0, 0x0000000000000000
sd t0, 0x78(t2)
dli t0, 0x00000000000000f0
sd t0, 0xb8(t2)
#endif
PRINTSTR("Scache index setup done\r\n")
#endif
#ifdef MULTI_CHIP
#if 0
TTYDBG("HT0 frequency reconfig \r\n")
###################### HT@CPU1
dli a0, 0x90001cfdfb000000
//set 800 Mhz HT HOST
lw a1, 0x48(a0)
li a2, 0x500 ##800Mhz
or a1, a1, a2
sw a1, 0x48(a0)
//set 8 bit HT HOST
lw a1, 0x44(a0)
li a2, 0x88ffffff ##8bit mode
and a1, a1, a2 ##set to 8 bit mode
li a2, 0x11000000 ##16bit
or a1, a1, a2
sw a1, 0x44(a0)
###################### HT@CPU0
dli a0, 0x90000cfdfb000000
//set 800 Mhz HT HOST
lw a1, 0x48(a0)
li a2, 0x500 ##800Mhz
or a1, a1, a2 ##
sw a1, 0x48(a0)
//set 8 bit HT HOST
lw a1, 0x44(a0)
li a2, 0x88ffffff ##8bit mode
and a1, a1, a2 ##set to 8 bit mode
li a2, 0x11000000 ##16bit
or a1, a1, a2
sw a1, 0x44(a0)
###################### Disconnect
dli a0, 0x90000cfdfb000000
//Disconnect HT BUS
lw a1, 0x50(a0)
li a2, 0x40000000
or a1, a1, a2
sw a1, 0x50(a0)
##################################################
#endif
#endif
#if 1//config L1 xbar cpu port
dli t2, 0x900000003ff02000
dli t1, 0x900000003ff02400
TTYDBG("Fix L1xbar illegal access \r\n")
1:
####### Unused HT0 port #########################
dli t0, 0x0000200000000000
sd t0, 0x28(t2)
dli t0, 0x0000200000000000
sd t0, 0x68(t2)
dli t0, 0x00002000000000f4
sd t0, 0xa8(t2)
/*
dli t0, 0x0000200000000000
sd t0, 0x30(t2)
dli t0, 0x0000200000000000
sd t0, 0x70(t2)
dli t0, 0x00002000000000f7
sd t0, 0xb0(t2)
#ifndef MULTI_CHIP
####### address space to other nodes ############
dli t0, 0x0000100000000000
sd t0, 0x38(t2)
dli t0, 0x0000300000000000
sd t0, 0x78(t2)
dli t0, 0x00001000000000f7
sd t0, 0xb8(t2)
#endif
*/
dli t0, 0x0000080000000000
sd t0, 0x38(t2)
dli t0, 0x0000080000000000
sd t0, 0x78(t2)
dli t0, 0x00000800000000f4
sd t0, 0xb8(t2)
daddiu t2, t2, 0x100
bne t2, t1, 1b
nop
#endif
#if 1//config L1 xbar cpu port
TTYDBG("Fix L1xbar illegal access from core4 to core7\r\n")
dli t2, 0x900010003ff06000
dli t1, 0x900010003ff06500
1:
####### Unused HT0 port #########################
/*
dli t0, 0x00000c0000000000
sd t0, 0x28(t2)
dli t0, 0x00000c0000000000
sd t0, 0x68(t2)
dli t0, 0x00000c00000000f7
sd t0, 0xa8(t2)
*/
dli t0, 0x0000200000000000
sd t0, 0x30(t2)
dli t0, 0x0000200000000000
sd t0, 0x70(t2)
dli t0, 0x00002000000000f7
sd t0, 0xb0(t2)
dli t0, 0x0000080000000000
sd t0, 0x38(t2)
dli t0, 0x0000080000000000
sd t0, 0x78(t2)
dli t0, 0x00000800000000f7
sd t0, 0xb8(t2)
daddiu t2, t2, 0x100
bne t2, t1, 1b
nop
#endif
#if 1
############
TTYDBG("Fix L2xbar in NODE 0\r\n")
dli t2, 0x900000003ff00000
dli t0, 0xfffffffffff00000
sd t0, 0x40(t2)
dli t0, 0x000000001fc000f2
sd t0, 0x80(t2)
dli t0, 0x000000001fc00000
sd t0, 0x0(t2)
############ 0x10000000 Set to not allow Cache access #######
dli t0, 0x0000000010000082
sd t0, 0x88(t2)
sd $0, 0x90(t2)
#endif
TTYDBG("Fix L2xbar in NODE 1\r\n")
dli t2, 0x900010003ff04000
dli t0, 0x0000100010000000
sd t0, 0x08(t2)
dli t0, 0xfffffffff0000000
sd t0, 0x48(t2)
dli t0, 0x0000000010000082
sd t0, 0x88(t2)
sd $0, 0x80(t2)
sd $0, 0x90(t2)

45
Targets/Bonito3cserver/Bonito/loongson3_fixup_3b.S
View File

@ -106,14 +106,6 @@
1: 1:
####### Unused HT0 port ######################### ####### Unused HT0 port #########################
#if 0
dli t0, 0x0000200000000000
sd t0, 0x28(t2)
dli t0, 0x0000200000000000
sd t0, 0x68(t2)
dli t0, 0x00002000000000f7
sd t0, 0xa8(t2)
#endif
dli t0, 0x00000c0000000000 dli t0, 0x00000c0000000000
sd t0, 0x30(t2) sd t0, 0x30(t2)
@ -141,14 +133,6 @@
dli t0, 0x00000c00000000f7 dli t0, 0x00000c00000000f7
sd t0, 0xa8(t2) sd t0, 0xa8(t2)
#if 0
dli t0, 0x0000200000000000
sd t0, 0x30(t2)
dli t0, 0x0000200000000000
sd t0, 0x70(t2)
dli t0, 0x00002000000000f7
sd t0, 0xb0(t2)
#endif
daddiu t2, t2, 0x100 daddiu t2, t2, 0x100
bne t2, t1, 1b bne t2, t1, 1b
@ -167,20 +151,11 @@
####### Unused HT0 port ######################### ####### Unused HT0 port #########################
dli t0, 0x00002c0000000000 dli t0, 0x00002c0000000000
sd t0, 0x28(t2) sd t0, 0x28(t2)
dli t0, 0xfffffc0000000000 dli t0, 0x00003c0000000000
sd t0, 0x68(t2) sd t0, 0x68(t2)
dli t0, 0x00003c00000000f4 dli t0, 0x00003c00000000f4
sd t0, 0xa8(t2) sd t0, 0xa8(t2)
#if 0
dli t0, 0x0000200000000000
sd t0, 0x30(t2)
dli t0, 0x0000200000000000
sd t0, 0x70(t2)
dli t0, 0x00002000000000f7
sd t0, 0xb0(t2)
#endif
daddiu t2, t2, 0x100 daddiu t2, t2, 0x100
bne t2, t1, 1b bne t2, t1, 1b
nop nop
@ -198,24 +173,6 @@
dli t0, 0x00002c00000000f7 dli t0, 0x00002c00000000f7
sd t0, 0xa8(t2) sd t0, 0xa8(t2)
/*
dli t0, 0x00000c0000000000
sd t0, 0x38(t2)
dli t0, 0x00000c0000000000
sd t0, 0x38(t2)
dli t0, 0x00001c00000000f4
sd t0, 0x38(t2)
*/
#if 0
dli t0, 0x0000200000000000
sd t0, 0x30(t2)
dli t0, 0x0000200000000000
sd t0, 0x70(t2)
dli t0, 0x00002000000000f7
sd t0, 0xb0(t2)
#endif
daddiu t2, t2, 0x100 daddiu t2, t2, 0x100
bne t2, t1, 1b bne t2, t1, 1b
nop nop

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